From f1c7e388e61bd9ba2362032dd45c9ab91cf3882f Mon Sep 17 00:00:00 2001 From: "antonello.contini" Date: Tue, 25 Feb 2025 19:59:57 +0100 Subject: [PATCH 1/4] do not use pllsrc for i2s; added field for plli2ssrc selection --- embassy-stm32/src/rcc/f247.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 79d793dcc..7426b6792 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -4,6 +4,9 @@ pub use crate::pac::rcc::vals::{ Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, }; + +#[cfg(any(stm32f413, stm32f423, stm32f412))] +pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource; #[cfg(any(stm32f4, stm32f7))] use crate::pac::PWR; use crate::pac::{FLASH, RCC}; @@ -84,6 +87,8 @@ pub struct Config { pub sys: Sysclk, pub pll_src: PllSource, + #[cfg(any(stm32f413, stm32f423, stm32f412))] + pub plli2s_src: Plli2sSource, pub pll: Option, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] @@ -111,6 +116,8 @@ impl Default for Config { hse: None, sys: Sysclk::HSI, pll_src: PllSource::HSI, + #[cfg(any(stm32f413, stm32f423, stm32f412))] + plli2s_src: Plli2sSource::HSE_HSI, pll: None, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] plli2s: None, @@ -417,7 +424,7 @@ fn init_pll(instance: PllInstance, config: Option, input: &PllInput) -> Pll #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))] w.set_pllm(pll.prediv); #[cfg(any(stm32f412, stm32f413, stm32f423))] - w.set_pllsrc(input.source); + w.set_plli2ssrc(Plli2sSource::HSE_HSI); write_fields!(w); }), From 51085a5e949317a578e5253d8eaccf247ccc47cc Mon Sep 17 00:00:00 2001 From: "antonello.contini" Date: Tue, 25 Feb 2025 21:21:23 +0100 Subject: [PATCH 2/4] let user set external i2s clock frequency --- embassy-stm32/src/rcc/f247.rs | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 7426b6792..52d093609 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -89,6 +89,8 @@ pub struct Config { pub pll_src: PllSource, #[cfg(any(stm32f413, stm32f423, stm32f412))] pub plli2s_src: Plli2sSource, + #[cfg(any(stm32f412, stm32f413, stm32f423))] + pub external_clock: Option, pub pll: Option, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] @@ -118,6 +120,8 @@ impl Default for Config { pll_src: PllSource::HSI, #[cfg(any(stm32f413, stm32f423, stm32f412))] plli2s_src: Plli2sSource::HSE_HSI, + #[cfg(any(stm32f412, stm32f413, stm32f423))] + external_clock: None, pll: None, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] plli2s: None, @@ -192,6 +196,8 @@ pub(crate) unsafe fn init(config: Config) { let pll_input = PllInput { hse, hsi, + #[cfg(any(stm32f412, stm32f413, stm32f423))] + external: config.external_clock, source: config.pll_src, }; let pll = init_pll(PllInstance::Pll, config.pll, &pll_input); @@ -325,6 +331,8 @@ struct PllInput { source: PllSource, hsi: Option, hse: Option, + #[cfg(any(stm32f412, stm32f413, stm32f423))] + external: Option, } #[derive(Default)] @@ -369,10 +377,17 @@ fn init_pll(instance: PllInstance, config: Option, input: &PllInput) -> Pll let Some(pll) = config else { return PllOutput::default() }; + #[cfg(not(any(stm32f412, stm32f413, stm32f423)))] let pll_src = match input.source { PllSource::HSE => input.hse, PllSource::HSI => input.hsi, }; + #[cfg(any(stm32f412, stm32f413, stm32f423))] + let pll_src = match (input.source, input.external) { + (PllSource::HSE, None) => input.hse, + (PllSource::HSI, None) => input.hsi, + (_, Some(ext)) => Some(ext), + }; let pll_src = pll_src.unwrap(); @@ -424,7 +439,13 @@ fn init_pll(instance: PllInstance, config: Option, input: &PllInput) -> Pll #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))] w.set_pllm(pll.prediv); #[cfg(any(stm32f412, stm32f413, stm32f423))] - w.set_plli2ssrc(Plli2sSource::HSE_HSI); + { + let plli2ssource = match input.external { + Some(_) => Plli2sSource::EXTERNAL, + None => Plli2sSource::HSE_HSI, + }; + w.set_plli2ssrc(plli2ssource); + } write_fields!(w); }), From 724e1a34e57c283bc59068f3ac69f19bf3d2a72a Mon Sep 17 00:00:00 2001 From: "antonello.contini" Date: Tue, 25 Feb 2025 21:37:01 +0100 Subject: [PATCH 3/4] simpler configuration --- embassy-stm32/src/rcc/f247.rs | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 52d093609..8c5307409 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -87,10 +87,8 @@ pub struct Config { pub sys: Sysclk, pub pll_src: PllSource, - #[cfg(any(stm32f413, stm32f423, stm32f412))] - pub plli2s_src: Plli2sSource, #[cfg(any(stm32f412, stm32f413, stm32f423))] - pub external_clock: Option, + pub external_i2s_clock: Option, pub pll: Option, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] @@ -118,10 +116,8 @@ impl Default for Config { hse: None, sys: Sysclk::HSI, pll_src: PllSource::HSI, - #[cfg(any(stm32f413, stm32f423, stm32f412))] - plli2s_src: Plli2sSource::HSE_HSI, #[cfg(any(stm32f412, stm32f413, stm32f423))] - external_clock: None, + external_i2s_clock: None, pll: None, #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))] plli2s: None, @@ -197,7 +193,7 @@ pub(crate) unsafe fn init(config: Config) { hse, hsi, #[cfg(any(stm32f412, stm32f413, stm32f423))] - external: config.external_clock, + external: config.external_i2s_clock, source: config.pll_src, }; let pll = init_pll(PllInstance::Pll, config.pll, &pll_input); From 0c1601651bc04fcfb174002d50e1c86110e1bfff Mon Sep 17 00:00:00 2001 From: "antonello.contini" Date: Tue, 25 Feb 2025 22:02:23 +0100 Subject: [PATCH 4/4] cargo fmt --- embassy-stm32/src/rcc/f247.rs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 8c5307409..8ce9d5f5b 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -1,12 +1,11 @@ use stm32_metapac::flash::vals::Latency; +#[cfg(any(stm32f413, stm32f423, stm32f412))] +pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource; pub use crate::pac::rcc::vals::{ Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk, }; - -#[cfg(any(stm32f413, stm32f423, stm32f412))] -pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource; #[cfg(any(stm32f4, stm32f7))] use crate::pac::PWR; use crate::pac::{FLASH, RCC};