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nrf5340: add regh_voltage config
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@ -347,12 +347,33 @@ pub mod config {
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pub struct DcdcConfig {
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/// Config for the high voltage stage, if disabled LDO will be used.
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pub regh: bool,
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/// Configure the voltage of the high voltage stage. It is stored in non-volatile memory (UICR.VREGHVOUT register); pass None to not touch it.
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#[cfg(feature = "nrf5340-app-s")]
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pub regh_voltage: Option<ReghVoltage>,
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/// Config for the main rail, if disabled LDO will be used.
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pub regmain: bool,
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/// Config for the radio rail, if disabled LDO will be used.
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pub regradio: bool,
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}
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/// Output voltage setting for VREGH regulator stage.
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#[cfg(feature = "nrf5340-app-s")]
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pub enum ReghVoltage {
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/// 1.8 V
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_1V8 = 0,
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/// 2.1 V
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_2V1 = 1,
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/// 2.4 V
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_2V4 = 2,
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/// 2.7 V
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_2V7 = 3,
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/// 3.0 V
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_3V0 = 4,
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/// 3.3 V
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_3v3 = 5,
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//ERASED = 7, means 1.8V
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}
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/// Settings for enabling the built in DCDC converter.
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#[cfg(feature = "_nrf91")]
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pub struct DcdcConfig {
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@ -399,6 +420,8 @@ pub mod config {
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#[cfg(feature = "_nrf5340-app")]
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dcdc: DcdcConfig {
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regh: false,
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#[cfg(feature = "nrf5340-app-s")]
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regh_voltage: None,
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regmain: false,
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regradio: false,
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},
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@ -431,6 +454,7 @@ mod consts {
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#[allow(unused)]
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mod consts {
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pub const UICR_APPROTECT: *mut u32 = 0x00FF8000 as *mut u32;
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pub const UICR_VREGHVOUT: *mut u32 = 0x00FF8010 as *mut u32;
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pub const UICR_SECUREAPPROTECT: *mut u32 = 0x00FF801C as *mut u32;
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pub const UICR_NFCPINS: *mut u32 = 0x00FF8028 as *mut u32;
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pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
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@ -683,6 +707,21 @@ pub fn init(config: config::Config) -> Peripherals {
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}
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}
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#[cfg(feature = "nrf5340-app-s")]
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unsafe {
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if let Some(value) = config.dcdc.regh_voltage {
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let value = value as u32;
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let res = uicr_write_masked(consts::UICR_VREGHVOUT, value, 0b00000000_00000000_00000000_00000111);
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needs_reset |= res == WriteResult::Written;
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if res == WriteResult::Failed {
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warn!(
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"Failed to set regulator voltage, as UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
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To fix this, erase UICR manually, for example using `probe-rs erase` or `nrfjprog --eraseuicr`."
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);
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}
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}
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}
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if needs_reset {
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cortex_m::peripheral::SCB::sys_reset();
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}
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