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https://github.com/embassy-rs/embassy.git
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Merge pull request #3556 from chrenderle/low-power
low-power: add support for stm32u0
This commit is contained in:
commit
37111a891c
@ -70,6 +70,7 @@ use crate::rtc::Rtc;
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static mut EXECUTOR: Option<Executor> = None;
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static mut EXECUTOR: Option<Executor> = None;
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#[cfg(not(stm32u0))]
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foreach_interrupt! {
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foreach_interrupt! {
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(RTC, rtc, $block:ident, WKUP, $irq:ident) => {
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(RTC, rtc, $block:ident, WKUP, $irq:ident) => {
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#[interrupt]
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#[interrupt]
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@ -80,6 +81,17 @@ foreach_interrupt! {
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};
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};
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}
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}
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#[cfg(stm32u0)]
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foreach_interrupt! {
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(RTC, rtc, $block:ident, TAMP, $irq:ident) => {
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#[interrupt]
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#[allow(non_snake_case)]
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unsafe fn $irq() {
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EXECUTOR.as_mut().unwrap().on_wakeup_irq();
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}
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};
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}
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#[allow(dead_code)]
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#[allow(dead_code)]
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pub(crate) unsafe fn on_wakeup_irq() {
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pub(crate) unsafe fn on_wakeup_irq() {
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EXECUTOR.as_mut().unwrap().on_wakeup_irq();
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EXECUTOR.as_mut().unwrap().on_wakeup_irq();
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@ -112,10 +124,10 @@ pub enum StopMode {
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Stop2,
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Stop2,
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}
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}
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#[cfg(any(stm32l4, stm32l5, stm32u5))]
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#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
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use stm32_metapac::pwr::vals::Lpms;
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use stm32_metapac::pwr::vals::Lpms;
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#[cfg(any(stm32l4, stm32l5, stm32u5))]
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#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
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impl Into<Lpms> for StopMode {
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impl Into<Lpms> for StopMode {
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fn into(self) -> Lpms {
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fn into(self) -> Lpms {
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match self {
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match self {
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@ -186,7 +198,7 @@ impl Executor {
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#[allow(unused_variables)]
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#[allow(unused_variables)]
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fn configure_stop(&mut self, stop_mode: StopMode) {
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fn configure_stop(&mut self, stop_mode: StopMode) {
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#[cfg(any(stm32l4, stm32l5, stm32u5))]
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#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
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crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
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crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
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#[cfg(stm32h5)]
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#[cfg(stm32h5)]
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crate::pac::PWR.pmcr().modify(|v| {
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crate::pac::PWR.pmcr().modify(|v| {
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@ -159,6 +159,9 @@ impl LsConfig {
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} else {
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} else {
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None
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None
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};
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};
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#[cfg(rcc_u0)]
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let lse_sysen = Some(lse_en);
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_ = lse_drv; // not all chips have it.
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_ = lse_drv; // not all chips have it.
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// Disable backup domain write protection
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// Disable backup domain write protection
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@ -199,7 +202,7 @@ impl LsConfig {
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}
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}
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ok &= reg.lseon() == lse_en;
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ok &= reg.lseon() == lse_en;
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ok &= reg.lsebyp() == lse_byp;
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ok &= reg.lsebyp() == lse_byp;
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#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
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#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
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if let Some(lse_sysen) = lse_sysen {
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if let Some(lse_sysen) = lse_sysen {
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ok &= reg.lsesysen() == lse_sysen;
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ok &= reg.lsesysen() == lse_sysen;
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}
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}
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@ -251,7 +254,7 @@ impl LsConfig {
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while !bdcr().read().lserdy() {}
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while !bdcr().read().lserdy() {}
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#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
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#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
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if let Some(lse_sysen) = lse_sysen {
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if let Some(lse_sysen) = lse_sysen {
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bdcr().modify(|w| {
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bdcr().modify(|w| {
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w.set_lsesysen(lse_sysen);
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w.set_lsesysen(lse_sysen);
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@ -65,7 +65,9 @@ pub(crate) enum WakeupPrescaler {
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Div16 = 16,
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Div16 = 16,
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}
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}
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#[cfg(any(stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5))]
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#[cfg(any(
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stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
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))]
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impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
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impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
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fn from(val: WakeupPrescaler) -> Self {
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fn from(val: WakeupPrescaler) -> Self {
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use crate::pac::rtc::vals::Wucksel;
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use crate::pac::rtc::vals::Wucksel;
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@ -79,7 +81,9 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
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}
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}
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}
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}
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#[cfg(any(stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5))]
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#[cfg(any(
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stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
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))]
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impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
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impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
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fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
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fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
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use crate::pac::rtc::vals::Wucksel;
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use crate::pac::rtc::vals::Wucksel;
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@ -223,7 +227,7 @@ impl Rtc {
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<RTC as crate::rtc::SealedInstance>::WakeupInterrupt::unpend();
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<RTC as crate::rtc::SealedInstance>::WakeupInterrupt::unpend();
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unsafe { <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::enable() };
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unsafe { <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::enable() };
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#[cfg(not(stm32u5))]
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#[cfg(not(any(stm32u5, stm32u0)))]
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{
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{
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use crate::pac::EXTI;
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use crate::pac::EXTI;
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EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
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EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
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@ -285,7 +285,7 @@ trait SealedInstance {
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const BACKUP_REGISTER_COUNT: usize;
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const BACKUP_REGISTER_COUNT: usize;
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#[cfg(feature = "low-power")]
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#[cfg(feature = "low-power")]
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#[cfg(not(stm32u5))]
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#[cfg(not(any(stm32u5, stm32u0)))]
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const EXTI_WAKEUP_LINE: usize;
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const EXTI_WAKEUP_LINE: usize;
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#[cfg(feature = "low-power")]
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#[cfg(feature = "low-power")]
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@ -133,14 +133,20 @@ impl SealedInstance for crate::peripherals::RTC {
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cfg_if::cfg_if!(
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cfg_if::cfg_if!(
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if #[cfg(stm32g4)] {
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if #[cfg(stm32g4)] {
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const EXTI_WAKEUP_LINE: usize = 20;
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const EXTI_WAKEUP_LINE: usize = 20;
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type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
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} else if #[cfg(stm32g0)] {
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} else if #[cfg(stm32g0)] {
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const EXTI_WAKEUP_LINE: usize = 19;
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const EXTI_WAKEUP_LINE: usize = 19;
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type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
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} else if #[cfg(any(stm32l5, stm32h5))] {
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} else if #[cfg(any(stm32l5, stm32h5))] {
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const EXTI_WAKEUP_LINE: usize = 17;
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const EXTI_WAKEUP_LINE: usize = 17;
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type WakeupInterrupt = crate::interrupt::typelevel::RTC;
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}
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} else if #[cfg(stm32u5)] {
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);
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#[cfg(feature = "low-power")]
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cfg_if::cfg_if!(
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if #[cfg(stm32g4)] {
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type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
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} else if #[cfg(any(stm32g0, stm32u0))] {
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type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
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} else if #[cfg(any(stm32l5, stm32h5, stm32u5))] {
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type WakeupInterrupt = crate::interrupt::typelevel::RTC;
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type WakeupInterrupt = crate::interrupt::typelevel::RTC;
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}
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}
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);
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);
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