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Merge pull request #4493 from esden/stm32u5-ucpd-software-trim

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ucpd: Add software trim setting of the CC Rp/Rd for stm32u5 parts.
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Dario Nieuwenhuis 2025-08-02 16:45:12 +00:00 committed by GitHub
commit 3f457c0e77
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1 changed files with 31 additions and 0 deletions
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31
embassy-stm32/src/ucpd.rs
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@ -193,6 +193,18 @@ impl<'d, T: Instance> Ucpd<'d, T> {
});
}
// Software trim according to RM0456, p. 3480/3462
#[cfg(stm32u5)]
{
let trim_rd_cc1 = unsafe { *(0x0BFA_0544 as *const u8) & 0xF };
let trim_rd_cc2 = unsafe { *(0x0BFA_0546 as *const u8) & 0xF };
r.cfgr3().write(|w| {
w.set_trim_cc1_rd(trim_rd_cc1);
w.set_trim_cc2_rd(trim_rd_cc2);
});
}
Self {
cc_phy: CcPhy { _lifetime: PhantomData },
}
@ -314,6 +326,25 @@ impl<'d, T: Instance> CcPhy<'d, T> {
}
});
// Software trim according to RM0456, p. 3480/3462
#[cfg(stm32u5)]
T::REGS.cfgr3().modify(|w| match cc_pull {
CcPull::Source1_5A => {
let trim_1a5_cc1 = unsafe { *(0x0BFA_07A7 as *const u8) & 0xF };
let trim_1a5_cc2 = unsafe { *(0x0BFA_07A8 as *const u8) & 0xF };
w.set_trim_cc1_rp(trim_1a5_cc1);
w.set_trim_cc2_rp(trim_1a5_cc2);
}
_ => {
let trim_3a0_cc1 = unsafe { *(0x0BFA_0545 as *const u8) & 0xF };
let trim_3a0_cc2 = unsafe { *(0x0BFA_0547 as *const u8) & 0xF };
w.set_trim_cc1_rp(trim_3a0_cc1);
w.set_trim_cc2_rp(trim_3a0_cc2);
}
});
// Disable dead-battery pull-down resistors which are enabled by default on boot.
critical_section::with(|cs| {
init(