From 169f1ce928177a6ff85ce7e9ff5a995063b6aace Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 19:50:42 -0800
Subject: [PATCH 01/16] I believe that this enables the PLL clock input to
 different TIMs for the STM32F3xx Series of chips.

---
 embassy-stm32/src/rcc/f013.rs | 241 ++++++++++++++++++++++++++++++++++
 1 file changed, 241 insertions(+)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index c2933186c..0d2877755 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -74,6 +74,107 @@ pub enum HrtimClockSource {
     PllClk,
 }
 
+#[cfg(all(stm32f3, not(rcc_f37)))]
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum TimClockSource {
+    PClk2,
+    PllClk,
+}
+
+#[cfg(all(stm32f3, not(rcc_f37)))]
+#[derive(Clone, Copy)]
+pub struct TimClockSources {
+    pub tim1: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E)),
+    ))]
+    pub tim2: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E)),
+    ))]
+    pub tim34: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_B, package_C, package_D, package_E)),
+        stm32f358,
+    ))]
+    pub tim8: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
+    pub tim15: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
+    pub tim16: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
+    pub tim17: TimClockSource,
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+    ))]
+    pub tim20: TimClockSource
+}
+
+impl Default for TimClockSources {
+    fn default() -> Self {
+        Self {
+            tim1: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                all(stm32f302, any(package_D, package_E)),
+            ))]
+            tim2: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                all(stm32f302, any(package_D, package_E)),
+            ))]
+            tim34: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_B, package_C, package_D, package_E)),
+                stm32f358,
+            ))]
+            tim8: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                stm32f301,
+                stm32f318,
+                all(stm32f302, any(package_6, package_8))
+            ))]
+            tim15: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                stm32f301,
+                stm32f318,
+                all(stm32f302, any(package_6, package_8))
+            ))]
+            tim16: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                stm32f301,
+                stm32f318,
+                all(stm32f302, any(package_6, package_8))
+            ))]
+            tim17: TimClockSource::PClk2,
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+            ))]
+            tim20: TimClockSource::PClk2
+        }
+    }
+}
+
 /// Clocks configutation
 #[non_exhaustive]
 pub struct Config {
@@ -99,6 +200,8 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
+    #[cfg(not(stm32f37))]
+    pub tim: TimClockSources,
 
     pub ls: super::LsConfig,
 }
@@ -129,6 +232,8 @@ impl Default for Config {
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
+            #[cfg(not(stm32f37))]
+            tim: Default::default()
         }
     }
 }
@@ -364,6 +469,126 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    #[cfg(all(stm32f3, not(rcc_f37)))]
+    let tim1 = match config.tim.tim1 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim1(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    let tim2 = match config.tim.tim2 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim2(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    let tim34 = match config.tim.tim34 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim34(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+    let tim8 = match config.tim.tim8 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim8(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    let tim15 = match config.tim.tim15 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim15(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    let tim16 = match config.tim.tim16 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim16(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    let tim17 = match config.tim.tim17 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim17(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
+    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
+    let tim20 = match config.tim.tim20 {
+        TimClockSource::PClk2 => None,
+        TimClockSource::PllClk => {
+            use crate::pac::rcc::vals::Timsw;
+
+            let pll = unwrap!(pll);
+            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+            RCC.cfgr3().modify(|w| w.set_tim20(Timsw::PLL1_P));
+
+            Some(pll * 2u32)
+        }
+    };
+
     set_clocks!(
         hsi: hsi,
         hse: hse,
@@ -380,6 +605,22 @@ pub(crate) unsafe fn init(config: Config) {
         adc34: Some(adc34),
         #[cfg(stm32f334)]
         hrtim: hrtim,
+        #[cfg(all(stm32f3, not(rcc_f37)))]
+        tim1: tim1,
+        #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+        tim2: tim2,
+        #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+        tim34: tim34,
+        #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+        tim8: tim8,
+        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+        tim15: tim15,
+        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+        tim16: tim16,
+        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+        tim17: tim17,
+        #[cfg(any(all(stm32f303, any(package_D, package_E))))]
+        tim20: tim20,
         rtc: rtc,
         hsi48: hsi48,
         #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]

From 029d6383b56c45167b99ef5c5c862946410d8f52 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 20:02:25 -0800
Subject: [PATCH 02/16] Rust fmt and fix build.

---
 embassy-stm32/src/rcc/f013.rs | 97 ++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 52 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 0d2877755..766a4a0f5 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,20 +85,11 @@ pub enum TimClockSource {
 #[derive(Clone, Copy)]
 pub struct TimClockSources {
     pub tim1: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-    ))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
     pub tim2: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-    ))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
     pub tim34: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_B, package_C, package_D, package_E)),
-        stm32f358,
-    ))]
+    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
     pub tim8: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
@@ -121,30 +112,19 @@ pub struct TimClockSources {
         all(stm32f302, any(package_6, package_8))
     ))]
     pub tim17: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-    ))]
-    pub tim20: TimClockSource
+    #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+    pub tim20: TimClockSource,
 }
 
 impl Default for TimClockSources {
     fn default() -> Self {
         Self {
             tim1: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-            ))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
             tim2: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-            ))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
             tim34: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_B, package_C, package_D, package_E)),
-                stm32f358,
-            ))]
+            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
             tim8: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
@@ -167,10 +147,8 @@ impl Default for TimClockSources {
                 all(stm32f302, any(package_6, package_8))
             ))]
             tim17: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-            ))]
-            tim20: TimClockSource::PClk2
+            #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+            tim20: TimClockSource::PClk2,
         }
     }
 }
@@ -233,7 +211,7 @@ impl Default for Config {
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
             #[cfg(not(stm32f37))]
-            tim: Default::default()
+            tim: Default::default(),
         }
     }
 }
@@ -476,9 +454,9 @@ pub(crate) unsafe fn init(config: Config) {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim1(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim1sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
@@ -491,9 +469,9 @@ pub(crate) unsafe fn init(config: Config) {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim2(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim2sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
@@ -506,9 +484,9 @@ pub(crate) unsafe fn init(config: Config) {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim34(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim34sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
@@ -521,54 +499,69 @@ pub(crate) unsafe fn init(config: Config) {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim8(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim8sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
     let tim15 = match config.tim.tim15 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim15(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim15sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
     let tim16 = match config.tim.tim16 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim16(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim16sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        stm32f301,
+        stm32f318,
+        all(stm32f302, any(package_6, package_8))
+    ))]
     let tim17 = match config.tim.tim17 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim17(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim17sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }
@@ -581,9 +574,9 @@ pub(crate) unsafe fn init(config: Config) {
             use crate::pac::rcc::vals::Timsw;
 
             let pll = unwrap!(pll);
-            assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
 
-            RCC.cfgr3().modify(|w| w.set_tim20(Timsw::PLL1_P));
+            RCC.cfgr3().modify(|w| w.set_tim20sw(Timsw::PLL1_P));
 
             Some(pll * 2u32)
         }

From 4408c169a5c3961f1a5163ce6c09762988c1a471 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 22:53:00 -0800
Subject: [PATCH 03/16] Fix cfg lines

---
 embassy-stm32/src/rcc/f013.rs | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 766a4a0f5..b5ec8585e 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -116,6 +116,7 @@ pub struct TimClockSources {
     pub tim20: TimClockSource,
 }
 
+#[cfg(all(stm32f3, not(rcc_f37)))]
 impl Default for TimClockSources {
     fn default() -> Self {
         Self {
@@ -178,7 +179,7 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
-    #[cfg(not(stm32f37))]
+    #[cfg(all(stm32f3, not(stm32f37)))]
     pub tim: TimClockSources,
 
     pub ls: super::LsConfig,
@@ -210,7 +211,7 @@ impl Default for Config {
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
-            #[cfg(not(stm32f37))]
+            #[cfg(all(stm32f3, not(stm32f37)))]
             tim: Default::default(),
         }
     }

From 56b345c722aa22e778eb8551c4d019441bf5520e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:12:18 -0800
Subject: [PATCH 04/16] Clean up register setting

---
 embassy-stm32/src/rcc/f013.rs | 118 +++++++---------------------------
 1 file changed, 23 insertions(+), 95 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index b5ec8585e..2352b057d 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -179,7 +179,7 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
-    #[cfg(all(stm32f3, not(stm32f37)))]
+    #[cfg(all(stm32f3, not(rcc_f37)))]
     pub tim: TimClockSources,
 
     pub ls: super::LsConfig,
@@ -449,62 +449,34 @@ pub(crate) unsafe fn init(config: Config) {
     };
 
     #[cfg(all(stm32f3, not(rcc_f37)))]
-    let tim1 = match config.tim.tim1 {
-        TimClockSource::PClk2 => None,
+    match config.tim.tim1 {
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim1sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
-    let tim2 = match config.tim.tim2 {
-        TimClockSource::PClk2 => None,
+    match config.tim.tim2 {
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim2sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
-    let tim34 = match config.tim.tim34 {
-        TimClockSource::PClk2 => None,
+    match config.tim.tim34 {
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim34sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
-    let tim8 = match config.tim.tim8 {
-        TimClockSource::PClk2 => None,
+    match config.tim.tim8 {
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim8sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -514,17 +486,10 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f318,
         all(stm32f302, any(package_6, package_8))
     ))]
-    let tim15 = match config.tim.tim15 {
+    match config.tim.tim15 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim15sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -534,17 +499,10 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f318,
         all(stm32f302, any(package_6, package_8))
     ))]
-    let tim16 = match config.tim.tim16 {
+    match config.tim.tim16 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim16sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -554,34 +512,20 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f318,
         all(stm32f302, any(package_6, package_8))
     ))]
-    let tim17 = match config.tim.tim17 {
+    match config.tim.tim17 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim17sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
-    };
+    }
 
     #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-    let tim20 = match config.tim.tim20 {
+    match config.tim.tim20 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            use crate::pac::rcc::vals::Timsw;
-
-            let pll = unwrap!(pll);
-            assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
-            RCC.cfgr3().modify(|w| w.set_tim20sw(Timsw::PLL1_P));
-
-            Some(pll * 2u32)
+            RCC.cfgr3().modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
-    };
+    }
 
     set_clocks!(
         hsi: hsi,
@@ -599,22 +543,6 @@ pub(crate) unsafe fn init(config: Config) {
         adc34: Some(adc34),
         #[cfg(stm32f334)]
         hrtim: hrtim,
-        #[cfg(all(stm32f3, not(rcc_f37)))]
-        tim1: tim1,
-        #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
-        tim2: tim2,
-        #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
-        tim34: tim34,
-        #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
-        tim8: tim8,
-        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
-        tim15: tim15,
-        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
-        tim16: tim16,
-        #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
-        tim17: tim17,
-        #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-        tim20: tim20,
         rtc: rtc,
         hsi48: hsi48,
         #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]

From d28ba1d60689e5a0d5623c5ea4890663d899523a Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:16:17 -0800
Subject: [PATCH 05/16] rustfmt

---
 embassy-stm32/src/rcc/f013.rs | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 2352b057d..17c734f09 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -204,14 +204,13 @@ impl Default for Config {
             // ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
             adc_pre: ADCPrescaler::DIV6,
 
-
             #[cfg(all(stm32f3, not(rcc_f37)))]
             adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
-            #[cfg(all(stm32f3, not(stm32f37)))]
+            #[cfg(all(stm32f3, not(rcc_f37)))]
             tim: Default::default(),
         }
     }
@@ -450,33 +449,37 @@ pub(crate) unsafe fn init(config: Config) {
 
     #[cfg(all(stm32f3, not(rcc_f37)))]
     match config.tim.tim1 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
     match config.tim.tim2 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
     match config.tim.tim34 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
     #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
     match config.tim.tim8 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -489,7 +492,8 @@ pub(crate) unsafe fn init(config: Config) {
     match config.tim.tim15 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -502,7 +506,8 @@ pub(crate) unsafe fn init(config: Config) {
     match config.tim.tim16 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     };
 
@@ -515,7 +520,8 @@ pub(crate) unsafe fn init(config: Config) {
     match config.tim.tim17 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     }
 
@@ -523,7 +529,8 @@ pub(crate) unsafe fn init(config: Config) {
     match config.tim.tim20 {
         TimClockSource::PClk2 => None,
         TimClockSource::PllClk => {
-            RCC.cfgr3().modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+            RCC.cfgr3()
+                .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
         }
     }
 

From d7623c79291cfba562f9881e062180d5c92b875e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:20:35 -0800
Subject: [PATCH 06/16] Remove extraneous , in cfg

---
 embassy-stm32/src/rcc/f013.rs | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 17c734f09..4d5116a56 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,11 +85,11 @@ pub enum TimClockSource {
 #[derive(Clone, Copy)]
 pub struct TimClockSources {
     pub tim1: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
     pub tim2: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
     pub tim34: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
+    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
     pub tim8: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
@@ -112,7 +112,7 @@ pub struct TimClockSources {
         all(stm32f302, any(package_6, package_8))
     ))]
     pub tim17: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
     pub tim20: TimClockSource,
 }
 
@@ -121,11 +121,11 @@ impl Default for TimClockSources {
     fn default() -> Self {
         Self {
             tim1: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
             tim2: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
             tim34: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
+            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
             tim8: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
@@ -148,7 +148,7 @@ impl Default for TimClockSources {
                 all(stm32f302, any(package_6, package_8))
             ))]
             tim17: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E))))]
             tim20: TimClockSource::PClk2,
         }
     }

From 370db9fb06862695433c9314585a492d8c1684ae Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:39:23 -0800
Subject: [PATCH 07/16] Update f013.rs

Add stm32f398
---
 embassy-stm32/src/rcc/f013.rs | 45 +++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 18 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 4d5116a56..3f1b88e5c 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,31 +85,34 @@ pub enum TimClockSource {
 #[derive(Clone, Copy)]
 pub struct TimClockSources {
     pub tim1: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
     pub tim2: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
     pub tim34: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
     pub tim8: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     pub tim15: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     pub tim16: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     pub tim17: TimClockSource,
     #[cfg(any(all(stm32f303, any(package_D, package_E))))]
@@ -121,31 +124,34 @@ impl Default for TimClockSources {
     fn default() -> Self {
         Self {
             tim1: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
             tim2: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
             tim34: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
             tim8: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
                 stm32f301,
                 stm32f318,
-                all(stm32f302, any(package_6, package_8))
+                all(stm32f302, any(package_6, package_8)),
+                stm32f398
             ))]
             tim15: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
                 stm32f301,
                 stm32f318,
-                all(stm32f302, any(package_6, package_8))
+                all(stm32f302, any(package_6, package_8)),
+                stm32f398
             ))]
             tim16: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
                 stm32f301,
                 stm32f318,
-                all(stm32f302, any(package_6, package_8))
+                all(stm32f302, any(package_6, package_8)),
+                stm32f398
             ))]
             tim17: TimClockSource::PClk2,
             #[cfg(any(all(stm32f303, any(package_D, package_E))))]
@@ -456,7 +462,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
     match config.tim.tim2 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
@@ -465,7 +471,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
     match config.tim.tim34 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
@@ -474,7 +480,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
     match config.tim.tim8 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
@@ -487,7 +493,8 @@ pub(crate) unsafe fn init(config: Config) {
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     match config.tim.tim15 {
         TimClockSource::PClk2 => None,
@@ -501,7 +508,8 @@ pub(crate) unsafe fn init(config: Config) {
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     match config.tim.tim16 {
         TimClockSource::PClk2 => None,
@@ -515,7 +523,8 @@ pub(crate) unsafe fn init(config: Config) {
         all(stm32f303, any(package_D, package_E)),
         stm32f301,
         stm32f318,
-        all(stm32f302, any(package_6, package_8))
+        all(stm32f302, any(package_6, package_8)),
+        stm32f398
     ))]
     match config.tim.tim17 {
         TimClockSource::PClk2 => None,

From 77739faaeb155478d3d50e7b8a3add79b5e94222 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:42:19 -0800
Subject: [PATCH 08/16] Rustfmt

---
 embassy-stm32/src/rcc/f013.rs | 54 +++++++++++++++++++++++++++++------
 1 file changed, 45 insertions(+), 9 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 3f1b88e5c..1a0e34614 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,11 +85,23 @@ pub enum TimClockSource {
 #[derive(Clone, Copy)]
 pub struct TimClockSources {
     pub tim1: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E))
+        stm32f398
+    ))]
     pub tim2: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E)),
+        stm32f398
+    ))]
     pub tim34: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_B, package_C, package_D, package_E)),
+        stm32f358,
+        stm32f398
+    ))]
     pub tim8: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
@@ -124,11 +136,23 @@ impl Default for TimClockSources {
     fn default() -> Self {
         Self {
             tim1: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                all(stm32f302, any(package_D, package_E)),
+                stm32f398
+            ))]
             tim2: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+            #[cfg(any(
+                all(stm32f303, any(package_D, package_E)),
+                all(stm32f302, any(package_D, package_E)),
+                stm32f398
+            ))]
             tim34: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+            #[cfg(any(
+                all(stm32f303, any(package_B, package_C, package_D, package_E)),
+                stm32f358,
+                stm32f398
+            ))]
             tim8: TimClockSource::PClk2,
             #[cfg(any(
                 all(stm32f303, any(package_D, package_E)),
@@ -462,7 +486,11 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E)),
+        stm32f398
+    ))]
     match config.tim.tim2 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
@@ -471,7 +499,11 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_D, package_E)),
+        all(stm32f302, any(package_D, package_E)),
+        stm32f398
+    ))]
     match config.tim.tim34 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
@@ -480,7 +512,11 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+    #[cfg(any(
+        all(stm32f303, any(package_B, package_C, package_D, package_E)),
+        stm32f358,
+        stm32f398
+    ))]
     match config.tim.tim8 {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {

From 7592e8be6e40dc6be655bcf011f3ce2aee5b9743 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:45:58 -0800
Subject: [PATCH 09/16] Fix build

---
 embassy-stm32/src/rcc/f013.rs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 1a0e34614..8ceae6a8a 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -495,7 +495,7 @@ pub(crate) unsafe fn init(config: Config) {
         TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
             RCC.cfgr3()
-                .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+                .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
         }
     };
 
@@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim15 {
-        TimClockSource::PClk2 => None,
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim16 {
-        TimClockSource::PClk2 => None,
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim17 {
-        TimClockSource::PClk2 => None,
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     #[cfg(any(all(stm32f303, any(package_D, package_E))))]
     match config.tim.tim20 {
-        TimClockSource::PClk2 => None,
+        TimClockSource::PClk2 => {},
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));

From c99c4a01a99d953805f11bf838c9f6c0b5338fae Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:47:38 -0800
Subject: [PATCH 10/16] Update f013.rs

---
 embassy-stm32/src/rcc/f013.rs | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 8ceae6a8a..02c3425d1 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -87,7 +87,7 @@ pub struct TimClockSources {
     pub tim1: TimClockSource,
     #[cfg(any(
         all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E))
+        all(stm32f302, any(package_D, package_E)),
         stm32f398
     ))]
     pub tim2: TimClockSource,
@@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim15 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim16 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
         stm32f398
     ))]
     match config.tim.tim17 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     #[cfg(any(all(stm32f303, any(package_D, package_E))))]
     match config.tim.tim20 {
-        TimClockSource::PClk2 => {},
+        TimClockSource::PClk2 => {}
         TimClockSource::PllClk => {
             RCC.cfgr3()
                 .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));

From e99ef496116b4cdfa0dd0706ac1bfc600f45c97b Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 19:56:07 -0800
Subject: [PATCH 11/16] Move to auto-generated based system.

---
 embassy-stm32/build.rs                |  69 ++++++++
 embassy-stm32/src/rcc/f013.rs         | 221 +-------------------------
 examples/stm32f3/src/bin/usart_dma.rs |   4 +-
 3 files changed, 78 insertions(+), 216 deletions(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index ee88d4541..f45a571f2 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -430,6 +430,8 @@ fn main() {
 
     let mut clock_names = BTreeSet::new();
 
+    let mut rcc_cfgr_regs = BTreeMap::new();
+
     for p in METADATA.peripherals {
         if !singletons.contains(&p.name.to_string()) {
             continue;
@@ -508,6 +510,16 @@ fn main() {
                     let field_name = format_ident!("{}", field_name);
                     let enum_name = format_ident!("{}", enum_name);
 
+                    if !rcc_cfgr_regs.contains_key(mux.register) {
+                        rcc_cfgr_regs.insert(mux.register, Vec::new());
+                    }
+
+                    rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
+                        fieldset_name.clone(),
+                        field_name.clone(),
+                        enum_name.clone(),
+                    ));
+
                     let match_arms: TokenStream = enumm
                         .variants
                         .iter()
@@ -590,6 +602,63 @@ fn main() {
         }
     }
 
+    for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
+        println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
+
+        let struct_fields: Vec<_> = fields
+            .iter()
+            .map(|(_fieldset, fieldname, enum_name)| {
+                quote! {
+                    pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
+                }
+            })
+            .collect();
+
+        let field_names: Vec<_> = fields
+            .iter()
+            .map(|(_fieldset, fieldname, _enum_name)| fieldname)
+            .collect();
+
+        let inits: Vec<_> = fields
+            .iter()
+            .map(|(fieldset, fieldname, _enum_name)| {
+                let setter = format_ident!("set_{}", fieldname);
+                quote! {
+                    match self.#fieldname {
+                        None => {}
+                        Some(val) => {
+                            crate::pac::RCC.#fieldset()
+                                .modify(|w| w.#setter(val));
+                        }
+                    };
+                }
+            })
+            .collect();
+
+        let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
+
+        g.extend(quote! {
+            #[derive(Clone, Copy)]
+            pub struct #cfgr_reg {
+                #( #struct_fields, )*
+            }
+
+            impl Default for #cfgr_reg {
+                fn default() -> Self {
+                    Self {
+                        #( #field_names: None, )*
+                    }
+                }
+            }
+
+            impl #cfgr_reg {
+                pub fn init(self) {
+                    #( #inits )*
+                }
+            }
+        });
+    }
+
     // Generate RCC
     clock_names.insert("sys".to_string());
     clock_names.insert("rtc".to_string());
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 02c3425d1..a61aae0e8 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -74,116 +74,6 @@ pub enum HrtimClockSource {
     PllClk,
 }
 
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy, PartialEq, Eq)]
-pub enum TimClockSource {
-    PClk2,
-    PllClk,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy)]
-pub struct TimClockSources {
-    pub tim1: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    pub tim2: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    pub tim34: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_B, package_C, package_D, package_E)),
-        stm32f358,
-        stm32f398
-    ))]
-    pub tim8: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim15: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim16: TimClockSource,
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    pub tim17: TimClockSource,
-    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-    pub tim20: TimClockSource,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-impl Default for TimClockSources {
-    fn default() -> Self {
-        Self {
-            tim1: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-                stm32f398
-            ))]
-            tim2: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                all(stm32f302, any(package_D, package_E)),
-                stm32f398
-            ))]
-            tim34: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_B, package_C, package_D, package_E)),
-                stm32f358,
-                stm32f398
-            ))]
-            tim8: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim15: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim16: TimClockSource::PClk2,
-            #[cfg(any(
-                all(stm32f303, any(package_D, package_E)),
-                stm32f301,
-                stm32f318,
-                all(stm32f302, any(package_6, package_8)),
-                stm32f398
-            ))]
-            tim17: TimClockSource::PClk2,
-            #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-            tim20: TimClockSource::PClk2,
-        }
-    }
-}
-
 /// Clocks configutation
 #[non_exhaustive]
 pub struct Config {
@@ -209,8 +99,8 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
-    #[cfg(all(stm32f3, not(rcc_f37)))]
-    pub tim: TimClockSources,
+    #[cfg(cfgr3)]
+    pub cfgr3: crate::_generated::CFGR3,
 
     pub ls: super::LsConfig,
 }
@@ -240,8 +130,8 @@ impl Default for Config {
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
-            #[cfg(all(stm32f3, not(rcc_f37)))]
-            tim: Default::default(),
+            #[cfg(cfgr3)]
+            cfgr3: Default::default(),
         }
     }
 }
@@ -477,107 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(all(stm32f3, not(rcc_f37)))]
-    match config.tim.tim1 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    match config.tim.tim2 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        all(stm32f302, any(package_D, package_E)),
-        stm32f398
-    ))]
-    match config.tim.tim34 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_B, package_C, package_D, package_E)),
-        stm32f358,
-        stm32f398
-    ))]
-    match config.tim.tim8 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim15 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim16 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    };
-
-    #[cfg(any(
-        all(stm32f303, any(package_D, package_E)),
-        stm32f301,
-        stm32f318,
-        all(stm32f302, any(package_6, package_8)),
-        stm32f398
-    ))]
-    match config.tim.tim17 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    }
-
-    #[cfg(any(all(stm32f303, any(package_D, package_E))))]
-    match config.tim.tim20 {
-        TimClockSource::PClk2 => {}
-        TimClockSource::PllClk => {
-            RCC.cfgr3()
-                .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
-        }
-    }
+    #[cfg(cfgr3)]
+    config.cfgr3.init();
 
     set_clocks!(
         hsi: hsi,
diff --git a/examples/stm32f3/src/bin/usart_dma.rs b/examples/stm32f3/src/bin/usart_dma.rs
index 5234e53b9..7dc905adc 100644
--- a/examples/stm32f3/src/bin/usart_dma.rs
+++ b/examples/stm32f3/src/bin/usart_dma.rs
@@ -17,7 +17,9 @@ bind_interrupts!(struct Irqs {
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let p = embassy_stm32::init(Default::default());
+    let mut init_config = embassy_stm32::Config::default();
+    init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
+    let p = embassy_stm32::init(init_config);
     info!("Hello World!");
 
     let config = Config::default();

From 2ee9b373738cf78cf784bf8753a7f55568f85d9b Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:54:35 -0800
Subject: [PATCH 12/16] Move to a single Mux Struct.

---
 embassy-stm32/build.rs        | 26 ++++++++++----------------
 embassy-stm32/src/rcc/f013.rs | 12 ++++++------
 embassy-stm32/src/rcc/mod.rs  |  2 ++
 3 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index f45a571f2..2ffbadfc3 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -430,7 +430,7 @@ fn main() {
 
     let mut clock_names = BTreeSet::new();
 
-    let mut rcc_cfgr_regs = BTreeMap::new();
+    let mut rcc_cfgr_regs = BTreeSet::new();
 
     for p in METADATA.peripherals {
         if !singletons.contains(&p.name.to_string()) {
@@ -510,11 +510,7 @@ fn main() {
                     let field_name = format_ident!("{}", field_name);
                     let enum_name = format_ident!("{}", enum_name);
 
-                    if !rcc_cfgr_regs.contains_key(mux.register) {
-                        rcc_cfgr_regs.insert(mux.register, Vec::new());
-                    }
-
-                    rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
+                    rcc_cfgr_regs.insert((
                         fieldset_name.clone(),
                         field_name.clone(),
                         enum_name.clone(),
@@ -602,10 +598,10 @@ fn main() {
         }
     }
 
-    for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
-        println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
+    if !rcc_cfgr_regs.is_empty() {
+        println!("cargo:rustc-cfg=clock_mux");
 
-        let struct_fields: Vec<_> = fields
+        let struct_fields: Vec<_> = rcc_cfgr_regs
             .iter()
             .map(|(_fieldset, fieldname, enum_name)| {
                 quote! {
@@ -614,12 +610,12 @@ fn main() {
             })
             .collect();
 
-        let field_names: Vec<_> = fields
+        let field_names: Vec<_> = rcc_cfgr_regs
             .iter()
             .map(|(_fieldset, fieldname, _enum_name)| fieldname)
             .collect();
 
-        let inits: Vec<_> = fields
+        let inits: Vec<_> = rcc_cfgr_regs
             .iter()
             .map(|(fieldset, fieldname, _enum_name)| {
                 let setter = format_ident!("set_{}", fieldname);
@@ -635,15 +631,13 @@ fn main() {
             })
             .collect();
 
-        let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
-
         g.extend(quote! {
             #[derive(Clone, Copy)]
-            pub struct #cfgr_reg {
+            pub struct ClockMux {
                 #( #struct_fields, )*
             }
 
-            impl Default for #cfgr_reg {
+            impl Default for ClockMux {
                 fn default() -> Self {
                     Self {
                         #( #field_names: None, )*
@@ -651,7 +645,7 @@ fn main() {
                 }
             }
 
-            impl #cfgr_reg {
+            impl ClockMux {
                 pub fn init(self) {
                     #( #inits )*
                 }
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index a61aae0e8..86af4bd68 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -99,8 +99,8 @@ pub struct Config {
     pub adc34: AdcClockSource,
     #[cfg(stm32f334)]
     pub hrtim: HrtimClockSource,
-    #[cfg(cfgr3)]
-    pub cfgr3: crate::_generated::CFGR3,
+    #[cfg(clock_mux)]
+    pub mux: crate::rcc::ClockMux,
 
     pub ls: super::LsConfig,
 }
@@ -130,8 +130,8 @@ impl Default for Config {
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(stm32f334)]
             hrtim: HrtimClockSource::BusClk,
-            #[cfg(cfgr3)]
-            cfgr3: Default::default(),
+            #[cfg(clock_mux)]
+            mux: Default::default(),
         }
     }
 }
@@ -367,8 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(cfgr3)]
-    config.cfgr3.init();
+    #[cfg(clock_mux)]
+    config.mux.init();
 
     set_clocks!(
         hsi: hsi,
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 0f3467151..f71211925 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,6 +32,8 @@ mod _version;
 pub use _version::*;
 
 pub use crate::_generated::Clocks;
+#[cfg(clock_mux)]
+pub use crate::_generated::ClockMux;
 
 #[cfg(feature = "low-power")]
 /// Must be written within a critical section

From 95056958300d92b34d5f8f77c7429894efbc0fa1 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:55:05 -0800
Subject: [PATCH 13/16] Move compile test to the STM32F334 example.

---
 examples/stm32f3/src/bin/usart_dma.rs | 4 +---
 examples/stm32f334/src/bin/pwm.rs     | 1 +
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/examples/stm32f3/src/bin/usart_dma.rs b/examples/stm32f3/src/bin/usart_dma.rs
index 7dc905adc..5234e53b9 100644
--- a/examples/stm32f3/src/bin/usart_dma.rs
+++ b/examples/stm32f3/src/bin/usart_dma.rs
@@ -17,9 +17,7 @@ bind_interrupts!(struct Irqs {
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let mut init_config = embassy_stm32::Config::default();
-    init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
-    let p = embassy_stm32::init(init_config);
+    let p = embassy_stm32::init(Default::default());
     info!("Hello World!");
 
     let config = Config::default();
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index 7fc1ea926..24606b9b6 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -28,6 +28,7 @@ async fn main(_spawner: Spawner) {
         config.rcc.apb1_pre = APBPrescaler::DIV2;
         config.rcc.apb2_pre = APBPrescaler::DIV1;
         config.rcc.hrtim = HrtimClockSource::PllClk;
+        config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P); // TODO: The two lines here do the same thing
     }
     let p = embassy_stm32::init(config);
 

From 88e29608ed5425f5dbc3edf56acff1654d587a5e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:59:51 -0800
Subject: [PATCH 14/16] Rust fmt

---
 embassy-stm32/build.rs            | 6 +-----
 embassy-stm32/src/rcc/mod.rs      | 2 +-
 examples/stm32f334/src/bin/pwm.rs | 4 +++-
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 2ffbadfc3..a0b74c0b9 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -510,11 +510,7 @@ fn main() {
                     let field_name = format_ident!("{}", field_name);
                     let enum_name = format_ident!("{}", enum_name);
 
-                    rcc_cfgr_regs.insert((
-                        fieldset_name.clone(),
-                        field_name.clone(),
-                        enum_name.clone(),
-                    ));
+                    rcc_cfgr_regs.insert((fieldset_name.clone(), field_name.clone(), enum_name.clone()));
 
                     let match_arms: TokenStream = enumm
                         .variants
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index f71211925..24516d426 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -31,9 +31,9 @@ mod _version;
 
 pub use _version::*;
 
-pub use crate::_generated::Clocks;
 #[cfg(clock_mux)]
 pub use crate::_generated::ClockMux;
+pub use crate::_generated::Clocks;
 
 #[cfg(feature = "low-power")]
 /// Must be written within a critical section
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index 24606b9b6..cf5eb7b26 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -27,8 +27,10 @@ async fn main(_spawner: Spawner) {
         config.rcc.ahb_pre = AHBPrescaler::DIV1;
         config.rcc.apb1_pre = APBPrescaler::DIV2;
         config.rcc.apb2_pre = APBPrescaler::DIV1;
+
+        // TODO: The two lines here do the same thing
         config.rcc.hrtim = HrtimClockSource::PllClk;
-        config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P); // TODO: The two lines here do the same thing
+        config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P);
     }
     let p = embassy_stm32::init(config);
 

From e79d2dd7561c0acfb2eb81ea95929c1ca8ba1b77 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sat, 24 Feb 2024 12:54:58 -0800
Subject: [PATCH 15/16] Move to internal mod and re-export the enums

---
 embassy-stm32/build.rs            | 37 +++++++++++++++++++------------
 embassy-stm32/src/rcc/f013.rs     | 14 +++++-------
 embassy-stm32/src/rcc/mod.rs      |  2 +-
 examples/stm32f334/src/bin/pwm.rs |  4 +---
 4 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index a0b74c0b9..64d8afa13 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -601,7 +601,7 @@ fn main() {
             .iter()
             .map(|(_fieldset, fieldname, enum_name)| {
                 quote! {
-                    pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
+                    pub #fieldname: Option<#enum_name>
                 }
             })
             .collect();
@@ -627,23 +627,32 @@ fn main() {
             })
             .collect();
 
-        g.extend(quote! {
-            #[derive(Clone, Copy)]
-            pub struct ClockMux {
-                #( #struct_fields, )*
-            }
+        let enum_names: BTreeSet<_> = rcc_cfgr_regs
+            .iter()
+            .map(|(_fieldset, _fieldname, enum_name)| enum_name)
+            .collect();
 
-            impl Default for ClockMux {
-                fn default() -> Self {
-                    Self {
-                        #( #field_names: None, )*
+        g.extend(quote! {
+            pub mod mux {
+                #(pub use crate::pac::rcc::vals::#enum_names as #enum_names; )*
+
+                #[derive(Clone, Copy)]
+                pub struct ClockMux {
+                    #( #struct_fields, )*
+                }
+
+                impl Default for ClockMux {
+                    fn default() -> Self {
+                        Self {
+                            #( #field_names: None, )*
+                        }
                     }
                 }
-            }
 
-            impl ClockMux {
-                pub fn init(self) {
-                    #( #inits )*
+                impl ClockMux {
+                    pub fn init(self) {
+                        #( #inits )*
+                    }
                 }
             }
         });
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 86af4bd68..de209272d 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -97,10 +97,9 @@ pub struct Config {
     pub adc: AdcClockSource,
     #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
     pub adc34: AdcClockSource,
-    #[cfg(stm32f334)]
-    pub hrtim: HrtimClockSource,
+
     #[cfg(clock_mux)]
-    pub mux: crate::rcc::ClockMux,
+    pub mux: crate::rcc::mux::ClockMux,
 
     pub ls: super::LsConfig,
 }
@@ -128,8 +127,7 @@ impl Default for Config {
             adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
             #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
             adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
-            #[cfg(stm32f334)]
-            hrtim: HrtimClockSource::BusClk,
+
             #[cfg(clock_mux)]
             mux: Default::default(),
         }
@@ -350,7 +348,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    #[cfg(stm32f334)]
+    /*
+    TODO: Maybe add something like this to clock_mux? How can we autogenerate the data for this?
     let hrtim = match config.hrtim {
         // Must be configured after the bus is ready, otherwise it won't work
         HrtimClockSource::BusClk => None,
@@ -366,6 +365,7 @@ pub(crate) unsafe fn init(config: Config) {
             Some(pll * 2u32)
         }
     };
+     */
 
     #[cfg(clock_mux)]
     config.mux.init();
@@ -384,8 +384,6 @@ pub(crate) unsafe fn init(config: Config) {
         adc: Some(adc),
         #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
         adc34: Some(adc34),
-        #[cfg(stm32f334)]
-        hrtim: hrtim,
         rtc: rtc,
         hsi48: hsi48,
         #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 24516d426..b5a8bc2a4 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,7 +32,7 @@ mod _version;
 pub use _version::*;
 
 #[cfg(clock_mux)]
-pub use crate::_generated::ClockMux;
+pub use crate::_generated::mux as mux;
 pub use crate::_generated::Clocks;
 
 #[cfg(feature = "low-power")]
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index cf5eb7b26..7c6d6cd71 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -28,9 +28,7 @@ async fn main(_spawner: Spawner) {
         config.rcc.apb1_pre = APBPrescaler::DIV2;
         config.rcc.apb2_pre = APBPrescaler::DIV1;
 
-        // TODO: The two lines here do the same thing
-        config.rcc.hrtim = HrtimClockSource::PllClk;
-        config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P);
+        config.rcc.mux.hrtim1sw = Some(embassy_stm32::rcc::mux::Timsw::PLL1_P);
     }
     let p = embassy_stm32::init(config);
 

From 394abda092cac80c875998c429f629caa289f9d1 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sat, 24 Feb 2024 12:58:38 -0800
Subject: [PATCH 16/16] Fix report with the same name

---
 embassy-stm32/src/rcc/mod.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index b5a8bc2a4..c8ca713de 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,7 +32,7 @@ mod _version;
 pub use _version::*;
 
 #[cfg(clock_mux)]
-pub use crate::_generated::mux as mux;
+pub use crate::_generated::mux;
 pub use crate::_generated::Clocks;
 
 #[cfg(feature = "low-power")]