From 52ab015facf9f5039f89cd772d0f178ec70d878b Mon Sep 17 00:00:00 2001 From: Bing Wen Date: Wed, 27 Nov 2024 12:23:13 +0800 Subject: [PATCH] Add new --- embassy-stm32/src/fmt.rs | 19 +++++++++++++++++++ embassy-stm32/src/rcc/c0.rs | 18 ++++++------------ embassy-stm32/src/rcc/f013.rs | 29 +++++++++++------------------ embassy-stm32/src/rcc/f247.rs | 22 ++++++++-------------- embassy-stm32/src/rcc/g0.rs | 33 +++++++++++---------------------- embassy-stm32/src/rcc/g4.rs | 33 +++++++++++---------------------- 6 files changed, 66 insertions(+), 88 deletions(-) diff --git a/embassy-stm32/src/fmt.rs b/embassy-stm32/src/fmt.rs index 8ca61bc39..660407569 100644 --- a/embassy-stm32/src/fmt.rs +++ b/embassy-stm32/src/fmt.rs @@ -6,6 +6,25 @@ use core::fmt::{Debug, Display, LowerHex}; #[cfg(all(feature = "defmt", feature = "log"))] compile_error!("You may not enable both `defmt` and `log` features."); +#[collapse_debuginfo(yes)] +macro_rules! rcc_assert { + ($($x:tt)*) => { + { + if cfg!(feature = "unchecked-overclocking") { + #[cfg(not(feature = "defmt"))] + ::core::assert!($($x)*); + #[cfg(feature = "defmt")] + ::defmt::assert!($($x)*); + } else { + #[cfg(feature = "log")] + ::log::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled."); + #[cfg(feature = "defmt")] + ::defmt::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled."); + } + } + }; +} + #[collapse_debuginfo(yes)] macro_rules! assert { ($($x:tt)*) => { diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs index c6ac46491..c989a3891 100644 --- a/embassy-stm32/src/rcc/c0.rs +++ b/embassy-stm32/src/rcc/c0.rs @@ -109,12 +109,9 @@ pub(crate) unsafe fn init(config: Config) { None } Some(hse) => { - #[cfg(not(feature = "unchecked-overclocking"))] - { - match hse.mode { - HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)), - HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)), - } + match hse.mode { + HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)), + HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)), } RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); @@ -129,17 +126,14 @@ pub(crate) unsafe fn init(config: Config) { Sysclk::HSE => unwrap!(hse), _ => unreachable!(), }; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::SYSCLK.contains(&sys)); + rcc_assert!(max::SYSCLK.contains(&sys)); // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. let hclk = sys / config.ahb_pre; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::HCLK.contains(&hclk)); + rcc_assert!(max::HCLK.contains(&hclk)); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK.contains(&pclk1)); + rcc_assert(max::PCLK.contains(&pclk1)); let latency = match hclk.0 { ..=24_000_000 => Latency::WS0, diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs index 20a0f3940..cfe44ce54 100644 --- a/embassy-stm32/src/rcc/f013.rs +++ b/embassy-stm32/src/rcc/f013.rs @@ -157,12 +157,9 @@ pub(crate) unsafe fn init(config: Config) { None } Some(hse) => { - #[cfg(not(feature = "unchecked-overclocking"))] - { - match hse.mode { - HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)), - HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)), - } + match hse.mode { + HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)), + HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)), } RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); @@ -195,11 +192,9 @@ pub(crate) unsafe fn init(config: Config) { PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)), }; let in_freq = src_freq / pll.prediv; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_IN.contains(&in_freq)); - #[cfg(not(feature = "unchecked-overclocking"))] + rcc_assert!(max::PLL_IN.contains(&in_freq)); let out_freq = in_freq * pll.mul; - assert!(max::PLL_OUT.contains(&out_freq)); + rcc_assert!(max::PLL_OUT.contains(&out_freq)); #[cfg(not(stm32f1))] RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv)); @@ -243,17 +238,15 @@ pub(crate) unsafe fn init(config: Config) { let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); #[cfg(stm32f0)] let (pclk2, pclk2_tim) = (pclk1, pclk1_tim); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::HCLK.contains(&hclk)); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK1.contains(&pclk1)); - #[cfg(all(not(feature = "unchecked-overclocking"), not(stm32f0)))] - assert!(max::PCLK2.contains(&pclk2)); + rcc_assert!(max::HCLK.contains(&hclk)); + rcc_assert!(max::PCLK1.contains(&pclk1)); + #[cfg(not(stm32f0))] + rcc_assert!(max::PCLK2.contains(&pclk2)); #[cfg(stm32f1)] let adc = pclk2 / config.adc_pre; - #[cfg(all(not(feature = "unchecked-overclocking"), stm32f1))] - assert!(max::ADC.contains(&adc)); + #[cfg(stm32f1)] + rcc_assert!(max::ADC.contains(&adc)); // Set latency based on HCLK frquency #[cfg(stm32f0)] diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 83d4428cc..3e7aff02d 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -169,12 +169,9 @@ pub(crate) unsafe fn init(config: Config) { None } Some(hse) => { - #[cfg(not(feature = "unchecked-overclocking"))] - { - match hse.mode { - HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)), - HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)), - } + match hse.mode { + HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)), + HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)), } RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); @@ -207,14 +204,11 @@ pub(crate) unsafe fn init(config: Config) { let hclk = sys / config.ahb_pre; let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::SYSCLK.contains(&sys)); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::HCLK.contains(&hclk)); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK1.contains(&pclk1)); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK2.contains(&pclk2)); + + rcc_assert!(max::SYSCLK.contains(&sys)); + rcc_assert!(max::HCLK.contains(&hclk)); + rcc_assert!(max::PCLK1.contains(&pclk1)); + rcc_assert!(max::PCLK2.contains(&pclk2)); let rtc = config.ls.init(); diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs index 9e1351eae..71e524a20 100644 --- a/embassy-stm32/src/rcc/g0.rs +++ b/embassy-stm32/src/rcc/g0.rs @@ -139,12 +139,9 @@ pub(crate) unsafe fn init(config: Config) { None } Some(hse) => { - #[cfg(not(feature = "unchecked-overclocking"))] - { - match hse.mode { - HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)), - HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)), - } + match hse.mode { + HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)), + HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)), } RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); @@ -172,11 +169,9 @@ pub(crate) unsafe fn init(config: Config) { while RCC.cr().read().pllrdy() {} let in_freq = src_freq / pll_config.prediv; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_IN.contains(&in_freq)); + rcc_assert!(max::PLL_IN.contains(&in_freq)); let internal_freq = in_freq * pll_config.mul; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_VCO.contains(&internal_freq)); + rcc_assert!(max::PLL_VCO.contains(&internal_freq)); RCC.pllcfgr().write(|w| { w.set_plln(pll_config.mul); @@ -190,8 +185,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllpen(true); }); let freq = internal_freq / div_p; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_P.contains(&freq)); + rcc_assert!(max::PLL_P.contains(&freq)); freq }); @@ -201,8 +195,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllqen(true); }); let freq = internal_freq / div_q; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_Q.contains(&freq)); + rcc_assert!(max::PLL_Q.contains(&freq)); freq }); @@ -212,8 +205,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllren(true); }); let freq = internal_freq / div_r; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_R.contains(&freq)); + rcc_assert!(max::PLL_R.contains(&freq)); freq }); @@ -235,17 +227,14 @@ pub(crate) unsafe fn init(config: Config) { Sysclk::PLL1_R => unwrap!(pll.pll_r), _ => unreachable!(), }; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::SYSCLK.contains(&sys)); + rcc_assert!(max::SYSCLK.contains(&sys)); // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. let hclk = sys / config.ahb_pre; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::HCLK.contains(&hclk)); + rcc_assert!(max::HCLK.contains(&hclk)); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK.contains(&pclk1)); + rcc_assert!(max::PCLK.contains(&pclk1)); let latency = match (config.voltage_range, hclk.0) { (VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0, diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs index 09b2a8de8..e09b2915e 100644 --- a/embassy-stm32/src/rcc/g4.rs +++ b/embassy-stm32/src/rcc/g4.rs @@ -140,12 +140,9 @@ pub(crate) unsafe fn init(config: Config) { None } Some(hse) => { - #[cfg(not(feature = "unchecked-overclocking"))] - { - match hse.mode { - HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)), - HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)), - } + match hse.mode { + HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)), + HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)), } RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator)); @@ -172,12 +169,10 @@ pub(crate) unsafe fn init(config: Config) { while RCC.cr().read().pllrdy() {} let in_freq = src_freq / pll_config.prediv; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_IN.contains(&in_freq)); + rcc_assert!(max::PLL_IN.contains(&in_freq)); let internal_freq = in_freq * pll_config.mul; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_VCO.contains(&internal_freq)); + rcc_assert!(max::PLL_VCO.contains(&internal_freq)); RCC.pllcfgr().write(|w| { w.set_plln(pll_config.mul); @@ -191,8 +186,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllpen(true); }); let freq = internal_freq / div_p; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_P.contains(&freq)); + rcc_assert!(max::PLL_P.contains(&freq)); freq }); @@ -202,8 +196,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllqen(true); }); let freq = internal_freq / div_q; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_Q.contains(&freq)); + rcc_assert!(max::PLL_Q.contains(&freq)); freq }); @@ -213,8 +206,7 @@ pub(crate) unsafe fn init(config: Config) { w.set_pllren(true); }); let freq = internal_freq / div_r; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PLL_R.contains(&freq)); + rcc_assert!(max::PLL_R.contains(&freq)); freq }); @@ -237,18 +229,15 @@ pub(crate) unsafe fn init(config: Config) { _ => unreachable!(), }; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::SYSCLK.contains(&sys)); + rcc_assert!(max::SYSCLK.contains(&sys)); // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency. let hclk = sys / config.ahb_pre; - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::HCLK.contains(&hclk)); + rcc_assert!(max::HCLK.contains(&hclk)); let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre); let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre); - #[cfg(not(feature = "unchecked-overclocking"))] - assert!(max::PCLK.contains(&pclk2)); + rcc_assert!(max::PCLK.contains(&pclk2)); // Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!) if config.boost {