mirror of
https://github.com/embassy-rs/embassy.git
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stm32/sai: update for new metapac, simplify cfgs.
This commit is contained in:
Dario Nieuwenhuis
parent
f6414d8cd2
commit
60b640bd97
@ -8,6 +8,7 @@ use embassy_hal_internal::PeripheralType;
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pub use crate::dma::word;
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use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
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use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
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pub use crate::pac::sai::vals::Mckdiv as MasterClockDivider;
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use crate::pac::sai::{vals, Sai as Regs};
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use crate::rcc::{self, RccPeripheral};
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use crate::{peripherals, Peri};
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@ -45,7 +46,6 @@ pub enum Mode {
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}
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impl Mode {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
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match tx_rx {
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TxRx::Transmitter => match self {
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@ -80,7 +80,6 @@ pub enum SlotSize {
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}
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impl SlotSize {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn slotsz(&self) -> vals::Slotsz {
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match self {
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SlotSize::DataSize => vals::Slotsz::DATA_SIZE,
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@ -103,7 +102,6 @@ pub enum DataSize {
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}
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impl DataSize {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn ds(&self) -> vals::Ds {
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match self {
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DataSize::Data8 => vals::Ds::BIT8,
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@ -128,7 +126,6 @@ pub enum FifoThreshold {
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}
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impl FifoThreshold {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn fth(&self) -> vals::Fth {
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match self {
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FifoThreshold::Empty => vals::Fth::EMPTY,
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@ -149,7 +146,6 @@ pub enum MuteValue {
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}
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impl MuteValue {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn muteval(&self) -> vals::Muteval {
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match self {
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MuteValue::Zero => vals::Muteval::SEND_ZERO,
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@ -168,7 +164,6 @@ pub enum Protocol {
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}
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impl Protocol {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn prtcfg(&self) -> vals::Prtcfg {
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match self {
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Protocol::Free => vals::Prtcfg::FREE,
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@ -226,7 +221,6 @@ pub enum StereoMono {
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}
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impl StereoMono {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn mono(&self) -> vals::Mono {
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match self {
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StereoMono::Stereo => vals::Mono::STEREO,
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@ -245,7 +239,6 @@ pub enum BitOrder {
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}
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impl BitOrder {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn lsbfirst(&self) -> vals::Lsbfirst {
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match self {
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BitOrder::LsbFirst => vals::Lsbfirst::LSB_FIRST,
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@ -264,7 +257,6 @@ pub enum FrameSyncOffset {
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}
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impl FrameSyncOffset {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn fsoff(&self) -> vals::Fsoff {
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match self {
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FrameSyncOffset::OnFirstBit => vals::Fsoff::ON_FIRST,
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@ -283,7 +275,6 @@ pub enum FrameSyncPolarity {
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}
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impl FrameSyncPolarity {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn fspol(&self) -> vals::Fspol {
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match self {
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FrameSyncPolarity::ActiveLow => vals::Fspol::FALLING_EDGE,
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@ -301,7 +292,6 @@ pub enum FrameSyncDefinition {
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}
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impl FrameSyncDefinition {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn fsdef(&self) -> bool {
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match self {
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FrameSyncDefinition::StartOfFrame => false,
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@ -319,7 +309,6 @@ pub enum ClockStrobe {
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}
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impl ClockStrobe {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn ckstr(&self) -> vals::Ckstr {
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match self {
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ClockStrobe::Falling => vals::Ckstr::FALLING_EDGE,
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@ -337,7 +326,6 @@ pub enum ComplementFormat {
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}
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impl ComplementFormat {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn cpl(&self) -> vals::Cpl {
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match self {
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ComplementFormat::OnesComplement => vals::Cpl::ONES_COMPLEMENT,
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@ -356,7 +344,6 @@ pub enum Companding {
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}
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impl Companding {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn comp(&self) -> vals::Comp {
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match self {
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Companding::None => vals::Comp::NO_COMPANDING,
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@ -375,7 +362,6 @@ pub enum OutputDrive {
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}
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impl OutputDrive {
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn outdriv(&self) -> vals::Outdriv {
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match self {
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OutputDrive::OnStart => vals::Outdriv::ON_START,
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@ -384,196 +370,6 @@ impl OutputDrive {
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}
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}
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/// Master clock divider.
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#[derive(Copy, Clone, PartialEq)]
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#[allow(missing_docs)]
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#[cfg(any(sai_v1, sai_v2))]
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pub enum MasterClockDivider {
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MasterClockDisabled,
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Div1,
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Div2,
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Div4,
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Div6,
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Div8,
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Div10,
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Div12,
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Div14,
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Div16,
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Div18,
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Div20,
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Div22,
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Div24,
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Div26,
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Div28,
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Div30,
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}
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/// Master clock divider.
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#[derive(Copy, Clone, PartialEq)]
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#[allow(missing_docs)]
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#[cfg(any(sai_v1_4pdm, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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pub enum MasterClockDivider {
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MasterClockDisabled,
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Div1,
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Div2,
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Div3,
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Div4,
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Div5,
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Div6,
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Div7,
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Div8,
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Div9,
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Div10,
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Div11,
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Div12,
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Div13,
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Div14,
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Div15,
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Div16,
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Div17,
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Div18,
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Div19,
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Div20,
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Div21,
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Div22,
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Div23,
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Div24,
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Div25,
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Div26,
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Div27,
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Div28,
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Div29,
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Div30,
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Div31,
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Div32,
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Div33,
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Div34,
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Div35,
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Div36,
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Div37,
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Div38,
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Div39,
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Div40,
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Div41,
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Div42,
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Div43,
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Div44,
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Div45,
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Div46,
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Div47,
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Div48,
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Div49,
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Div50,
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Div51,
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Div52,
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Div53,
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Div54,
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Div55,
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Div56,
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Div57,
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Div58,
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Div59,
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Div60,
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Div61,
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Div62,
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Div63,
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}
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impl MasterClockDivider {
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#[cfg(any(sai_v1, sai_v2))]
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const fn mckdiv(&self) -> u8 {
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match self {
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MasterClockDivider::MasterClockDisabled => 0,
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MasterClockDivider::Div1 => 0,
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MasterClockDivider::Div2 => 1,
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MasterClockDivider::Div4 => 2,
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MasterClockDivider::Div6 => 3,
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MasterClockDivider::Div8 => 4,
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MasterClockDivider::Div10 => 5,
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MasterClockDivider::Div12 => 6,
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MasterClockDivider::Div14 => 7,
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MasterClockDivider::Div16 => 8,
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MasterClockDivider::Div18 => 9,
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MasterClockDivider::Div20 => 10,
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MasterClockDivider::Div22 => 11,
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MasterClockDivider::Div24 => 12,
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MasterClockDivider::Div26 => 13,
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MasterClockDivider::Div28 => 14,
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MasterClockDivider::Div30 => 15,
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}
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}
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#[cfg(any(sai_v1_4pdm, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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const fn mckdiv(&self) -> u8 {
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match self {
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MasterClockDivider::MasterClockDisabled => 0,
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MasterClockDivider::Div1 => 1,
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MasterClockDivider::Div2 => 2,
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MasterClockDivider::Div3 => 3,
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MasterClockDivider::Div4 => 4,
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MasterClockDivider::Div5 => 5,
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MasterClockDivider::Div6 => 6,
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MasterClockDivider::Div7 => 7,
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MasterClockDivider::Div8 => 8,
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MasterClockDivider::Div9 => 9,
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MasterClockDivider::Div10 => 10,
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MasterClockDivider::Div11 => 11,
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MasterClockDivider::Div12 => 12,
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MasterClockDivider::Div13 => 13,
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MasterClockDivider::Div14 => 14,
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MasterClockDivider::Div15 => 15,
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MasterClockDivider::Div16 => 16,
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MasterClockDivider::Div17 => 17,
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MasterClockDivider::Div18 => 18,
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MasterClockDivider::Div19 => 19,
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MasterClockDivider::Div20 => 20,
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MasterClockDivider::Div21 => 21,
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MasterClockDivider::Div22 => 22,
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MasterClockDivider::Div23 => 23,
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MasterClockDivider::Div24 => 24,
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MasterClockDivider::Div25 => 25,
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MasterClockDivider::Div26 => 26,
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MasterClockDivider::Div27 => 27,
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MasterClockDivider::Div28 => 28,
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MasterClockDivider::Div29 => 29,
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MasterClockDivider::Div30 => 30,
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MasterClockDivider::Div31 => 31,
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MasterClockDivider::Div32 => 32,
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MasterClockDivider::Div33 => 33,
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MasterClockDivider::Div34 => 34,
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MasterClockDivider::Div35 => 35,
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MasterClockDivider::Div36 => 36,
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MasterClockDivider::Div37 => 37,
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MasterClockDivider::Div38 => 38,
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MasterClockDivider::Div39 => 39,
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MasterClockDivider::Div40 => 40,
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MasterClockDivider::Div41 => 41,
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MasterClockDivider::Div42 => 42,
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MasterClockDivider::Div43 => 43,
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MasterClockDivider::Div44 => 44,
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MasterClockDivider::Div45 => 45,
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MasterClockDivider::Div46 => 46,
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MasterClockDivider::Div47 => 47,
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MasterClockDivider::Div48 => 48,
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MasterClockDivider::Div49 => 49,
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MasterClockDivider::Div50 => 50,
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MasterClockDivider::Div51 => 51,
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MasterClockDivider::Div52 => 52,
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MasterClockDivider::Div53 => 53,
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MasterClockDivider::Div54 => 54,
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MasterClockDivider::Div55 => 55,
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MasterClockDivider::Div56 => 56,
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MasterClockDivider::Div57 => 57,
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MasterClockDivider::Div58 => 58,
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MasterClockDivider::Div59 => 59,
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MasterClockDivider::Div60 => 60,
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MasterClockDivider::Div61 => 61,
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MasterClockDivider::Div62 => 62,
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MasterClockDivider::Div63 => 63,
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}
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}
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}
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/// [`SAI`] configuration.
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#[allow(missing_docs)]
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#[non_exhaustive]
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@ -598,8 +394,7 @@ pub struct Config {
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pub frame_length: u8,
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pub clock_strobe: ClockStrobe,
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pub output_drive: OutputDrive,
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pub master_clock_divider: MasterClockDivider,
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pub nodiv: bool,
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pub master_clock_divider: Option<MasterClockDivider>,
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pub is_high_impedance_on_inactive_slot: bool,
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pub fifo_threshold: FifoThreshold,
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pub companding: Companding,
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@ -628,8 +423,7 @@ impl Default for Config {
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frame_sync_active_level_length: word::U7(16),
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frame_sync_definition: FrameSyncDefinition::ChannelIdentification,
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frame_length: 32,
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master_clock_divider: MasterClockDivider::MasterClockDisabled,
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nodiv: false,
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master_clock_divider: None,
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clock_strobe: ClockStrobe::Rising,
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output_drive: OutputDrive::Immediately,
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is_high_impedance_on_inactive_slot: false,
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@ -761,15 +555,11 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
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mclk: Peri<'d, impl MclkPin<T, S>>,
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dma: Peri<'d, impl Channel + Dma<T, S>>,
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dma_buf: &'d mut [W],
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mut config: Config,
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config: Config,
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) -> Self {
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let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
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mclk.set_as_af(mclk.af_num(), ck_af_type);
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if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
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config.master_clock_divider = MasterClockDivider::Div1;
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}
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Self::new_asynchronous(peri, sck, sd, fs, dma, dma_buf, config)
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}
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@ -851,10 +641,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
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) -> Self {
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let ch = T::REGS.ch(sub_block as usize);
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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{
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ch.cr1().modify(|w| w.set_saien(false));
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}
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ch.cr1().modify(|w| w.set_saien(false));
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ch.cr2().modify(|w| w.set_fflush(true));
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@ -877,55 +664,52 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
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}
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}
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#[cfg(any(sai_v1, sai_v1_4pdm, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
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{
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ch.cr1().modify(|w| {
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w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
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TxRx::Transmitter
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} else {
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TxRx::Receiver
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}));
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w.set_prtcfg(config.protocol.prtcfg());
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w.set_ds(config.data_size.ds());
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w.set_lsbfirst(config.bit_order.lsbfirst());
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w.set_ckstr(config.clock_strobe.ckstr());
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w.set_syncen(config.sync_input.syncen());
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w.set_mono(config.stereo_mono.mono());
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w.set_outdriv(config.output_drive.outdriv());
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w.set_mckdiv(config.master_clock_divider.mckdiv().into());
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w.set_nodiv(config.nodiv);
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w.set_dmaen(true);
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});
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ch.cr1().modify(|w| {
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w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
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TxRx::Transmitter
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} else {
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TxRx::Receiver
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}));
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w.set_prtcfg(config.protocol.prtcfg());
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w.set_ds(config.data_size.ds());
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w.set_lsbfirst(config.bit_order.lsbfirst());
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w.set_ckstr(config.clock_strobe.ckstr());
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w.set_syncen(config.sync_input.syncen());
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w.set_mono(config.stereo_mono.mono());
|
||||
w.set_outdriv(config.output_drive.outdriv());
|
||||
w.set_mckdiv(config.master_clock_divider.unwrap_or(MasterClockDivider::DIV1));
|
||||
w.set_nodiv(config.master_clock_divider.is_none());
|
||||
w.set_dmaen(true);
|
||||
});
|
||||
|
||||
ch.cr2().modify(|w| {
|
||||
w.set_fth(config.fifo_threshold.fth());
|
||||
w.set_comp(config.companding.comp());
|
||||
w.set_cpl(config.complement_format.cpl());
|
||||
w.set_muteval(config.mute_value.muteval());
|
||||
w.set_mutecnt(config.mute_detection_counter.0 as u8);
|
||||
w.set_tris(config.is_high_impedance_on_inactive_slot);
|
||||
});
|
||||
ch.cr2().modify(|w| {
|
||||
w.set_fth(config.fifo_threshold.fth());
|
||||
w.set_comp(config.companding.comp());
|
||||
w.set_cpl(config.complement_format.cpl());
|
||||
w.set_muteval(config.mute_value.muteval());
|
||||
w.set_mutecnt(config.mute_detection_counter.0 as u8);
|
||||
w.set_tris(config.is_high_impedance_on_inactive_slot);
|
||||
});
|
||||
|
||||
ch.frcr().modify(|w| {
|
||||
w.set_fsoff(config.frame_sync_offset.fsoff());
|
||||
w.set_fspol(config.frame_sync_polarity.fspol());
|
||||
w.set_fsdef(config.frame_sync_definition.fsdef());
|
||||
w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
|
||||
w.set_frl(config.frame_length - 1);
|
||||
});
|
||||
ch.frcr().modify(|w| {
|
||||
w.set_fsoff(config.frame_sync_offset.fsoff());
|
||||
w.set_fspol(config.frame_sync_polarity.fspol());
|
||||
w.set_fsdef(config.frame_sync_definition.fsdef());
|
||||
w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
|
||||
w.set_frl(config.frame_length - 1);
|
||||
});
|
||||
|
||||
ch.slotr().modify(|w| {
|
||||
w.set_nbslot(config.slot_count.0 as u8 - 1);
|
||||
w.set_slotsz(config.slot_size.slotsz());
|
||||
w.set_fboff(config.first_bit_offset.0 as u8);
|
||||
w.set_sloten(vals::Sloten::from_bits(config.slot_enable as u16));
|
||||
});
|
||||
ch.slotr().modify(|w| {
|
||||
w.set_nbslot(config.slot_count.0 as u8 - 1);
|
||||
w.set_slotsz(config.slot_size.slotsz());
|
||||
w.set_fboff(config.first_bit_offset.0 as u8);
|
||||
w.set_sloten(vals::Sloten::from_bits(config.slot_enable as u16));
|
||||
});
|
||||
|
||||
ch.cr1().modify(|w| w.set_saien(true));
|
||||
ch.cr1().modify(|w| w.set_saien(true));
|
||||
|
||||
if ch.cr1().read().saien() == false {
|
||||
panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
|
||||
}
|
||||
if ch.cr1().read().saien() == false {
|
||||
panic!("SAI failed to enable. Check that config is valid (frame length, slot count, etc)");
|
||||
}
|
||||
|
||||
Self {
|
||||
|
||||
@ -63,7 +63,7 @@ async fn main(_spawner: Spawner) {
|
||||
tx_config.tx_rx = TxRx::Transmitter;
|
||||
tx_config.sync_output = true;
|
||||
tx_config.clock_strobe = ClockStrobe::Falling;
|
||||
tx_config.master_clock_divider = mclk_div;
|
||||
tx_config.master_clock_divider = Some(mclk_div);
|
||||
tx_config.stereo_mono = StereoMono::Stereo;
|
||||
tx_config.data_size = DataSize::Data24;
|
||||
tx_config.bit_order = BitOrder::MsbFirst;
|
||||
@ -119,71 +119,7 @@ async fn main(_spawner: Spawner) {
|
||||
}
|
||||
}
|
||||
|
||||
const fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
|
||||
match v {
|
||||
1 => MasterClockDivider::Div1,
|
||||
2 => MasterClockDivider::Div2,
|
||||
3 => MasterClockDivider::Div3,
|
||||
4 => MasterClockDivider::Div4,
|
||||
5 => MasterClockDivider::Div5,
|
||||
6 => MasterClockDivider::Div6,
|
||||
7 => MasterClockDivider::Div7,
|
||||
8 => MasterClockDivider::Div8,
|
||||
9 => MasterClockDivider::Div9,
|
||||
10 => MasterClockDivider::Div10,
|
||||
11 => MasterClockDivider::Div11,
|
||||
12 => MasterClockDivider::Div12,
|
||||
13 => MasterClockDivider::Div13,
|
||||
14 => MasterClockDivider::Div14,
|
||||
15 => MasterClockDivider::Div15,
|
||||
16 => MasterClockDivider::Div16,
|
||||
17 => MasterClockDivider::Div17,
|
||||
18 => MasterClockDivider::Div18,
|
||||
19 => MasterClockDivider::Div19,
|
||||
20 => MasterClockDivider::Div20,
|
||||
21 => MasterClockDivider::Div21,
|
||||
22 => MasterClockDivider::Div22,
|
||||
23 => MasterClockDivider::Div23,
|
||||
24 => MasterClockDivider::Div24,
|
||||
25 => MasterClockDivider::Div25,
|
||||
26 => MasterClockDivider::Div26,
|
||||
27 => MasterClockDivider::Div27,
|
||||
28 => MasterClockDivider::Div28,
|
||||
29 => MasterClockDivider::Div29,
|
||||
30 => MasterClockDivider::Div30,
|
||||
31 => MasterClockDivider::Div31,
|
||||
32 => MasterClockDivider::Div32,
|
||||
33 => MasterClockDivider::Div33,
|
||||
34 => MasterClockDivider::Div34,
|
||||
35 => MasterClockDivider::Div35,
|
||||
36 => MasterClockDivider::Div36,
|
||||
37 => MasterClockDivider::Div37,
|
||||
38 => MasterClockDivider::Div38,
|
||||
39 => MasterClockDivider::Div39,
|
||||
40 => MasterClockDivider::Div40,
|
||||
41 => MasterClockDivider::Div41,
|
||||
42 => MasterClockDivider::Div42,
|
||||
43 => MasterClockDivider::Div43,
|
||||
44 => MasterClockDivider::Div44,
|
||||
45 => MasterClockDivider::Div45,
|
||||
46 => MasterClockDivider::Div46,
|
||||
47 => MasterClockDivider::Div47,
|
||||
48 => MasterClockDivider::Div48,
|
||||
49 => MasterClockDivider::Div49,
|
||||
50 => MasterClockDivider::Div50,
|
||||
51 => MasterClockDivider::Div51,
|
||||
52 => MasterClockDivider::Div52,
|
||||
53 => MasterClockDivider::Div53,
|
||||
54 => MasterClockDivider::Div54,
|
||||
55 => MasterClockDivider::Div55,
|
||||
56 => MasterClockDivider::Div56,
|
||||
57 => MasterClockDivider::Div57,
|
||||
58 => MasterClockDivider::Div58,
|
||||
59 => MasterClockDivider::Div59,
|
||||
60 => MasterClockDivider::Div60,
|
||||
61 => MasterClockDivider::Div61,
|
||||
62 => MasterClockDivider::Div62,
|
||||
63 => MasterClockDivider::Div63,
|
||||
_ => panic!(),
|
||||
}
|
||||
fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
|
||||
assert!((1..=63).contains(&v));
|
||||
MasterClockDivider::from_bits(v)
|
||||
}
|
||||
|
||||
@ -168,7 +168,7 @@ fn new_sai_transmitter<'d>(
|
||||
sai_config.slot_enable = 0xFFFF; // All slots
|
||||
sai_config.data_size = sai::DataSize::Data32;
|
||||
sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
|
||||
sai_config.master_clock_divider = hal::sai::MasterClockDivider::MasterClockDisabled;
|
||||
sai_config.master_clock_divider = None;
|
||||
|
||||
let (sub_block_tx, _) = hal::sai::split_subblocks(sai);
|
||||
Sai::new_asynchronous(sub_block_tx, sck, sd, fs, dma, buf, sai_config)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user