From be5b62bdd469dc7fd68ddb4040b4c0547e65bda8 Mon Sep 17 00:00:00 2001 From: Pietro Lorefice Date: Fri, 20 Jun 2025 10:46:33 +0200 Subject: [PATCH 1/2] stm32: hsem: add missing RCC initialization --- embassy-stm32/src/hsem/mod.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs index 31527bcdb..f648bf861 100644 --- a/embassy-stm32/src/hsem/mod.rs +++ b/embassy-stm32/src/hsem/mod.rs @@ -3,7 +3,7 @@ use embassy_hal_internal::PeripheralType; use crate::pac; -use crate::rcc::RccPeripheral; +use crate::rcc::{self, RccPeripheral}; // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs. // Those MCUs have a different HSEM implementation (Secure semaphore lock support, // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute), @@ -80,6 +80,8 @@ pub struct HardwareSemaphore<'d, T: Instance> { impl<'d, T: Instance> HardwareSemaphore<'d, T> { /// Creates a new HardwareSemaphore instance. pub fn new(peripheral: Peri<'d, T>) -> Self { + rcc::enable_and_reset::(); + HardwareSemaphore { _peri: peripheral } } From 59228e2ab4d70eee356400b2470190885527bbc1 Mon Sep 17 00:00:00 2001 From: Pietro Lorefice Date: Fri, 20 Jun 2025 10:47:37 +0200 Subject: [PATCH 2/2] stm32: hsem: fix broken CPUID detection --- embassy-stm32/src/hsem/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs index f648bf861..573a1851d 100644 --- a/embassy-stm32/src/hsem/mod.rs +++ b/embassy-stm32/src/hsem/mod.rs @@ -46,7 +46,7 @@ pub enum CoreId { #[inline(always)] pub fn get_current_coreid() -> CoreId { let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() }; - match cpuid & 0x000000F0 { + match (cpuid & 0x000000F0) >> 4 { #[cfg(any(stm32wb, stm32wl))] 0x0 => CoreId::Core1,