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stm32: update metapac, cleanup clocks a bit.

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This commit is contained in:
Dario Nieuwenhuis 2025-04-18 20:32:15 +02:00
parent 4c6311a1e3
commit 7512c5f14e
9 changed files with 63 additions and 44 deletions
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4
embassy-stm32/Cargo.toml
View File

@ -73,7 +73,7 @@ rand_core = "0.6.3"
sdio-host = "0.9.0"
critical-section = "1.1"
#stm32-metapac = { version = "16" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-a7a30c9d54e7415709c463a537501691784672db" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b" }
vcell = "0.1.3"
nb = "1.0.0"
@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-a7a30c9d54e7415709c463a537501691784672db", default-features = false, features = ["metadata"] }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b", default-features = false, features = ["metadata"] }
[features]
default = ["rt"]

81
embassy-stm32/build.rs
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@ -489,9 +489,39 @@ fn main() {
}
impl<'a> ClockGen<'a> {
fn parse_mul_div(name: &str) -> (&str, Frac) {
if name == "hse_div_rtcpre" {
return (name, Frac { num: 1, denom: 1 });
}
if let Some(i) = name.find("_div_") {
let n = &name[..i];
let val: u32 = name[i + 5..].parse().unwrap();
(n, Frac { num: 1, denom: val })
} else if let Some(i) = name.find("_mul_") {
let n = &name[..i];
let val: u32 = name[i + 5..].parse().unwrap();
(n, Frac { num: val, denom: 1 })
} else {
(name, Frac { num: 1, denom: 1 })
}
}
fn gen_clock(&mut self, peripheral: &str, name: &str) -> TokenStream {
let clock_name = format_ident!("{}", name.to_ascii_lowercase());
self.clock_names.insert(name.to_ascii_lowercase());
let name = name.to_ascii_lowercase();
let (name, frac) = Self::parse_mul_div(&name);
let clock_name = format_ident!("{}", name);
self.clock_names.insert(name.to_string());
let mut muldiv = quote!();
if frac.num != 1 {
let val = frac.num;
muldiv.extend(quote!(* #val));
}
if frac.denom != 1 {
let val = frac.denom;
muldiv.extend(quote!(/ #val));
}
quote!(unsafe {
unwrap!(
crate::rcc::get_freqs().#clock_name.to_hertz(),
@ -500,6 +530,7 @@ fn main() {
#peripheral,
#name
)
#muldiv
})
}
@ -1503,29 +1534,6 @@ fn main() {
}
}
#[derive(Copy, Clone, Debug)]
struct Frac {
num: u32,
denom: u32,
}
impl Frac {
fn simplify(self) -> Self {
let d = gcd(self.num, self.denom);
Self {
num: self.num / d,
denom: self.denom / d,
}
}
}
fn gcd(a: u32, b: u32) -> u32 {
if b == 0 {
return a;
}
gcd(b, a % b)
}
fn parse_num(n: &str) -> Result<Frac, ()> {
for prefix in ["DIV", "MUL"] {
if let Some(n) = n.strip_prefix(prefix) {
@ -2136,3 +2144,26 @@ fn mem_filter(chip: &str, region: &str) -> bool {
true
}
#[derive(Copy, Clone, Debug)]
struct Frac {
num: u32,
denom: u32,
}
impl Frac {
fn simplify(self) -> Self {
let d = gcd(self.num, self.denom);
Self {
num: self.num / d,
denom: self.denom / d,
}
}
}
fn gcd(a: u32, b: u32) -> u32 {
if b == 0 {
return a;
}
gcd(b, a % b)
}

6
embassy-stm32/src/rcc/f013.rs
View File

@ -289,9 +289,6 @@ pub(crate) unsafe fn init(config: Config) {
out_freq
});
#[cfg(stm32f3)]
let pll_mul_2 = pll.map(|pll| pll * 2u32);
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3, stm32f107))]
let usb = match pll {
Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
@ -483,9 +480,6 @@ pub(crate) unsafe fn init(config: Config) {
hsi: hsi,
hse: hse,
pll1_p: pll,
#[cfg(stm32f3)]
pll1_p_mul_2: pll_mul_2,
hsi_div_244: hsi.map(|h| h / 244u32),
sys: Some(sys),
pclk1: Some(pclk1),
pclk2: Some(pclk2),

1
embassy-stm32/src/rcc/f247.rs
View File

@ -316,7 +316,6 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(dsihost)]
dsi_phy: None, // DSI PLL clock not supported, don't call `RccPeripheral::frequency()` in the drivers
hsi_div488: hsi.map(|hsi| hsi/488u32),
hsi_hse: None,
afif: None,
);

2
embassy-stm32/src/rcc/g0.rs
View File

@ -309,8 +309,6 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(crs)]
hsi48: hsi48,
rtc: rtc,
hsi_div_8: hsi.map(|h| h / 8u32),
hsi_div_488: hsi.map(|h| h / 488u32),
// TODO
lsi: None,

2
embassy-stm32/src/rcc/g4.rs
View File

@ -320,6 +320,8 @@ pub(crate) unsafe fn init(config: Config) {
hse: hse,
hsi48: hsi48,
rtc: rtc,
lsi: None,
lse: None,
);
}

5
embassy-stm32/src/rcc/h.rs
View File

@ -687,7 +687,6 @@ pub(crate) unsafe fn init(config: Config) {
hsi: hsi,
hsi48: hsi48,
csi: csi,
csi_div_122: csi.map(|c| c / 122u32),
hse: hse,
lse: None,
@ -726,9 +725,9 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h7rs)]
clk48mohci: None, // TODO
#[cfg(stm32h7rs)]
hse_div_2: hse.map(|clk| clk / 2u32),
#[cfg(stm32h7rs)]
usb: Some(Hertz(48_000_000)),
#[cfg(stm32h5)]
hse_div_rtcpre: None, // TODO
);
}

2
embassy-stm32/src/rcc/l.rs
View File

@ -396,7 +396,7 @@ pub(crate) unsafe fn init(config: Config) {
hsi48: hsi48,
#[cfg(any(stm32l0, stm32l1))]
pll1_vco_div_2: pll.vco.map(|c| c/2u32),
pll1_vco: pll.vco,
#[cfg(not(any(stm32l0, stm32l1)))]
pll1_p: pll.p,

4
embassy-stm32/src/rcc/u5.rs
View File

@ -345,10 +345,8 @@ pub(crate) unsafe fn init(config: Config) {
lse: lse,
lsi: lsi,
hse: hse,
hse_div_2: hse.map(|clk| clk / 2u32),
hsi: hsi,
pll1_p: pll1.p,
pll1_p_div_2: pll1.p.map(|clk| clk / 2u32),
pll1_q: pll1.q,
pll1_r: pll1.r,
pll2_p: pll2.p,
@ -363,9 +361,7 @@ pub(crate) unsafe fn init(config: Config) {
// TODO
audioclk: None,
hsi48_div_2: None,
shsi: None,
shsi_div_2: None,
);
}