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Apply fixes to XSPI as well

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This commit is contained in:
Brian Schwind 2025-09-13 00:12:36 +09:00
parent 4a3e9e38e5
commit 881fee9820
1 changed files with 8 additions and 9 deletions
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17
embassy-stm32/src/xspi/mod.rs
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@ -110,7 +110,7 @@ pub struct TransferConfig {
/// Data width (DMODE)
pub dwidth: XspiWidth,
/// Data buffer
/// Data Double Transfer rate enable
pub ddtr: bool,
/// Number of dummy cycles (DCYC)
@ -424,11 +424,6 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
// Configure alternate bytes
if let Some(ab) = command.alternate_bytes {
T::REGS.abr().write(|v| v.set_alternate(ab));
T::REGS.ccr().modify(|w| {
w.set_abmode(CcrAbmode::from_bits(command.abwidth.into()));
w.set_abdtr(command.abdtr);
w.set_absize(CcrAbsize::from_bits(command.absize.into()));
})
} else {
T::REGS.ccr().modify(|w| {
// disable alternate bytes
@ -445,14 +440,14 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
if let Some(data_length) = data_len {
T::REGS.dlr().write(|v| {
v.set_dl((data_length - 1) as u32);
})
});
} else {
T::REGS.dlr().write(|v| {
v.set_dl((0) as u32);
})
});
}
// Configure instruction/address/data modes
// Configure instruction/address/alternate bytes/data modes
T::REGS.ccr().modify(|w| {
w.set_imode(CcrImode::from_bits(command.iwidth.into()));
w.set_idtr(command.idtr);
@ -462,6 +457,10 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
w.set_addtr(command.addtr);
w.set_adsize(CcrAdsize::from_bits(command.adsize.into()));
w.set_abmode(CcrAbmode::from_bits(command.abwidth.into()));
w.set_abdtr(command.abdtr);
w.set_absize(CcrAbsize::from_bits(command.absize.into()));
w.set_dmode(CcrDmode::from_bits(command.dwidth.into()));
w.set_ddtr(command.ddtr);
});