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Merge pull request #3574 from itswenb/main

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feat: Add new feature to enable overclocking
This commit is contained in:
Ulf Lilleengen 2024-11-27 07:38:00 +00:00 committed by GitHub
commit 8e25bc56f6
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7 changed files with 65 additions and 41 deletions
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4
embassy-stm32/Cargo.toml
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@ -138,6 +138,10 @@ trustzone-secure = []
## There are no plans to make this stable.
unstable-pac = []
## Enable this feature to disable the overclocking check.
## DO NOT ENABLE THIS FEATURE UNLESS YOU KNOW WHAT YOU'RE DOING.
unchecked-overclocking = []
#! ## Time
## Enables additional driver features that depend on embassy-time

22
embassy-stm32/src/fmt.rs
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@ -6,6 +6,28 @@ use core::fmt::{Debug, Display, LowerHex};
#[cfg(all(feature = "defmt", feature = "log"))]
compile_error!("You may not enable both `defmt` and `log` features.");
#[collapse_debuginfo(yes)]
macro_rules! rcc_assert {
($($x:tt)*) => {
{
#[cfg(not(feature = "unchecked-overclocking"))]
{
#[cfg(not(feature = "defmt"))]
::core::assert!($($x)*);
#[cfg(feature = "defmt")]
::defmt::assert!($($x)*);
}
#[cfg(feature = "unchecked-overclocking")]
{
#[cfg(feature = "log")]
::log::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
#[cfg(feature = "defmt")]
::defmt::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
}
}
};
}
#[collapse_debuginfo(yes)]
macro_rules! assert {
($($x:tt)*) => {

10
embassy-stm32/src/rcc/c0.rs
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@ -110,8 +110,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -127,14 +127,14 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
assert!(max::PCLK.contains(&pclk1));
rcc_assert!(max::PCLK.contains(&pclk1));
let latency = match hclk.0 {
..=24_000_000 => Latency::WS0,

16
embassy-stm32/src/rcc/f013.rs
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@ -158,8 +158,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -192,9 +192,9 @@ pub(crate) unsafe fn init(config: Config) {
PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
};
let in_freq = src_freq / pll.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let out_freq = in_freq * pll.mul;
assert!(max::PLL_OUT.contains(&out_freq));
rcc_assert!(max::PLL_OUT.contains(&out_freq));
#[cfg(not(stm32f1))]
RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
@ -239,15 +239,15 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32f0)]
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
rcc_assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(stm32f0))]
assert!(max::PCLK2.contains(&pclk2));
rcc_assert!(max::PCLK2.contains(&pclk2));
#[cfg(stm32f1)]
let adc = pclk2 / config.adc_pre;
#[cfg(stm32f1)]
assert!(max::ADC.contains(&adc));
rcc_assert!(max::ADC.contains(&adc));
// Set latency based on HCLK frquency
#[cfg(stm32f0)]

12
embassy-stm32/src/rcc/f247.rs
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@ -170,8 +170,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -205,10 +205,10 @@ pub(crate) unsafe fn init(config: Config) {
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
assert!(max::SYSCLK.contains(&sys));
assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
assert!(max::PCLK2.contains(&pclk2));
rcc_assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::PCLK1.contains(&pclk1));
rcc_assert!(max::PCLK2.contains(&pclk2));
let rtc = config.ls.init();

21
embassy-stm32/src/rcc/g0.rs
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@ -140,8 +140,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -169,10 +169,9 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;
assert!(max::PLL_VCO.contains(&internal_freq));
rcc_assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul);
@ -186,7 +185,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
assert!(max::PLL_P.contains(&freq));
rcc_assert!(max::PLL_P.contains(&freq));
freq
});
@ -196,7 +195,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
assert!(max::PLL_Q.contains(&freq));
rcc_assert!(max::PLL_Q.contains(&freq));
freq
});
@ -206,7 +205,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
assert!(max::PLL_R.contains(&freq));
rcc_assert!(max::PLL_R.contains(&freq));
freq
});
@ -229,14 +228,14 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
assert!(max::PCLK.contains(&pclk1));
rcc_assert!(max::PCLK.contains(&pclk1));
let latency = match (config.voltage_range, hclk.0) {
(VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,

21
embassy-stm32/src/rcc/g4.rs
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@ -141,8 +141,8 @@ pub(crate) unsafe fn init(config: Config) {
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -169,10 +169,10 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv;
assert!(max::PLL_IN.contains(&in_freq));
rcc_assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;
assert!(max::PLL_VCO.contains(&internal_freq));
rcc_assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul);
@ -186,7 +186,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
assert!(max::PLL_P.contains(&freq));
rcc_assert!(max::PLL_P.contains(&freq));
freq
});
@ -196,7 +196,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
assert!(max::PLL_Q.contains(&freq));
rcc_assert!(max::PLL_Q.contains(&freq));
freq
});
@ -206,7 +206,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
assert!(max::PLL_R.contains(&freq));
rcc_assert!(max::PLL_R.contains(&freq));
freq
});
@ -229,16 +229,15 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
assert!(max::SYSCLK.contains(&sys));
rcc_assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
rcc_assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
assert!(max::PCLK.contains(&pclk2));
assert!(max::PCLK.contains(&pclk2));
rcc_assert!(max::PCLK.contains(&pclk2));
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
if config.boost {