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Add new feature to enable overclocking

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This commit is contained in:
Bing Wen 2024-11-26 12:27:43 +08:00
parent b9408f0510
commit 8eaa3c8fd3
6 changed files with 63 additions and 23 deletions
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4
embassy-stm32/Cargo.toml
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@ -138,6 +138,10 @@ trustzone-secure = []
## There are no plans to make this stable.
unstable-pac = []
## Enable this feature to disable the overclocking check.
## DO NOT ENABLE THIS FEATURE UNLESS YOU KNOW WHAT YOU'RE DOING.
unchecked-overclocking = []
#! ## Time
## Enables additional driver features that depend on embassy-time

13
embassy-stm32/src/rcc/c0.rs
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@ -109,9 +109,12 @@ pub(crate) unsafe fn init(config: Config) {
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
#[cfg(not(feature = "unchecked-overclocking"))]
{
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -126,14 +129,16 @@ pub(crate) unsafe fn init(config: Config) {
Sysclk::HSE => unwrap!(hse),
_ => unreachable!(),
};
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK.contains(&pclk1));
let latency = match hclk.0 {

18
embassy-stm32/src/rcc/f013.rs
View File

@ -157,9 +157,12 @@ pub(crate) unsafe fn init(config: Config) {
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
#[cfg(not(feature = "unchecked-overclocking"))]
{
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -192,7 +195,9 @@ pub(crate) unsafe fn init(config: Config) {
PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
};
let in_freq = src_freq / pll.prediv;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_IN.contains(&in_freq));
#[cfg(not(feature = "unchecked-overclocking"))]
let out_freq = in_freq * pll.mul;
assert!(max::PLL_OUT.contains(&out_freq));
@ -238,15 +243,16 @@ pub(crate) unsafe fn init(config: Config) {
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
#[cfg(stm32f0)]
let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::HCLK.contains(&hclk));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(stm32f0))]
#[cfg(all(not(feature = "unchecked-overclocking"), not(stm32f0)))]
assert!(max::PCLK2.contains(&pclk2));
#[cfg(stm32f1)]
let adc = pclk2 / config.adc_pre;
#[cfg(stm32f1)]
#[cfg(all(not(feature = "unchecked-overclocking"), stm32f1))]
assert!(max::ADC.contains(&adc));
// Set latency based on HCLK frquency

14
embassy-stm32/src/rcc/f247.rs
View File

@ -169,9 +169,12 @@ pub(crate) unsafe fn init(config: Config) {
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
#[cfg(not(feature = "unchecked-overclocking"))]
{
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -204,10 +207,13 @@ pub(crate) unsafe fn init(config: Config) {
let hclk = sys / config.ahb_pre;
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::SYSCLK.contains(&sys));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::HCLK.contains(&hclk));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK1.contains(&pclk1));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK2.contains(&pclk2));
let rtc = config.ls.init();

19
embassy-stm32/src/rcc/g0.rs
View File

@ -139,9 +139,12 @@ pub(crate) unsafe fn init(config: Config) {
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
#[cfg(not(feature = "unchecked-overclocking"))]
{
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -169,9 +172,10 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| {
@ -186,6 +190,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_P.contains(&freq));
freq
});
@ -196,6 +201,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_Q.contains(&freq));
freq
});
@ -206,6 +212,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_R.contains(&freq));
freq
});
@ -228,14 +235,16 @@ pub(crate) unsafe fn init(config: Config) {
Sysclk::PLL1_R => unwrap!(pll.pll_r),
_ => unreachable!(),
};
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK.contains(&pclk1));
let latency = match (config.voltage_range, hclk.0) {

18
embassy-stm32/src/rcc/g4.rs
View File

@ -140,9 +140,12 @@ pub(crate) unsafe fn init(config: Config) {
None
}
Some(hse) => {
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
#[cfg(not(feature = "unchecked-overclocking"))]
{
match hse.mode {
HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
}
RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@ -169,9 +172,11 @@ pub(crate) unsafe fn init(config: Config) {
while RCC.cr().read().pllrdy() {}
let in_freq = src_freq / pll_config.prediv;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_IN.contains(&in_freq));
let internal_freq = in_freq * pll_config.mul;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_VCO.contains(&internal_freq));
RCC.pllcfgr().write(|w| {
@ -186,6 +191,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllpen(true);
});
let freq = internal_freq / div_p;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_P.contains(&freq));
freq
});
@ -196,6 +202,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllqen(true);
});
let freq = internal_freq / div_q;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_Q.contains(&freq));
freq
});
@ -206,6 +213,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllren(true);
});
let freq = internal_freq / div_r;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PLL_R.contains(&freq));
freq
});
@ -229,15 +237,17 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::SYSCLK.contains(&sys));
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys / config.ahb_pre;
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::HCLK.contains(&hclk));
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
assert!(max::PCLK.contains(&pclk2));
#[cfg(not(feature = "unchecked-overclocking"))]
assert!(max::PCLK.contains(&pclk2));
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)