From 9c4df75940023456e92623700a9bb25fe6600196 Mon Sep 17 00:00:00 2001 From: Brian Schwind Date: Fri, 12 Sep 2025 20:02:33 +0900 Subject: [PATCH] Set the alternate bytes register to the correct value when configuring an Ospi command --- embassy-stm32/src/ospi/mod.rs | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs index 4df3b0042..cbd6c8d35 100644 --- a/embassy-stm32/src/ospi/mod.rs +++ b/embassy-stm32/src/ospi/mod.rs @@ -451,11 +451,6 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { // Configure alternate bytes if let Some(ab) = command.alternate_bytes { T::REGS.abr().write(|v| v.set_alternate(ab)); - T::REGS.ccr().modify(|w| { - w.set_abmode(PhaseMode::from_bits(command.abwidth.into())); - w.set_abdtr(command.abdtr); - w.set_absize(SizeInBits::from_bits(command.absize.into())); - }) } // Configure dummy cycles @@ -474,7 +469,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { }); } - // Configure instruction/address/data/communication modes + // Configure instruction/address/alternate bytes/data/communication modes T::REGS.ccr().modify(|w| { w.set_imode(PhaseMode::from_bits(command.iwidth.into())); w.set_idtr(command.idtr); @@ -484,6 +479,10 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> { w.set_addtr(command.addtr); w.set_adsize(SizeInBits::from_bits(command.adsize.into())); + w.set_abmode(PhaseMode::from_bits(command.abwidth.into())); + w.set_abdtr(command.abdtr); + w.set_absize(SizeInBits::from_bits(command.absize.into())); + w.set_dmode(PhaseMode::from_bits(command.dwidth.into())); w.set_ddtr(command.ddtr);