From 1074cc7eaf406647a887fbc1fbe521ae1e8850bc Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 7 Apr 2025 01:04:50 +0200
Subject: [PATCH] stm32/adc: enable interrupt for stm32f1

Co-Authored-By: Tnze <cjd001113@outlook.com>
---
 embassy-stm32/src/adc/f1.rs | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index fa6255c23..3cdc9d8fb 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -4,8 +4,10 @@ use core::task::Poll;
 
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::interrupt::typelevel::Interrupt;
+use crate::interrupt::{self};
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peri};
+use crate::{rcc, Peri};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -20,12 +22,9 @@ pub struct InterruptHandler<T: Instance> {
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
     unsafe fn on_interrupt() {
         if T::regs().sr().read().eoc() {
-            T::regs().cr1().modify(|w| w.set_eocie(false));
-        } else {
-            return;
+            T::regs().cr1().modify(|w| w.set_eocie(false)); // End of Convert interrupt disable
+            T::state().waker.wake();
         }
-
-        T::state().waker.wake();
     }
 }
 
@@ -69,6 +68,9 @@ impl<'d, T: Instance> Adc<'d, T> {
         // One cycle after calibration
         blocking_delay_us((1_000_000 * 1) / Self::freq().0 + 1);
 
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+
         Self {
             adc,
             sample_time: SampleTime::from_bits(0),