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include proper pll divs/divt initialization

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This commit is contained in:
Rick Rogers 2025-07-25 15:03:37 -04:00
parent c37fb51cfe
commit a5a9c02543
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GPG Key ID: 81A2B5FD9B4E4436
2 changed files with 34 additions and 2 deletions
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2
embassy-stm32/build.rs
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@ -1599,7 +1599,7 @@ fn main() {
for e in rcc_registers.ir.enums {
fn is_rcc_name(e: &str) -> bool {
match e {
"Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true,
"Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true,
"Timpre" | "Pllrclkpre" => false,
e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
_ => false,

34
embassy-stm32/src/rcc/h.rs
View File

@ -758,6 +758,12 @@ struct PllOutput {
q: Option<Hertz>,
#[allow(dead_code)]
r: Option<Hertz>,
#[cfg(stm32h7rs)]
#[allow(dead_code)]
s: Option<Hertz>,
#[cfg(stm32h7rs)]
#[allow(dead_code)]
t: Option<Hertz>,
}
fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
@ -776,6 +782,10 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
p: None,
q: None,
r: None,
#[cfg(stm32h7rs)]
s: None,
#[cfg(stm32h7rs)]
t: None,
};
};
@ -823,6 +833,10 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
});
let q = config.divq.map(|div| vco_clk / div);
let r = config.divr.map(|div| vco_clk / div);
#[cfg(stm32h7rs)]
let s = config.divs.map(|div| vco_clk / div);
#[cfg(stm32h7rs)]
let t = config.divt.map(|div| vco_clk / div);
#[cfg(stm32h5)]
RCC.pllcfgr(num).write(|w| {
@ -849,6 +863,10 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
w.set_divpen(num, p.is_some());
w.set_divqen(num, q.is_some());
w.set_divren(num, r.is_some());
#[cfg(stm32h7rs)]
w.set_divsen(num, s.is_some());
#[cfg(stm32h7rs)]
w.set_divten(num, t.is_some());
});
}
@ -859,10 +877,24 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
w.set_pllr(config.divr.unwrap_or(PllDiv::DIV2));
});
#[cfg(stm32h7rs)]
RCC.plldivr2(num).write(|w| {
w.set_plls(config.divs.unwrap_or(Plldivst::DIV2));
w.set_pllt(config.divt.unwrap_or(Plldivst::DIV2));
});
RCC.cr().modify(|w| w.set_pllon(num, true));
while !RCC.cr().read().pllrdy(num) {}
PllOutput { p, q, r }
PllOutput {
p,
q,
r,
#[cfg(stm32h7rs)]
s,
#[cfg(stm32h7rs)]
t,
}
}
fn flash_setup(clk: Hertz, vos: VoltageScale) {