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https://github.com/embassy-rs/embassy.git
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Merge pull request #4674 from per42/adc_v3-enums
ADC v3: Migrate to stm32-data g0 with enums
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
ab81b797c2
@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- feat: derive Clone, Copy and defmt::Format for all *SPI-related configs
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- fix: handle address and data-length errors in OSPI
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- feat: Allow OSPI DMA writes larger than 64kB using chunking
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- feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times
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## 0.4.0 - 2025-08-26
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@ -174,7 +174,7 @@ futures-util = { version = "0.3.30", default-features = false }
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sdio-host = "0.9.0"
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critical-section = "1.1"
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#stm32-metapac = { version = "18" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d8432edd0406495adec19d31923584e80b8e03cb" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7" }
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vcell = "0.1.3"
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nb = "1.0.0"
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@ -192,6 +192,7 @@ bitflags = "2.4.2"
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block-device-driver = { version = "0.2" }
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aligned = "0.4.1"
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heapless = "0.9.1"
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[dev-dependencies]
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critical-section = { version = "1.1", features = ["std"] }
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@ -203,7 +204,7 @@ proc-macro2 = "1.0.36"
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quote = "1.0.15"
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#stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d8432edd0406495adec19d31923584e80b8e03cb", default-features = false, features = ["metadata"] }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7", default-features = false, features = ["metadata"] }
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[features]
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default = ["rt"]
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@ -1,7 +1,13 @@
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use cfg_if::cfg_if;
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#[cfg(adc_g0)]
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use heapless::Vec;
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use pac::adc::vals::Dmacfg;
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#[cfg(adc_g0)]
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use pac::adc::vals::{Ckmode, Smpsel};
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#[cfg(adc_v3)]
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use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
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#[cfg(adc_g0)]
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pub use pac::adc::vals::{Ovsr, Ovss, Presc};
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use super::{
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blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
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@ -14,6 +20,11 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
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/// VREF voltage used for factory calibration of VREFINTCAL register.
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pub const VREF_CALIB_MV: u32 = 3000;
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#[cfg(adc_g0)]
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/// The number of variants in Smpsel
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// TODO: Use [#![feature(variant_count)]](https://github.com/rust-lang/rust/issues/73662) when stable
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const SAMPLE_TIMES_CAPACITY: usize = 2;
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pub struct VrefInt;
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impl<T: Instance> AdcChannel<T> for VrefInt {}
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impl<T: Instance> SealedAdcChannel<T> for VrefInt {
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@ -113,30 +124,10 @@ pub enum Averaging {
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cfg_if! { if #[cfg(adc_g0)] {
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/// Synchronous PCLK prescaler
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/// * ADC_CFGR2:CKMODE in STM32WL5x
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#[repr(u8)]
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pub enum CkModePclk {
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DIV1 = 3,
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DIV2 = 1,
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DIV4 = 2,
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}
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/// Asynchronous ADCCLK prescaler
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/// * ADC_CCR:PRESC in STM32WL5x
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#[repr(u8)]
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pub enum Presc {
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DIV1,
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DIV2,
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DIV4,
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DIV6,
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DIV8,
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DIV10,
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DIV12,
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DIV16,
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DIV32,
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DIV64,
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DIV128,
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DIV256,
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}
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/// The analog clock is either the synchronous prescaled PCLK or
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@ -215,8 +206,14 @@ impl<'d, T: Instance> Adc<'d, T> {
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}
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}
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match clock {
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Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div as u8)),
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Clock::Sync { div } => T::regs().cfgr2().modify(|reg| reg.set_ckmode(div as u8)),
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Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
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Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
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reg.set_ckmode(match div {
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CkModePclk::DIV1 => Ckmode::PCLK,
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CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
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CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
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})
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}),
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}
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Self::init_calibrate();
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@ -436,53 +433,78 @@ impl<'d, T: Instance> Adc<'d, T> {
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w.set_l(sequence.len() as u8 - 1);
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});
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#[cfg(any(adc_g0, adc_u0))]
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let mut channel_mask = 0;
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#[cfg(adc_g0)]
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{
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let mut sample_times = Vec::<SampleTime, SAMPLE_TIMES_CAPACITY>::new();
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// Configure channels and ranks
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for (_i, (channel, sample_time)) in sequence.enumerate() {
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Self::configure_channel(channel, sample_time);
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// Each channel is sampled according to sequence
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#[cfg(not(any(adc_g0, adc_u0)))]
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match _i {
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0..=3 => {
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T::regs().sqr1().modify(|w| {
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w.set_sq(_i, channel.channel());
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});
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}
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4..=8 => {
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T::regs().sqr2().modify(|w| {
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w.set_sq(_i - 4, channel.channel());
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});
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}
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9..=13 => {
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T::regs().sqr3().modify(|w| {
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w.set_sq(_i - 9, channel.channel());
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});
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}
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14..=15 => {
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T::regs().sqr4().modify(|w| {
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w.set_sq(_i - 14, channel.channel());
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});
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}
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_ => unreachable!(),
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}
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#[cfg(any(adc_g0, adc_u0))]
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{
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channel_mask |= 1 << channel.channel();
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}
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T::regs().chselr().write(|chselr| {
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T::regs().smpr().write(|smpr| {
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for (channel, sample_time) in sequence {
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chselr.set_chsel(channel.channel.into(), true);
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if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
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smpr.set_smpsel(channel.channel.into(), (i as u8).into());
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} else {
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smpr.set_sample_time(sample_times.len(), sample_time);
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if let Err(_) = sample_times.push(sample_time) {
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panic!(
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"Implementation is limited to {} unique sample times among all channels.",
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SAMPLE_TIMES_CAPACITY
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);
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}
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}
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}
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})
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});
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}
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#[cfg(not(adc_g0))]
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{
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#[cfg(adc_u0)]
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let mut channel_mask = 0;
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// On G0 and U0 enabled channels are sampled from 0 to last channel.
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// It is possible to add up to 8 sequences if CHSELRMOD = 1.
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// However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
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#[cfg(any(adc_g0, adc_u0))]
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T::regs().chselr().modify(|reg| {
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reg.set_chsel(channel_mask);
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});
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// Configure channels and ranks
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for (_i, (channel, sample_time)) in sequence.enumerate() {
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Self::configure_channel(channel, sample_time);
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// Each channel is sampled according to sequence
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#[cfg(not(any(adc_g0, adc_u0)))]
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match _i {
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0..=3 => {
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T::regs().sqr1().modify(|w| {
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w.set_sq(_i, channel.channel());
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});
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}
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4..=8 => {
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T::regs().sqr2().modify(|w| {
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w.set_sq(_i - 4, channel.channel());
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});
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}
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9..=13 => {
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T::regs().sqr3().modify(|w| {
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w.set_sq(_i - 9, channel.channel());
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});
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}
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14..=15 => {
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T::regs().sqr4().modify(|w| {
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w.set_sq(_i - 14, channel.channel());
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});
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}
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_ => unreachable!(),
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}
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#[cfg(adc_u0)]
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{
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channel_mask |= 1 << channel.channel();
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}
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}
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// On G0 and U0 enabled channels are sampled from 0 to last channel.
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// It is possible to add up to 8 sequences if CHSELRMOD = 1.
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// However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
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#[cfg(adc_u0)]
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T::regs().chselr().modify(|reg| {
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reg.set_chsel(channel_mask);
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});
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}
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// Set continuous mode with oneshot dma.
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// Clear overrun flag before starting transfer.
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T::regs().isr().modify(|reg| {
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@ -537,6 +559,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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});
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}
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#[cfg(not(adc_g0))]
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fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
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// RM0492, RM0481, etc.
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// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
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@ -551,13 +574,23 @@ impl<'d, T: Instance> Adc<'d, T> {
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fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
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self.enable();
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#[cfg(not(adc_g0))]
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Self::configure_channel(channel, self.sample_time);
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#[cfg(adc_g0)]
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T::regs().smpr().write(|reg| {
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reg.set_sample_time(0, self.sample_time);
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reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
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});
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// Select channel
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#[cfg(not(any(adc_g0, adc_u0)))]
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T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
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#[cfg(any(adc_g0, adc_u0))]
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T::regs().chselr().write(|reg| reg.set_chsel(1 << channel.channel()));
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T::regs().chselr().write(|reg| {
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#[cfg(adc_g0)]
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reg.set_chsel(channel.channel().into(), true);
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#[cfg(adc_u0)]
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reg.set_chsel(1 << channel.channel());
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});
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// Some models are affected by an erratum:
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// If we perform conversions slower than 1 kHz, the first read ADC value can be
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@ -581,12 +614,20 @@ impl<'d, T: Instance> Adc<'d, T> {
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val
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}
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#[cfg(any(adc_g0, adc_u0))]
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#[cfg(adc_g0)]
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pub fn set_oversampling_shift(&mut self, shift: Ovss) {
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T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
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}
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#[cfg(adc_u0)]
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pub fn set_oversampling_shift(&mut self, shift: u8) {
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T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
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}
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#[cfg(any(adc_g0, adc_u0))]
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#[cfg(adc_g0)]
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pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
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T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
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}
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#[cfg(adc_u0)]
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pub fn set_oversampling_ratio(&mut self, ratio: u8) {
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T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
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}
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@ -613,9 +654,10 @@ impl<'d, T: Instance> Adc<'d, T> {
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T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
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}
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#[cfg(not(adc_g0))]
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fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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cfg_if! {
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if #[cfg(any(adc_g0, adc_u0))] {
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if #[cfg(adc_u0)] {
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// On G0 and U6 all channels use the same sampling time.
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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@ -7,7 +7,7 @@
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_stm32::adc::{Adc, Clock, Presc, SampleTime};
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use embassy_stm32::adc::{Adc, Clock, Ovsr, Ovss, Presc, SampleTime};
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use embassy_time::Timer;
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use {defmt_rtt as _, panic_probe as _};
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@ -20,19 +20,8 @@ async fn main(_spawner: Spawner) {
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adc.set_sample_time(SampleTime::CYCLES1_5);
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let mut pin = p.PA1;
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// From https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
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// page373 15.8 Oversampler
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// Table 76. Maximum output results vs N and M. Grayed values indicates truncation
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// 0x00 oversampling ratio X2
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// 0x01 oversampling ratio X4
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// 0x02 oversampling ratio X8
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// 0x03 oversampling ratio X16
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// 0x04 oversampling ratio X32
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// 0x05 oversampling ratio X64
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// 0x06 oversampling ratio X128
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// 0x07 oversampling ratio X256
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adc.set_oversampling_ratio(0x03);
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adc.set_oversampling_shift(0b0000);
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adc.set_oversampling_ratio(Ovsr::MUL16);
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adc.set_oversampling_shift(Ovss::NO_SHIFT);
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adc.oversampling_enable(true);
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loop {
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