diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index a7137d132..5ef2366d9 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -72,7 +72,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f1297385e91f061fcb6134bb25f51e12d8abff93" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-34c0188a682b32c32ff147d377e0629b1ebe8318" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -97,7 +97,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f1297385e91f061fcb6134bb25f51e12d8abff93", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-34c0188a682b32c32ff147d377e0629b1ebe8318", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index cc30302b9..b77a3415b 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -21,7 +21,7 @@ pub enum HsemError {
 /// chip family (i.e. stm32h747 see rm0399 table 95)
 #[derive(Debug, PartialEq, Eq, Clone, Copy, Hash)]
 #[repr(u8)]
-#[derive(defmt::Format)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum CoreId {
     #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
     /// Cortex-M7, core 1.
@@ -36,7 +36,7 @@ pub enum CoreId {
     Core0 = 0x4,
 
     #[cfg(any(stm32wb, stm32wl))]
-    // Cortex-M0+, core 2.
+    /// Cortex-M0+, core 2.
     Core1 = 0x8,
 }
 
@@ -66,6 +66,7 @@ pub fn get_current_coreid() -> CoreId {
 fn core_id_to_index(core: CoreId) -> usize {
     match core {
         CoreId::Core0 => 0,
+        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
         CoreId::Core1 => 1,
     }
 }