From 90404a8e524a0d06ce35230dea7ff4d3e4d0375a Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 02:17:54 +0200 Subject: [PATCH 01/22] Add intercore communication examples for STM32H755CM4 and CM7, does not work in release for now (for some reason) --- examples/stm32h755cm4/Cargo.toml | 17 +- examples/stm32h755cm4/src/bin/intercore.rs | 181 +++++++++++++++++ examples/stm32h755cm7/Cargo.toml | 15 +- examples/stm32h755cm7/src/bin/intercore.rs | 226 +++++++++++++++++++++ 4 files changed, 415 insertions(+), 24 deletions(-) create mode 100644 examples/stm32h755cm4/src/bin/intercore.rs create mode 100644 examples/stm32h755cm7/src/bin/intercore.rs diff --git a/examples/stm32h755cm4/Cargo.toml b/examples/stm32h755cm4/Cargo.toml index 7c17bc766..c6d4996f1 100644 --- a/examples/stm32h755cm4/Cargo.toml +++ b/examples/stm32h755cm4/Cargo.toml @@ -15,8 +15,8 @@ embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defm embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] } embassy-futures = { version = "0.1.0", path = "../../embassy-futures" } -defmt = "0.3" -defmt-rtt = "0.4" +defmt = "1.0.1" +defmt-rtt = "1.0.0" cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] } cortex-m-rt = "0.7.0" @@ -25,7 +25,7 @@ embedded-hal-1 = { package = "embedded-hal", version = "1.0" } embedded-hal-async = { version = "1.0" } embedded-nal-async = "0.8.0" embedded-io-async = { version = "0.6.1" } -panic-probe = { version = "0.3", features = ["print-defmt"] } +panic-probe = { version = "1.0.0", features = ["print-defmt"] } heapless = { version = "0.8", default-features = false } rand_core = "0.6.3" critical-section = "1.1" @@ -37,13 +37,6 @@ chrono = { version = "^0.4", default-features = false } grounded = "0.2.0" # cargo build/run -[profile.dev] -codegen-units = 1 -debug = 2 -debug-assertions = true # <- -incremental = false -opt-level = 3 # <- -overflow-checks = true # <- # cargo test [profile.test] @@ -60,8 +53,8 @@ codegen-units = 1 debug = 2 debug-assertions = false # <- incremental = false -lto = 'fat' -opt-level = 3 # <- +#lto = 'fat' +#opt-level = 3 # <- overflow-checks = false # <- # cargo test --release diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs new file mode 100644 index 000000000..08cf6c7b9 --- /dev/null +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -0,0 +1,181 @@ +#![no_std] +#![no_main] + +// IMPORTANT: This must match EXACTLY the definition in CM7! +mod shared { + use core::sync::atomic::{AtomicU32, Ordering}; + + /// Shared LED state between CM7 and CM4 cores + #[repr(C, align(4))] + pub struct SharedLedState { + // Magic number for validation + pub magic: AtomicU32, + // Counter for synchronization testing + pub counter: AtomicU32, + // LED states packed into a single atomic + pub led_states: AtomicU32, + } + + // Bit positions in led_states + pub const GREEN_LED_BIT: u32 = 0; + pub const YELLOW_LED_BIT: u32 = 1; + + impl SharedLedState { + pub const fn new() -> Self { + Self { + magic: AtomicU32::new(0xDEADBEEF), // Magic number + counter: AtomicU32::new(0), + led_states: AtomicU32::new(0), + } + } + + /// Set LED state using safe bit operations + #[inline(never)] + pub fn set_led(&self, is_green: bool, state: bool) { + let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; + + // Use bit operations to avoid complex atomic operations + let current = self.led_states.load(Ordering::SeqCst); + + let new_value = if state { + current | (1 << bit) // Set bit + } else { + current & !(1 << bit) // Clear bit + }; + + self.led_states.store(new_value, Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + } + + /// Get LED state using safe bit operations + #[inline(never)] + pub fn get_led(&self, is_green: bool) -> bool { + let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; + + let value = self.led_states.load(Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + + (value & (1 << bit)) != 0 + } + + /// Increment counter safely + #[inline(never)] + pub fn increment_counter(&self) -> u32 { + let current = self.counter.load(Ordering::SeqCst); + let new_value = current.wrapping_add(1); + self.counter.store(new_value, Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + new_value + } + + /// Get counter without incrementing + #[inline(never)] + pub fn get_counter(&self) -> u32 { + let value = self.counter.load(Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + value + } + } + + #[link_section = ".ram_d3"] + pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); + + // SRAM4 memory region constants for MPU configuration + pub const SRAM4_BASE_ADDRESS: u32 = 0x38000000; + pub const SRAM4_SIZE_LOG2: u32 = 15; // 64KB = 2^(15+1) + pub const SRAM4_REGION_NUMBER: u8 = 0; // MPU region number to use +} + +use core::mem::MaybeUninit; +use defmt::*; +use embassy_executor::Spawner; +use embassy_stm32::gpio::{Level, Output, Speed}; +use embassy_stm32::SharedData; +use embassy_time::Timer; +use {defmt_rtt as _, panic_probe as _}; + +// Use our shared state from the module +use shared::SHARED_LED_STATE; + +#[link_section = ".ram_d3"] +static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); + +#[embassy_executor::task] +async fn blink_heartbeat(mut led: Output<'static>) { + loop { + led.toggle(); + info!("CM4 heartbeat"); + Timer::after_millis(500).await; + } +} + +#[embassy_executor::main] +async fn main(spawner: Spawner) -> ! { + // Initialize the secondary core + let p = embassy_stm32::init_secondary(&SHARED_DATA); + info!("CM4 core initialized!"); + + // Read the magic value to ensure shared memory is accessible + let magic = SHARED_LED_STATE.magic.load(core::sync::atomic::Ordering::SeqCst); + info!("CM4: Magic value = 0x{:X}", magic); + + // Initialize LEDs + let mut green_led = Output::new(p.PB0, Level::Low, Speed::Low); // LD1 + let mut yellow_led = Output::new(p.PE1, Level::Low, Speed::Low); // LD2 + let red_led = Output::new(p.PB14, Level::Low, Speed::Low); // LD3 (heartbeat) + + // Start heartbeat task + unwrap!(spawner.spawn(blink_heartbeat(red_led))); + + // Previous values for detecting changes + let mut prev_green = false; + let mut prev_yellow = false; + let mut prev_counter = 0; + + info!("CM4: Starting main loop"); + loop { + // Read values from shared memory + let green_state = SHARED_LED_STATE.get_led(true); + let yellow_state = SHARED_LED_STATE.get_led(false); + let counter = SHARED_LED_STATE.get_counter(); + + // Check for state changes + let green_changed = green_state != prev_green; + let yellow_changed = yellow_state != prev_yellow; + let counter_changed = counter != prev_counter; + + // If any state changed, log it and update LEDs + if green_changed || yellow_changed || counter_changed { + if counter_changed { + info!("CM4: Counter = {}", counter); + prev_counter = counter; + } + + // Update LED states + if green_changed { + if green_state { + green_led.set_high(); + info!("CM4: Green LED ON"); + } else { + green_led.set_low(); + info!("CM4: Green LED OFF"); + } + prev_green = green_state; + } + + if yellow_changed { + if yellow_state { + yellow_led.set_high(); + info!("CM4: Yellow LED ON"); + } else { + yellow_led.set_low(); + info!("CM4: Yellow LED OFF"); + } + prev_yellow = yellow_state; + } + } + + // Poll at a reasonable rate + Timer::after_millis(10).await; + } +} \ No newline at end of file diff --git a/examples/stm32h755cm7/Cargo.toml b/examples/stm32h755cm7/Cargo.toml index 3186929a8..06a3b06af 100644 --- a/examples/stm32h755cm7/Cargo.toml +++ b/examples/stm32h755cm7/Cargo.toml @@ -15,8 +15,8 @@ embassy-net = { version = "0.7.0", path = "../../embassy-net", features = ["defm embassy-usb = { version = "0.4.0", path = "../../embassy-usb", features = ["defmt"] } embassy-futures = { version = "0.1.0", path = "../../embassy-futures" } -defmt = "0.3" -defmt-rtt = "0.4" +defmt = "1.0.1" +defmt-rtt = "1.0.0" cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] } cortex-m-rt = "0.7.0" @@ -25,7 +25,7 @@ embedded-hal-1 = { package = "embedded-hal", version = "1.0" } embedded-hal-async = { version = "1.0" } embedded-nal-async = "0.8.0" embedded-io-async = { version = "0.6.1" } -panic-probe = { version = "0.3", features = ["print-defmt"] } +panic-probe = { version = "1.0.0", features = ["print-defmt"] } heapless = { version = "0.8", default-features = false } rand_core = "0.6.3" critical-section = "1.1" @@ -36,15 +36,6 @@ static_cell = "2" chrono = { version = "^0.4", default-features = false } grounded = "0.2.0" -# cargo build/run -[profile.dev] -codegen-units = 1 -debug = 2 -debug-assertions = true # <- -incremental = false -opt-level = 3 # <- -overflow-checks = true # <- - # cargo test [profile.test] codegen-units = 1 diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs new file mode 100644 index 000000000..154b1682b --- /dev/null +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -0,0 +1,226 @@ +#![no_std] +#![no_main] + +mod shared { + use core::sync::atomic::{AtomicU32, Ordering}; + + /// Shared LED state between CM7 and CM4 cores + #[repr(C, align(4))] + pub struct SharedLedState { + // Magic number for validation + pub magic: AtomicU32, + // Counter for synchronization testing + pub counter: AtomicU32, + // LED states packed into a single atomic + pub led_states: AtomicU32, + } + + // Bit positions in led_states + pub const GREEN_LED_BIT: u32 = 0; + pub const YELLOW_LED_BIT: u32 = 1; + + impl SharedLedState { + pub const fn new() -> Self { + Self { + magic: AtomicU32::new(0xDEADBEEF), // Magic number + counter: AtomicU32::new(0), + led_states: AtomicU32::new(0), + } + } + + /// Set LED state using safe bit operations + #[inline(never)] + pub fn set_led(&self, is_green: bool, state: bool) { + let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; + + // Use bit operations to avoid complex atomic operations + let current = self.led_states.load(Ordering::SeqCst); + + let new_value = if state { + current | (1 << bit) // Set bit + } else { + current & !(1 << bit) // Clear bit + }; + + self.led_states.store(new_value, Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + } + + /// Get LED state using safe bit operations + #[inline(never)] + pub fn get_led(&self, is_green: bool) -> bool { + let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; + + let value = self.led_states.load(Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + + (value & (1 << bit)) != 0 + } + + /// Increment counter safely + #[inline(never)] + pub fn increment_counter(&self) -> u32 { + let current = self.counter.load(Ordering::SeqCst); + let new_value = current.wrapping_add(1); + self.counter.store(new_value, Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + new_value + } + + /// Get counter without incrementing + #[inline(never)] + pub fn get_counter(&self) -> u32 { + let value = self.counter.load(Ordering::SeqCst); + core::sync::atomic::compiler_fence(Ordering::SeqCst); + value + } + } + + #[link_section = ".ram_d3"] + pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); + + // SRAM4 memory region constants for MPU configuration + pub const SRAM4_BASE_ADDRESS: u32 = 0x38000000; + pub const SRAM4_SIZE_LOG2: u32 = 15; // 64KB = 2^(15+1) + pub const SRAM4_REGION_NUMBER: u8 = 0; // MPU region number to use +} + +use core::mem::MaybeUninit; +use defmt::*; +use embassy_executor::Spawner; +use embassy_stm32::{Config, SharedData}; +use embassy_time::Timer; +use {defmt_rtt as _, panic_probe as _}; + +// Import cortex_m for MPU configuration +use cortex_m::peripheral::{MPU, SCB}; +use cortex_m::asm; + +// Use our shared state from the module +use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; + +#[link_section = ".ram_d3"] +static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); + +// Function to configure MPU with your provided settings +fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) { + // Ensure all operations complete before reconfiguring MPU/caches + asm::dmb(); + unsafe { + // Disable MPU + mpu.ctrl.write(0); + + // Configure SRAM4 as non-cacheable + // Set region number (0) + mpu.rnr.write(SRAM4_REGION_NUMBER as u32); + + // Set base address (SRAM4 = 0x38000000) with VALID bit and region number + mpu.rbar.write( + SRAM4_BASE_ADDRESS | + (1 << 4) // Region number = 0 (explicit in RBAR) + ); + + // Configure region attributes: + // SIZE=15 (64KB = 2^(15+1)) + // ENABLE=1 + // AP=3 (Full access) + // TEX=1, S=1, C=0, B=0 (Normal memory, Non-cacheable, Shareable) + let rasr_value: u32 = (SRAM4_SIZE_LOG2 << 1) | // SIZE=15 (64KB) + (1 << 0) | // ENABLE=1 + (3 << 24) | // AP=3 (Full access) + (1 << 19) | // TEX=1 + (1 << 18); // S=1 (Shareable) + + mpu.rasr.write(rasr_value); + + // Enable MPU with default memory map as background + mpu.ctrl.write(1 | (1 << 2)); // MPU_ENABLE | PRIVDEFENA + } + + // Ensure changes are committed + asm::dsb(); + asm::isb(); + + info!("MPU configured - SRAM4 set as non-cacheable"); +} + +#[embassy_executor::main] +async fn main(spawner: Spawner) -> ! { + // Configure MPU to make SRAM4 non-cacheable + { + let mut cp = cortex_m::Peripherals::take().unwrap(); + let mpu = &mut cp.MPU; + let scb = &mut cp.SCB; + + // Configure MPU without disabling caches + configure_mpu_non_cacheable(mpu, scb); + } + + // Configure the clocks + let mut config = Config::default(); + { + use embassy_stm32::rcc::*; + config.rcc.hsi = Some(HSIPrescaler::DIV1); + config.rcc.csi = true; + config.rcc.hsi48 = Some(Default::default()); + config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, + prediv: PllPreDiv::DIV4, + mul: PllMul::MUL50, + divp: Some(PllDiv::DIV2), + divq: Some(PllDiv::DIV8), + divr: None, + }); + config.rcc.sys = Sysclk::PLL1_P; + config.rcc.ahb_pre = AHBPrescaler::DIV2; + config.rcc.apb1_pre = APBPrescaler::DIV2; + config.rcc.apb2_pre = APBPrescaler::DIV2; + config.rcc.apb3_pre = APBPrescaler::DIV2; + config.rcc.apb4_pre = APBPrescaler::DIV2; + config.rcc.voltage_scale = VoltageScale::Scale1; + config.rcc.supply_config = SupplyConfig::DirectSMPS; + } + + // Initialize the CM7 core + let _p = embassy_stm32::init_primary(config, &SHARED_DATA); + info!("CM7 core initialized with non-cacheable SRAM4!"); + + // Read the magic value to ensure shared memory is accessible + let magic = SHARED_LED_STATE.magic.load(core::sync::atomic::Ordering::SeqCst); + info!("CM7: Magic value = 0x{:X}", magic); + + // Initialize shared memory state + SHARED_LED_STATE.set_led(true, false); // Green LED off + SHARED_LED_STATE.set_led(false, false); // Yellow LED off + + // Main loop - update shared memory values + let mut green_state = false; + let mut yellow_state = false; + let mut loop_count = 0; + + info!("CM7: Starting main loop"); + loop { + // Update loop counter + loop_count += 1; + + // Update shared counter + let counter = SHARED_LED_STATE.increment_counter(); + + // Every second, toggle green LED state + if loop_count % 10 == 0 { + green_state = !green_state; + SHARED_LED_STATE.set_led(true, green_state); + info!("CM7: Counter = {}, Set green LED to {}", counter, green_state); + } + + // Every 3 seconds, toggle yellow LED state + if loop_count % 30 == 0 { + yellow_state = !yellow_state; + SHARED_LED_STATE.set_led(false, yellow_state); + info!("CM7: Counter = {}, Set yellow LED to {}", counter, yellow_state); + } + + // Wait 100ms before next cycle + Timer::after_millis(100).await; + } +} \ No newline at end of file From cf60b110668f1650836f7d81bf41b629603ae6d6 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 02:22:48 +0200 Subject: [PATCH 02/22] rustfmt --- examples/stm32h755cm4/src/bin/intercore.rs | 8 ++++---- examples/stm32h755cm7/src/bin/intercore.rs | 17 ++++++++--------- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 08cf6c7b9..7b2406e76 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -120,9 +120,9 @@ async fn main(spawner: Spawner) -> ! { info!("CM4: Magic value = 0x{:X}", magic); // Initialize LEDs - let mut green_led = Output::new(p.PB0, Level::Low, Speed::Low); // LD1 - let mut yellow_led = Output::new(p.PE1, Level::Low, Speed::Low); // LD2 - let red_led = Output::new(p.PB14, Level::Low, Speed::Low); // LD3 (heartbeat) + let mut green_led = Output::new(p.PB0, Level::Low, Speed::Low); // LD1 + let mut yellow_led = Output::new(p.PE1, Level::Low, Speed::Low); // LD2 + let red_led = Output::new(p.PB14, Level::Low, Speed::Low); // LD3 (heartbeat) // Start heartbeat task unwrap!(spawner.spawn(blink_heartbeat(red_led))); @@ -178,4 +178,4 @@ async fn main(spawner: Spawner) -> ! { // Poll at a reasonable rate Timer::after_millis(10).await; } -} \ No newline at end of file +} diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index 154b1682b..5783d05e1 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -75,7 +75,7 @@ mod shared { value } } - + #[link_section = ".ram_d3"] pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); @@ -93,8 +93,8 @@ use embassy_time::Timer; use {defmt_rtt as _, panic_probe as _}; // Import cortex_m for MPU configuration -use cortex_m::peripheral::{MPU, SCB}; use cortex_m::asm; +use cortex_m::peripheral::{MPU, SCB}; // Use our shared state from the module use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; @@ -116,8 +116,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) { // Set base address (SRAM4 = 0x38000000) with VALID bit and region number mpu.rbar.write( - SRAM4_BASE_ADDRESS | - (1 << 4) // Region number = 0 (explicit in RBAR) + SRAM4_BASE_ADDRESS | (1 << 4), // Region number = 0 (explicit in RBAR) ); // Configure region attributes: @@ -129,7 +128,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) { (1 << 0) | // ENABLE=1 (3 << 24) | // AP=3 (Full access) (1 << 19) | // TEX=1 - (1 << 18); // S=1 (Shareable) + (1 << 18); // S=1 (Shareable) mpu.rasr.write(rasr_value); @@ -151,7 +150,7 @@ async fn main(spawner: Spawner) -> ! { let mut cp = cortex_m::Peripherals::take().unwrap(); let mpu = &mut cp.MPU; let scb = &mut cp.SCB; - + // Configure MPU without disabling caches configure_mpu_non_cacheable(mpu, scb); } @@ -190,9 +189,9 @@ async fn main(spawner: Spawner) -> ! { info!("CM7: Magic value = 0x{:X}", magic); // Initialize shared memory state - SHARED_LED_STATE.set_led(true, false); // Green LED off + SHARED_LED_STATE.set_led(true, false); // Green LED off SHARED_LED_STATE.set_led(false, false); // Yellow LED off - + // Main loop - update shared memory values let mut green_state = false; let mut yellow_state = false; @@ -223,4 +222,4 @@ async fn main(spawner: Spawner) -> ! { // Wait 100ms before next cycle Timer::after_millis(100).await; } -} \ No newline at end of file +} From 65f67694a964b217c55b5f6eb15d2a6830ea0ec3 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 02:34:33 +0200 Subject: [PATCH 03/22] Add #[allow(dead_code] attributes and rename spawner variable --- examples/stm32h755cm7/src/bin/intercore.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index 5783d05e1..464357185 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -48,6 +48,7 @@ mod shared { /// Get LED state using safe bit operations #[inline(never)] + #[allow(dead_code)] pub fn get_led(&self, is_green: bool) -> bool { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; @@ -69,6 +70,7 @@ mod shared { /// Get counter without incrementing #[inline(never)] + #[allow(dead_code)] pub fn get_counter(&self) -> u32 { let value = self.counter.load(Ordering::SeqCst); core::sync::atomic::compiler_fence(Ordering::SeqCst); @@ -144,7 +146,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) { } #[embassy_executor::main] -async fn main(spawner: Spawner) -> ! { +async fn main(_spawner: Spawner) -> ! { // Configure MPU to make SRAM4 non-cacheable { let mut cp = cortex_m::Peripherals::take().unwrap(); From 6b84bf5137eb9ab0dc6b4ebd049cd68f571a78a6 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 02:36:36 +0200 Subject: [PATCH 04/22] formatting --- examples/stm32h755cm7/src/bin/intercore.rs | 25 ++++++++++------------ 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index 464357185..f01d6a6b7 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -1,6 +1,17 @@ #![no_std] #![no_main] +use core::mem::MaybeUninit; + +use cortex_m::asm; +use cortex_m::peripheral::{MPU, SCB}; +use defmt::*; +use embassy_executor::Spawner; +use embassy_stm32::{Config, SharedData}; +use embassy_time::Timer; +use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; +use {defmt_rtt as _, panic_probe as _}; + mod shared { use core::sync::atomic::{AtomicU32, Ordering}; @@ -87,20 +98,6 @@ mod shared { pub const SRAM4_REGION_NUMBER: u8 = 0; // MPU region number to use } -use core::mem::MaybeUninit; -use defmt::*; -use embassy_executor::Spawner; -use embassy_stm32::{Config, SharedData}; -use embassy_time::Timer; -use {defmt_rtt as _, panic_probe as _}; - -// Import cortex_m for MPU configuration -use cortex_m::asm; -use cortex_m::peripheral::{MPU, SCB}; - -// Use our shared state from the module -use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; - #[link_section = ".ram_d3"] static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); From f52c77693e119095270df36a9acdb92130afa755 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 08:41:44 +0200 Subject: [PATCH 05/22] formatting again --- examples/stm32h755cm4/src/bin/intercore.rs | 4 ++-- examples/stm32h755cm7/src/bin/intercore.rs | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 7b2406e76..d38b34365 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -87,15 +87,15 @@ mod shared { } use core::mem::MaybeUninit; + use defmt::*; use embassy_executor::Spawner; use embassy_stm32::gpio::{Level, Output, Speed}; use embassy_stm32::SharedData; use embassy_time::Timer; -use {defmt_rtt as _, panic_probe as _}; - // Use our shared state from the module use shared::SHARED_LED_STATE; +use {defmt_rtt as _, panic_probe as _}; #[link_section = ".ram_d3"] static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index f01d6a6b7..ab5ed6364 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -2,7 +2,6 @@ #![no_main] use core::mem::MaybeUninit; - use cortex_m::asm; use cortex_m::peripheral::{MPU, SCB}; use defmt::*; From d9befca44f3e35c14fef85744d19bbacc4a76de3 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 08:45:29 +0200 Subject: [PATCH 06/22] dead code, formatting, ci, we're good --- examples/stm32h755cm4/src/bin/intercore.rs | 7 ++----- examples/stm32h755cm7/src/bin/intercore.rs | 1 + 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index d38b34365..8f61c3eb2 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -31,6 +31,7 @@ mod shared { /// Set LED state using safe bit operations #[inline(never)] + #[allow(dead_code)] pub fn set_led(&self, is_green: bool, state: bool) { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; @@ -60,6 +61,7 @@ mod shared { /// Increment counter safely #[inline(never)] + #[allow(dead_code)] pub fn increment_counter(&self) -> u32 { let current = self.counter.load(Ordering::SeqCst); let new_value = current.wrapping_add(1); @@ -79,11 +81,6 @@ mod shared { #[link_section = ".ram_d3"] pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); - - // SRAM4 memory region constants for MPU configuration - pub const SRAM4_BASE_ADDRESS: u32 = 0x38000000; - pub const SRAM4_SIZE_LOG2: u32 = 15; // 64KB = 2^(15+1) - pub const SRAM4_REGION_NUMBER: u8 = 0; // MPU region number to use } use core::mem::MaybeUninit; diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index ab5ed6364..f01d6a6b7 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -2,6 +2,7 @@ #![no_main] use core::mem::MaybeUninit; + use cortex_m::asm; use cortex_m::peripheral::{MPU, SCB}; use defmt::*; From 04c0bd84e6043ac35d2a20f1f4a789ccf79bb316 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 10:04:34 +0200 Subject: [PATCH 07/22] fix release mode that was broken by lto and codegen units (there are probably things that can be done to be able to keep lto, I haven't found yet) --- examples/stm32h755cm4/Cargo.toml | 5 ++--- examples/stm32h755cm4/src/bin/intercore.rs | 8 ++++---- examples/stm32h755cm7/Cargo.toml | 3 +-- examples/stm32h755cm7/src/bin/intercore.rs | 18 +++++++++++++----- 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/examples/stm32h755cm4/Cargo.toml b/examples/stm32h755cm4/Cargo.toml index c6d4996f1..d2b9b1f0e 100644 --- a/examples/stm32h755cm4/Cargo.toml +++ b/examples/stm32h755cm4/Cargo.toml @@ -49,12 +49,11 @@ overflow-checks = true # <- # cargo build/run --release [profile.release] -codegen-units = 1 +codegen-units = 16 debug = 2 debug-assertions = false # <- incremental = false -#lto = 'fat' -#opt-level = 3 # <- +opt-level = 3 # <- overflow-checks = false # <- # cargo test --release diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 8f61c3eb2..3a66a1ecd 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -45,7 +45,7 @@ mod shared { }; self.led_states.store(new_value, Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); + core::sync::atomic::fence(Ordering::SeqCst); } /// Get LED state using safe bit operations @@ -54,7 +54,7 @@ mod shared { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; let value = self.led_states.load(Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); + core::sync::atomic::fence(Ordering::SeqCst); (value & (1 << bit)) != 0 } @@ -66,7 +66,7 @@ mod shared { let current = self.counter.load(Ordering::SeqCst); let new_value = current.wrapping_add(1); self.counter.store(new_value, Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); + core::sync::atomic::fence(Ordering::SeqCst); new_value } @@ -74,7 +74,7 @@ mod shared { #[inline(never)] pub fn get_counter(&self) -> u32 { let value = self.counter.load(Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); + core::sync::atomic::fence(Ordering::SeqCst); value } } diff --git a/examples/stm32h755cm7/Cargo.toml b/examples/stm32h755cm7/Cargo.toml index 06a3b06af..2e34f0928 100644 --- a/examples/stm32h755cm7/Cargo.toml +++ b/examples/stm32h755cm7/Cargo.toml @@ -47,11 +47,10 @@ overflow-checks = true # <- # cargo build/run --release [profile.release] -codegen-units = 1 +codegen-units = 16 debug = 2 debug-assertions = false # <- incremental = false -lto = 'fat' opt-level = 3 # <- overflow-checks = false # <- diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index f01d6a6b7..f1fbd29bc 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -4,7 +4,7 @@ use core::mem::MaybeUninit; use cortex_m::asm; -use cortex_m::peripheral::{MPU, SCB}; +use cortex_m::peripheral::MPU; use defmt::*; use embassy_executor::Spawner; use embassy_stm32::{Config, SharedData}; @@ -102,7 +102,7 @@ mod shared { static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); // Function to configure MPU with your provided settings -fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) { +fn configure_mpu_non_cacheable(mpu: &mut MPU) { // Ensure all operations complete before reconfiguring MPU/caches asm::dmb(); unsafe { @@ -147,11 +147,19 @@ async fn main(_spawner: Spawner) -> ! { // Configure MPU to make SRAM4 non-cacheable { let mut cp = cortex_m::Peripherals::take().unwrap(); - let mpu = &mut cp.MPU; let scb = &mut cp.SCB; - // Configure MPU without disabling caches - configure_mpu_non_cacheable(mpu, scb); + scb.disable_icache(); + scb.disable_dcache(&mut cp.CPUID); + + // 2. MPU setup + configure_mpu_non_cacheable(&mut cp.MPU); + + // 3. re-enable caches + scb.enable_icache(); + scb.enable_dcache(&mut cp.CPUID); + asm::dsb(); + asm::isb(); } // Configure the clocks From f28934cb46bd18cf362b988471266e1b7bb9927e Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 10:40:35 +0200 Subject: [PATCH 08/22] Rewrite documentation and generally improve it --- examples/stm32h755cm4/src/bin/intercore.rs | 53 +++++++++------ examples/stm32h755cm7/src/bin/intercore.rs | 79 +++++++++++----------- 2 files changed, 71 insertions(+), 61 deletions(-) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 3a66a1ecd..715df28d6 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -1,18 +1,32 @@ #![no_std] #![no_main] -// IMPORTANT: This must match EXACTLY the definition in CM7! +//! STM32H7 Secondary Core (CM4) Intercore Communication Example +//! +//! This example demonstrates reliable communication between the Cortex-M7 and +//! Cortex-M4 cores. This secondary core monitors shared memory for LED state +//! changes and updates the physical LEDs accordingly. +//! +//! The CM4 core handles: +//! - Responding to state changes from CM7 +//! - Controlling the physical green and yellow LEDs +//! - Providing visual feedback via a heartbeat on the red LED +//! +//! Usage: +//! 1. Flash this CM4 (secondary) core binary first +//! 2. Then flash the CM7 (primary) core binary +//! 3. The red LED should blink continuously as a heartbeat +//! 4. Green and yellow LEDs should toggle according to CM7 core signals + +/// Module providing shared memory constructs for intercore communication mod shared { use core::sync::atomic::{AtomicU32, Ordering}; - /// Shared LED state between CM7 and CM4 cores + /// State shared between CM7 and CM4 cores for LED control #[repr(C, align(4))] pub struct SharedLedState { - // Magic number for validation pub magic: AtomicU32, - // Counter for synchronization testing pub counter: AtomicU32, - // LED states packed into a single atomic pub led_states: AtomicU32, } @@ -23,19 +37,17 @@ mod shared { impl SharedLedState { pub const fn new() -> Self { Self { - magic: AtomicU32::new(0xDEADBEEF), // Magic number + magic: AtomicU32::new(0xDEADBEEF), counter: AtomicU32::new(0), led_states: AtomicU32::new(0), } } - /// Set LED state using safe bit operations + /// Set LED state by manipulating the appropriate bit in the led_states field #[inline(never)] #[allow(dead_code)] pub fn set_led(&self, is_green: bool, state: bool) { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; - - // Use bit operations to avoid complex atomic operations let current = self.led_states.load(Ordering::SeqCst); let new_value = if state { @@ -48,7 +60,7 @@ mod shared { core::sync::atomic::fence(Ordering::SeqCst); } - /// Get LED state using safe bit operations + /// Get current LED state #[inline(never)] pub fn get_led(&self, is_green: bool) -> bool { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; @@ -59,7 +71,7 @@ mod shared { (value & (1 << bit)) != 0 } - /// Increment counter safely + /// Increment counter and return new value #[inline(never)] #[allow(dead_code)] pub fn increment_counter(&self) -> u32 { @@ -70,7 +82,7 @@ mod shared { new_value } - /// Get counter without incrementing + /// Get current counter value #[inline(never)] pub fn get_counter(&self) -> u32 { let value = self.counter.load(Ordering::SeqCst); @@ -84,19 +96,18 @@ mod shared { } use core::mem::MaybeUninit; - use defmt::*; use embassy_executor::Spawner; use embassy_stm32::gpio::{Level, Output, Speed}; use embassy_stm32::SharedData; use embassy_time::Timer; -// Use our shared state from the module use shared::SHARED_LED_STATE; use {defmt_rtt as _, panic_probe as _}; #[link_section = ".ram_d3"] static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); +/// Task that continuously blinks the red LED as a heartbeat indicator #[embassy_executor::task] async fn blink_heartbeat(mut led: Output<'static>) { loop { @@ -112,11 +123,11 @@ async fn main(spawner: Spawner) -> ! { let p = embassy_stm32::init_secondary(&SHARED_DATA); info!("CM4 core initialized!"); - // Read the magic value to ensure shared memory is accessible + // Verify shared memory is accessible let magic = SHARED_LED_STATE.magic.load(core::sync::atomic::Ordering::SeqCst); info!("CM4: Magic value = 0x{:X}", magic); - // Initialize LEDs + // Set up LEDs let mut green_led = Output::new(p.PB0, Level::Low, Speed::Low); // LD1 let mut yellow_led = Output::new(p.PE1, Level::Low, Speed::Low); // LD2 let red_led = Output::new(p.PB14, Level::Low, Speed::Low); // LD3 (heartbeat) @@ -124,31 +135,30 @@ async fn main(spawner: Spawner) -> ! { // Start heartbeat task unwrap!(spawner.spawn(blink_heartbeat(red_led))); - // Previous values for detecting changes + // Track previous values to detect changes let mut prev_green = false; let mut prev_yellow = false; let mut prev_counter = 0; info!("CM4: Starting main loop"); loop { - // Read values from shared memory + // Read current values from shared memory let green_state = SHARED_LED_STATE.get_led(true); let yellow_state = SHARED_LED_STATE.get_led(false); let counter = SHARED_LED_STATE.get_counter(); - // Check for state changes + // Detect changes let green_changed = green_state != prev_green; let yellow_changed = yellow_state != prev_yellow; let counter_changed = counter != prev_counter; - // If any state changed, log it and update LEDs + // Update LEDs and logs when values change if green_changed || yellow_changed || counter_changed { if counter_changed { info!("CM4: Counter = {}", counter); prev_counter = counter; } - // Update LED states if green_changed { if green_state { green_led.set_high(); @@ -172,7 +182,6 @@ async fn main(spawner: Spawner) -> ! { } } - // Poll at a reasonable rate Timer::after_millis(10).await; } } diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index f1fbd29bc..530e782ab 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -1,6 +1,23 @@ #![no_std] #![no_main] +//! STM32H7 Primary Core (CM7) Intercore Communication Example +//! +//! This example demonstrates reliable communication between the Cortex-M7 and +//! Cortex-M4 cores using a shared memory region configured as non-cacheable +//! via MPU settings. +//! +//! The CM7 core handles: +//! - MPU configuration to make shared memory non-cacheable +//! - Clock initialization +//! - Toggling LED states in shared memory +//! +//! Usage: +//! 1. Flash the CM4 (secondary) core binary first +//! 2. Then flash this CM7 (primary) core binary +//! 3. The system will start with CM7 toggling LED states and CM4 responding by +//! physically toggling the LEDs + use core::mem::MaybeUninit; use cortex_m::asm; @@ -12,17 +29,15 @@ use embassy_time::Timer; use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; use {defmt_rtt as _, panic_probe as _}; +/// Module providing shared memory constructs for intercore communication mod shared { use core::sync::atomic::{AtomicU32, Ordering}; - /// Shared LED state between CM7 and CM4 cores + /// State shared between CM7 and CM4 cores for LED control #[repr(C, align(4))] pub struct SharedLedState { - // Magic number for validation pub magic: AtomicU32, - // Counter for synchronization testing pub counter: AtomicU32, - // LED states packed into a single atomic pub led_states: AtomicU32, } @@ -33,18 +48,16 @@ mod shared { impl SharedLedState { pub const fn new() -> Self { Self { - magic: AtomicU32::new(0xDEADBEEF), // Magic number + magic: AtomicU32::new(0xDEADBEEF), counter: AtomicU32::new(0), led_states: AtomicU32::new(0), } } - /// Set LED state using safe bit operations + /// Set LED state by manipulating the appropriate bit in the led_states field #[inline(never)] pub fn set_led(&self, is_green: bool, state: bool) { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; - - // Use bit operations to avoid complex atomic operations let current = self.led_states.load(Ordering::SeqCst); let new_value = if state { @@ -57,7 +70,7 @@ mod shared { core::sync::atomic::compiler_fence(Ordering::SeqCst); } - /// Get LED state using safe bit operations + /// Get current LED state #[inline(never)] #[allow(dead_code)] pub fn get_led(&self, is_green: bool) -> bool { @@ -69,7 +82,7 @@ mod shared { (value & (1 << bit)) != 0 } - /// Increment counter safely + /// Increment counter and return new value #[inline(never)] pub fn increment_counter(&self) -> u32 { let current = self.counter.load(Ordering::SeqCst); @@ -79,7 +92,7 @@ mod shared { new_value } - /// Get counter without incrementing + /// Get current counter value #[inline(never)] #[allow(dead_code)] pub fn get_counter(&self) -> u32 { @@ -92,37 +105,29 @@ mod shared { #[link_section = ".ram_d3"] pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); - // SRAM4 memory region constants for MPU configuration + // Memory region constants for MPU configuration pub const SRAM4_BASE_ADDRESS: u32 = 0x38000000; pub const SRAM4_SIZE_LOG2: u32 = 15; // 64KB = 2^(15+1) - pub const SRAM4_REGION_NUMBER: u8 = 0; // MPU region number to use + pub const SRAM4_REGION_NUMBER: u8 = 0; } #[link_section = ".ram_d3"] static SHARED_DATA: MaybeUninit = MaybeUninit::uninit(); -// Function to configure MPU with your provided settings +/// Configure MPU to make SRAM4 region non-cacheable fn configure_mpu_non_cacheable(mpu: &mut MPU) { - // Ensure all operations complete before reconfiguring MPU/caches asm::dmb(); unsafe { // Disable MPU mpu.ctrl.write(0); // Configure SRAM4 as non-cacheable - // Set region number (0) mpu.rnr.write(SRAM4_REGION_NUMBER as u32); - // Set base address (SRAM4 = 0x38000000) with VALID bit and region number - mpu.rbar.write( - SRAM4_BASE_ADDRESS | (1 << 4), // Region number = 0 (explicit in RBAR) - ); + // Set base address with region number + mpu.rbar.write(SRAM4_BASE_ADDRESS | (1 << 4)); - // Configure region attributes: - // SIZE=15 (64KB = 2^(15+1)) - // ENABLE=1 - // AP=3 (Full access) - // TEX=1, S=1, C=0, B=0 (Normal memory, Non-cacheable, Shareable) + // Configure region attributes let rasr_value: u32 = (SRAM4_SIZE_LOG2 << 1) | // SIZE=15 (64KB) (1 << 0) | // ENABLE=1 (3 << 24) | // AP=3 (Full access) @@ -135,7 +140,6 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU) { mpu.ctrl.write(1 | (1 << 2)); // MPU_ENABLE | PRIVDEFENA } - // Ensure changes are committed asm::dsb(); asm::isb(); @@ -144,25 +148,26 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU) { #[embassy_executor::main] async fn main(_spawner: Spawner) -> ! { - // Configure MPU to make SRAM4 non-cacheable + // Set up MPU and cache configuration { let mut cp = cortex_m::Peripherals::take().unwrap(); let scb = &mut cp.SCB; + // First disable caches scb.disable_icache(); scb.disable_dcache(&mut cp.CPUID); - // 2. MPU setup + // Configure MPU configure_mpu_non_cacheable(&mut cp.MPU); - // 3. re-enable caches + // Re-enable caches scb.enable_icache(); scb.enable_dcache(&mut cp.CPUID); asm::dsb(); asm::isb(); } - // Configure the clocks + // Configure the clock system let mut config = Config::default(); { use embassy_stm32::rcc::*; @@ -191,42 +196,38 @@ async fn main(_spawner: Spawner) -> ! { let _p = embassy_stm32::init_primary(config, &SHARED_DATA); info!("CM7 core initialized with non-cacheable SRAM4!"); - // Read the magic value to ensure shared memory is accessible + // Verify shared memory is accessible let magic = SHARED_LED_STATE.magic.load(core::sync::atomic::Ordering::SeqCst); info!("CM7: Magic value = 0x{:X}", magic); - // Initialize shared memory state + // Initialize LED states SHARED_LED_STATE.set_led(true, false); // Green LED off SHARED_LED_STATE.set_led(false, false); // Yellow LED off - // Main loop - update shared memory values + // Main loop - periodically toggle LED states let mut green_state = false; let mut yellow_state = false; let mut loop_count = 0; info!("CM7: Starting main loop"); loop { - // Update loop counter loop_count += 1; - - // Update shared counter let counter = SHARED_LED_STATE.increment_counter(); - // Every second, toggle green LED state + // Toggle green LED every second if loop_count % 10 == 0 { green_state = !green_state; SHARED_LED_STATE.set_led(true, green_state); info!("CM7: Counter = {}, Set green LED to {}", counter, green_state); } - // Every 3 seconds, toggle yellow LED state + // Toggle yellow LED every 3 seconds if loop_count % 30 == 0 { yellow_state = !yellow_state; SHARED_LED_STATE.set_led(false, yellow_state); info!("CM7: Counter = {}, Set yellow LED to {}", counter, yellow_state); } - // Wait 100ms before next cycle Timer::after_millis(100).await; } } From ddcf13b5260c909d95b72d61131bb1c7e96d2e66 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Sat, 10 May 2025 10:42:52 +0200 Subject: [PATCH 09/22] nightly rustfmt really do be my bane rn --- examples/stm32h755cm4/src/bin/intercore.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 715df28d6..6ebf61cd4 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -96,6 +96,7 @@ mod shared { } use core::mem::MaybeUninit; + use defmt::*; use embassy_executor::Spawner; use embassy_stm32::gpio::{Level, Output, Speed}; From d5c9d1af26e7bd0ebefafba6ae28b0bd660aa924 Mon Sep 17 00:00:00 2001 From: ragarnoy Date: Wed, 21 May 2025 12:27:56 +0200 Subject: [PATCH 10/22] Remove unnecessary atomic fences from intercore examples --- examples/stm32h755cm4/src/bin/intercore.rs | 6 ------ examples/stm32h755cm7/src/bin/intercore.rs | 5 ----- 2 files changed, 11 deletions(-) diff --git a/examples/stm32h755cm4/src/bin/intercore.rs b/examples/stm32h755cm4/src/bin/intercore.rs index 6ebf61cd4..d5e3e7648 100644 --- a/examples/stm32h755cm4/src/bin/intercore.rs +++ b/examples/stm32h755cm4/src/bin/intercore.rs @@ -55,9 +55,7 @@ mod shared { } else { current & !(1 << bit) // Clear bit }; - self.led_states.store(new_value, Ordering::SeqCst); - core::sync::atomic::fence(Ordering::SeqCst); } /// Get current LED state @@ -66,8 +64,6 @@ mod shared { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; let value = self.led_states.load(Ordering::SeqCst); - core::sync::atomic::fence(Ordering::SeqCst); - (value & (1 << bit)) != 0 } @@ -78,7 +74,6 @@ mod shared { let current = self.counter.load(Ordering::SeqCst); let new_value = current.wrapping_add(1); self.counter.store(new_value, Ordering::SeqCst); - core::sync::atomic::fence(Ordering::SeqCst); new_value } @@ -86,7 +81,6 @@ mod shared { #[inline(never)] pub fn get_counter(&self) -> u32 { let value = self.counter.load(Ordering::SeqCst); - core::sync::atomic::fence(Ordering::SeqCst); value } } diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs index 530e782ab..a4e1b5ff4 100644 --- a/examples/stm32h755cm7/src/bin/intercore.rs +++ b/examples/stm32h755cm7/src/bin/intercore.rs @@ -67,7 +67,6 @@ mod shared { }; self.led_states.store(new_value, Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); } /// Get current LED state @@ -77,8 +76,6 @@ mod shared { let bit = if is_green { GREEN_LED_BIT } else { YELLOW_LED_BIT }; let value = self.led_states.load(Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); - (value & (1 << bit)) != 0 } @@ -88,7 +85,6 @@ mod shared { let current = self.counter.load(Ordering::SeqCst); let new_value = current.wrapping_add(1); self.counter.store(new_value, Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); new_value } @@ -97,7 +93,6 @@ mod shared { #[allow(dead_code)] pub fn get_counter(&self) -> u32 { let value = self.counter.load(Ordering::SeqCst); - core::sync::atomic::compiler_fence(Ordering::SeqCst); value } } From 94080b38a5b8dec05210b5b1377d595b2640488c Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 20:29:06 +0200 Subject: [PATCH 11/22] Added Option to enable HW Oversampling in STM32 V3 ADCs. Copied from adc/v4.rs and adjusted to reflect 2 to 256x oversampling + adjusted bit shifting operations --- embassy-stm32/src/adc/v3.rs | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 313244e19..f561f817c 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -93,6 +93,18 @@ cfg_if! { } } +/// Number of samples used for averaging. +pub enum Averaging { + Disabled, + Samples2, + Samples4, + Samples8, + Samples16, + Samples32, + Samples64, + Samples128, + Samples256, +} impl<'d, T: Instance> Adc<'d, T> { pub fn new(adc: Peri<'d, T>) -> Self { rcc::enable_and_reset::(); @@ -223,6 +235,25 @@ impl<'d, T: Instance> Adc<'d, T> { T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into())); } + pub fn set_averaging(&mut self, averaging: Averaging) { + let (enable, samples, right_shift) = match averaging { + Averaging::Disabled => (false, 0, 0), + Averaging::Samples2 => (true, 0, 1), + Averaging::Samples4 => (true, 1, 2), + Averaging::Samples8 => (true, 2, 3), + Averaging::Samples16 => (true, 3, 4), + Averaging::Samples32 => (true, 4, 5), + Averaging::Samples64 => (true, 5, 6), + Averaging::Samples128 => (true, 6, 7), + Averaging::Samples256 => (true, 7, 8), + }; + + T::regs().cfgr2().modify(|reg| { + reg.set_rovse(enable); + reg.set_ovsr(samples); + reg.set_ovss(right_shift); + }) + } /* /// Convert a raw sample from the `Temperature` to deg C pub fn to_degrees_centigrade(sample: u16) -> f32 { From a912a3798d5321d099765df4e1af16158699c8d5 Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 21:04:41 +0200 Subject: [PATCH 12/22] Fixed variations in register access for different families --- embassy-stm32/src/adc/v3.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index f561f817c..c032113d5 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -247,9 +247,14 @@ impl<'d, T: Instance> Adc<'d, T> { Averaging::Samples128 => (true, 6, 7), Averaging::Samples256 => (true, 7, 8), }; - T::regs().cfgr2().modify(|reg| { + #[cfg(not(adc_g0))] reg.set_rovse(enable); + #[cfg(adc_g0)] + reg.set_ovse(enable); + #[cfg(any(adc_h5, adc_h7rs))] + reg.set_ovsr(samples.into()); + #[cfg(not(any(adc_h5, adc_h7rs)))] reg.set_ovsr(samples); reg.set_ovss(right_shift); }) From adb728009ceba095d2190038ff698aaee08907a9 Mon Sep 17 00:00:00 2001 From: Benjamin Date: Tue, 3 Jun 2025 21:10:19 +0200 Subject: [PATCH 13/22] adjusted for u0 as well --- embassy-stm32/src/adc/v3.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index c032113d5..7b5df80b8 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -248,9 +248,9 @@ impl<'d, T: Instance> Adc<'d, T> { Averaging::Samples256 => (true, 7, 8), }; T::regs().cfgr2().modify(|reg| { - #[cfg(not(adc_g0))] + #[cfg(not(any(adc_g0, adc_u0)))] reg.set_rovse(enable); - #[cfg(adc_g0)] + #[cfg(any(adc_g0, adc_u0))] reg.set_ovse(enable); #[cfg(any(adc_h5, adc_h7rs))] reg.set_ovsr(samples.into()); From e4cb80be7cc74203259dbb82092f83a154bcd8a2 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Thu, 24 Jul 2025 15:12:12 -0400 Subject: [PATCH 14/22] add pll divs/t for h7rs --- embassy-stm32/src/rcc/h.rs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 383f48874..354824e26 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -8,6 +8,9 @@ use crate::pac::rcc::vals::{Pllrge, Pllvcosel, Timpre}; use crate::pac::{FLASH, PWR, RCC}; use crate::time::Hertz; +#[cfg(stm32h7rs)] +use stm32_metapac::rcc::vals::Plldivst; + /// HSI speed pub const HSI_FREQ: Hertz = Hertz(64_000_000); @@ -78,6 +81,12 @@ pub struct Pll { pub divq: Option, /// PLL R division factor. If None, PLL R output is disabled. pub divr: Option, + #[cfg(stm32h7rs)] + /// PLL S division factor. If None, PLL S output is disabled. + pub divs: Option, + #[cfg(stm32h7rs)] + /// PLL T division factor. If None, PLL T output is disabled. + pub divt: Option, } fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz { From 24b2794931e73325ad969d83453d0cf872ac4775 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Thu, 24 Jul 2025 21:09:24 -0400 Subject: [PATCH 15/22] add plls/t to stm32h7rs examples --- examples/stm32h7rs/src/bin/blinky.rs | 2 ++ examples/stm32h7rs/src/bin/eth.rs | 2 ++ examples/stm32h7rs/src/bin/usb_serial.rs | 2 ++ examples/stm32h7rs/src/bin/xspi_memory_mapped.rs | 2 ++ 4 files changed, 8 insertions(+) diff --git a/examples/stm32h7rs/src/bin/blinky.rs b/examples/stm32h7rs/src/bin/blinky.rs index 137c585b7..5fd50fb15 100644 --- a/examples/stm32h7rs/src/bin/blinky.rs +++ b/examples/stm32h7rs/src/bin/blinky.rs @@ -25,6 +25,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz diff --git a/examples/stm32h7rs/src/bin/eth.rs b/examples/stm32h7rs/src/bin/eth.rs index 6d246bb09..d8002e9ba 100644 --- a/examples/stm32h7rs/src/bin/eth.rs +++ b/examples/stm32h7rs/src/bin/eth.rs @@ -41,6 +41,8 @@ async fn main(spawner: Spawner) -> ! { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz diff --git a/examples/stm32h7rs/src/bin/usb_serial.rs b/examples/stm32h7rs/src/bin/usb_serial.rs index 56a9884af..23abc3e2f 100644 --- a/examples/stm32h7rs/src/bin/usb_serial.rs +++ b/examples/stm32h7rs/src/bin/usb_serial.rs @@ -40,6 +40,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV1), //600 MHz divq: Some(PllDiv::DIV2), // 300 MHz divr: Some(PllDiv::DIV2), // 300 MHz + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 MHz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 MHz diff --git a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs index 59045ca2e..4c1b450b4 100644 --- a/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs +++ b/examples/stm32h7rs/src/bin/xspi_memory_mapped.rs @@ -36,6 +36,8 @@ async fn main(_spawner: Spawner) { divp: Some(PllDiv::DIV2), divq: None, divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz From 3a30458b253083087b43b85c43cc8eaf10870414 Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 12:10:17 -0400 Subject: [PATCH 16/22] address rustfmt ci check --- embassy-stm32/src/rcc/h.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index 354824e26..c31b1bbd1 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -1,5 +1,8 @@ use core::ops::RangeInclusive; +#[cfg(stm32h7rs)] +use stm32_metapac::rcc::vals::Plldivst; + use crate::pac; pub use crate::pac::rcc::vals::{ Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk, @@ -8,9 +11,6 @@ use crate::pac::rcc::vals::{Pllrge, Pllvcosel, Timpre}; use crate::pac::{FLASH, PWR, RCC}; use crate::time::Hertz; -#[cfg(stm32h7rs)] -use stm32_metapac::rcc::vals::Plldivst; - /// HSI speed pub const HSI_FREQ: Hertz = Hertz(64_000_000); From c37fb51cfe25511b2222e92e37b80933079ed3fc Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 12:24:54 -0400 Subject: [PATCH 17/22] address ci test failure --- tests/stm32/src/common.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index a4d8048ce..cb63b3374 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs @@ -681,6 +681,8 @@ pub fn config() -> Config { divp: Some(PllDiv::DIV2), // 600Mhz divq: Some(PllDiv::DIV25), // 48Mhz divr: None, + divs: None, + divt: None, }); config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz From 777e0c71c99fde779cf91c364849ac6906cb3d97 Mon Sep 17 00:00:00 2001 From: emkanea-dev Date: Fri, 25 Jul 2025 20:53:04 +0200 Subject: [PATCH 18/22] fixed build after rebase --- embassy-stm32/src/adc/v3.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 805dae564..a2e42fe52 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs @@ -257,8 +257,8 @@ impl<'d, T: Instance> Adc<'d, T> { #[cfg(any(adc_h5, adc_h7rs))] reg.set_ovsr(samples.into()); #[cfg(not(any(adc_h5, adc_h7rs)))] - reg.set_ovsr(samples); - reg.set_ovss(right_shift); + reg.set_ovsr(samples.into()); + reg.set_ovss(right_shift.into()); }) } /* From a5a9c02543fbe978c68a707654029552f6b7b00a Mon Sep 17 00:00:00 2001 From: Rick Rogers Date: Fri, 25 Jul 2025 15:03:37 -0400 Subject: [PATCH 19/22] include proper pll divs/divt initialization --- embassy-stm32/build.rs | 2 +- embassy-stm32/src/rcc/h.rs | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 73860c64a..753f94fa6 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -1599,7 +1599,7 @@ fn main() { for e in rcc_registers.ir.enums { fn is_rcc_name(e: &str) -> bool { match e { - "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true, + "Pllp" | "Pllq" | "Pllr" | "Plldivst" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true, "Timpre" | "Pllrclkpre" => false, e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true, _ => false, diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs index c31b1bbd1..837210b6a 100644 --- a/embassy-stm32/src/rcc/h.rs +++ b/embassy-stm32/src/rcc/h.rs @@ -758,6 +758,12 @@ struct PllOutput { q: Option, #[allow(dead_code)] r: Option, + #[cfg(stm32h7rs)] + #[allow(dead_code)] + s: Option, + #[cfg(stm32h7rs)] + #[allow(dead_code)] + t: Option, } fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { @@ -776,6 +782,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { p: None, q: None, r: None, + #[cfg(stm32h7rs)] + s: None, + #[cfg(stm32h7rs)] + t: None, }; }; @@ -823,6 +833,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { }); let q = config.divq.map(|div| vco_clk / div); let r = config.divr.map(|div| vco_clk / div); + #[cfg(stm32h7rs)] + let s = config.divs.map(|div| vco_clk / div); + #[cfg(stm32h7rs)] + let t = config.divt.map(|div| vco_clk / div); #[cfg(stm32h5)] RCC.pllcfgr(num).write(|w| { @@ -849,6 +863,10 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { w.set_divpen(num, p.is_some()); w.set_divqen(num, q.is_some()); w.set_divren(num, r.is_some()); + #[cfg(stm32h7rs)] + w.set_divsen(num, s.is_some()); + #[cfg(stm32h7rs)] + w.set_divten(num, t.is_some()); }); } @@ -859,10 +877,24 @@ fn init_pll(num: usize, config: Option, input: &PllInput) -> PllOutput { w.set_pllr(config.divr.unwrap_or(PllDiv::DIV2)); }); + #[cfg(stm32h7rs)] + RCC.plldivr2(num).write(|w| { + w.set_plls(config.divs.unwrap_or(Plldivst::DIV2)); + w.set_pllt(config.divt.unwrap_or(Plldivst::DIV2)); + }); + RCC.cr().modify(|w| w.set_pllon(num, true)); while !RCC.cr().read().pllrdy(num) {} - PllOutput { p, q, r } + PllOutput { + p, + q, + r, + #[cfg(stm32h7rs)] + s, + #[cfg(stm32h7rs)] + t, + } } fn flash_setup(clk: Hertz, vos: VoltageScale) { From 1ccf6ef6c0ee5fb141631491c1c6629db218bbc1 Mon Sep 17 00:00:00 2001 From: korbin Date: Sat, 26 Jul 2025 17:41:18 -0600 Subject: [PATCH 20/22] add embassy-net defmt derives for config structs --- embassy-net/src/lib.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/embassy-net/src/lib.rs b/embassy-net/src/lib.rs index 693a39ed5..2b1888170 100644 --- a/embassy-net/src/lib.rs +++ b/embassy-net/src/lib.rs @@ -106,6 +106,7 @@ impl StackResources { /// Static IP address configuration. #[cfg(feature = "proto-ipv4")] #[derive(Debug, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct StaticConfigV4 { /// IP address and subnet mask. pub address: Ipv4Cidr, @@ -118,6 +119,7 @@ pub struct StaticConfigV4 { /// Static IPv6 address configuration #[cfg(feature = "proto-ipv6")] #[derive(Debug, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct StaticConfigV6 { /// IP address and subnet mask. pub address: Ipv6Cidr, @@ -130,6 +132,7 @@ pub struct StaticConfigV6 { /// DHCP configuration. #[cfg(feature = "dhcpv4")] #[derive(Debug, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[non_exhaustive] pub struct DhcpConfig { /// Maximum lease duration. @@ -169,6 +172,7 @@ impl Default for DhcpConfig { /// Network stack configuration. #[derive(Debug, Clone, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[non_exhaustive] pub struct Config { /// IPv4 configuration @@ -220,6 +224,7 @@ impl Config { /// Network stack IPv4 configuration. #[cfg(feature = "proto-ipv4")] #[derive(Debug, Clone, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ConfigV4 { /// Do not configure IPv4. #[default] @@ -234,6 +239,7 @@ pub enum ConfigV4 { /// Network stack IPv6 configuration. #[cfg(feature = "proto-ipv6")] #[derive(Debug, Clone, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum ConfigV6 { /// Do not configure IPv6. #[default] From 1379e15d6385e6a4613dc4ddd543ad9f42805bd2 Mon Sep 17 00:00:00 2001 From: korbin Date: Sat, 26 Jul 2025 17:45:27 -0600 Subject: [PATCH 21/22] add embassy-time/defmt config flag passthrough --- embassy-net/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-net/Cargo.toml b/embassy-net/Cargo.toml index 526c8a4b3..a2665c770 100644 --- a/embassy-net/Cargo.toml +++ b/embassy-net/Cargo.toml @@ -24,7 +24,7 @@ features = ["defmt", "tcp", "udp", "raw", "dns", "icmp", "dhcpv4", "proto-ipv6", [features] ## Enable defmt -defmt = ["dep:defmt", "smoltcp/defmt", "embassy-net-driver/defmt", "heapless/defmt-03", "defmt?/ip_in_core"] +defmt = ["dep:defmt", "smoltcp/defmt", "embassy-net-driver/defmt", "embassy-time/defmt", "heapless/defmt-03", "defmt?/ip_in_core"] ## Trace all raw received and transmitted packets using defmt or log. packet-trace = [] From 77a8bc27e9c34e363f321132ebb9e8d8ff684a9f Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sun, 27 Jul 2025 02:03:43 +0200 Subject: [PATCH 22/22] ci: lower book, doc job prio --- .github/ci/book.sh | 2 +- .github/ci/doc.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/ci/book.sh b/.github/ci/book.sh index 2466f53f5..c91d10d16 100755 --- a/.github/ci/book.sh +++ b/.github/ci/book.sh @@ -1,6 +1,6 @@ #!/bin/bash ## on push branch=main -## priority -9 +## priority -100 ## dedup dequeue set -euxo pipefail diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh index 9162b37ae..26971afdc 100755 --- a/.github/ci/doc.sh +++ b/.github/ci/doc.sh @@ -1,6 +1,6 @@ #!/bin/bash ## on push branch=main -## priority -10 +## priority -100 ## dedup dequeue set -euxo pipefail