remove Hz from log

This commit is contained in:
Steven Friedman 2025-04-08 09:36:35 -04:00
parent 3cb178e78e
commit bbf2a641dd
No known key found for this signature in database
GPG Key ID: 58A79D6C92E57FA7
6 changed files with 7 additions and 7 deletions

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@ -163,7 +163,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
let frequency = Hertz(T::frequency().0 / prescaler.divisor());
debug!("ADC frequency set to {} Hz", frequency);
debug!("ADC frequency set to {}", frequency);
if frequency > MAX_ADC_CLK_FREQ {
panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );

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@ -143,7 +143,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
let frequency = Hertz(T::frequency().0 / prescaler.divisor());
info!("ADC frequency set to {} Hz", frequency);
info!("ADC frequency set to {}", frequency);
if frequency > MAX_ADC_CLK_FREQ {
panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );

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@ -193,7 +193,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
let frequency = Hertz(T::frequency().0 / prescaler.divisor());
info!("ADC4 frequency set to {} Hz", frequency);
info!("ADC4 frequency set to {}", frequency);
if frequency > MAX_ADC_CLK_FREQ {
panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );

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@ -166,7 +166,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
let frequency = Hertz(T::frequency().0 / prescaler.divisor());
info!("ADC frequency set to {} Hz", frequency);
info!("ADC frequency set to {}", frequency);
if frequency > MAX_ADC_CLK_FREQ {
panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );

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@ -575,7 +575,7 @@ pub(crate) unsafe fn init(config: Config) {
Hertz(24_000_000) => Usbrefcksel::MHZ24,
Hertz(26_000_000) => Usbrefcksel::MHZ26,
Hertz(32_000_000) => Usbrefcksel::MHZ32,
_ => panic!("cannot select USBPHYC reference clock with source frequency of {} Hz, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
_ => panic!("cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
},
None => Usbrefcksel::MHZ24,
};
@ -792,7 +792,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
Pllvcosel::WIDE_VCO
} else {
panic!("pll vco_clk out of range: {} hz", vco_clk)
panic!("pll vco_clk out of range: {}", vco_clk)
};
let p = config.divp.map(|div| {

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@ -315,7 +315,7 @@ pub(crate) unsafe fn init(config: Config) {
Hertz(24_000_000) => Usbrefcksel::MHZ24,
Hertz(26_000_000) => Usbrefcksel::MHZ26,
Hertz(32_000_000) => Usbrefcksel::MHZ32,
_ => panic!("cannot select OTG_HS reference clock with source frequency of {} Hz, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
_ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
},
None => Usbrefcksel::MHZ24,
};