From bea1f34440eff7842c0c04e8b7381cdb429f5005 Mon Sep 17 00:00:00 2001
From: Daniel Trnka <daniel.trnka@gmail.com>
Date: Wed, 21 Aug 2024 13:15:48 +0200
Subject: [PATCH] stm32/usart: sending break character

---
 embassy-stm32/src/usart/mod.rs | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 89d92dda2..cbd4ac3bc 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -520,6 +520,21 @@ impl<'d, M: Mode> UartTx<'d, M> {
     pub fn blocking_flush(&mut self) -> Result<(), Error> {
         blocking_flush(self.info)
     }
+
+    /// Send break character
+    pub fn send_break(&self) {
+        // Busy wait until previous break has been sent
+        #[cfg(any(usart_v1, usart_v2))]
+        while self.info.regs.cr1().read().sbk() {}
+        #[cfg(any(usart_v3, usart_v4))]
+        while self.info.regs.isr().read().sbkf() {}
+
+        // Send break right after completing the current character transmission
+        #[cfg(any(usart_v1, usart_v2))]
+        self.info.regs.cr1().modify(|w| w.set_sbk(true));
+        #[cfg(any(usart_v3, usart_v4))]
+        self.info.regs.rqr().write(|w| w.set_sbkrq(true));
+    }
 }
 
 fn blocking_flush(info: &Info) -> Result<(), Error> {
@@ -1365,6 +1380,11 @@ impl<'d, M: Mode> Uart<'d, M> {
     pub fn split(self) -> (UartTx<'d, M>, UartRx<'d, M>) {
         (self.tx, self.rx)
     }
+
+    /// Send break character
+    pub fn send_break(&self) {
+        self.tx.send_break();
+    }
 }
 
 fn reconfigure(info: &Info, kernel_clock: Hertz, config: &Config) -> Result<(), ConfigError> {