itsscb/embassy
1
0
Fork 0
mirror of https://github.com/embassy-rs/embassy.git synced 2025-10-03 23:24:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

rustfmt

Browse Source
This commit is contained in:
ragarnoy 2025-05-10 02:22:48 +02:00
parent 90404a8e52
commit cf60b11066
No known key found for this signature in database
GPG Key ID: 7A8FB9858346157A
2 changed files with 12 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
examples/stm32h755cm7/src/bin/intercore.rs
View File

@ -93,8 +93,8 @@ use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _}; use {defmt_rtt as _, panic_probe as _};
// Import cortex_m for MPU configuration // Import cortex_m for MPU configuration
use cortex_m::peripheral::{MPU, SCB};
use cortex_m::asm; use cortex_m::asm;
use cortex_m::peripheral::{MPU, SCB};
// Use our shared state from the module // Use our shared state from the module
use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2};
@ -116,8 +116,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
// Set base address (SRAM4 = 0x38000000) with VALID bit and region number // Set base address (SRAM4 = 0x38000000) with VALID bit and region number
mpu.rbar.write( mpu.rbar.write(
SRAM4_BASE_ADDRESS | SRAM4_BASE_ADDRESS | (1 << 4), // Region number = 0 (explicit in RBAR)
(1 << 4) // Region number = 0 (explicit in RBAR)
); );
// Configure region attributes: // Configure region attributes: