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ragarnoy 2025-05-10 02:22:48 +02:00
parent 90404a8e52
commit cf60b11066
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2 changed files with 12 additions and 13 deletions
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5
examples/stm32h755cm7/src/bin/intercore.rs
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@ -93,8 +93,8 @@ use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
// Import cortex_m for MPU configuration
use cortex_m::peripheral::{MPU, SCB};
use cortex_m::asm;
use cortex_m::peripheral::{MPU, SCB};
// Use our shared state from the module
use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2};
@ -116,8 +116,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
// Set base address (SRAM4 = 0x38000000) with VALID bit and region number
mpu.rbar.write(
SRAM4_BASE_ADDRESS |
(1 << 4) // Region number = 0 (explicit in RBAR)
SRAM4_BASE_ADDRESS | (1 << 4), // Region number = 0 (explicit in RBAR)
);
// Configure region attributes: