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fix: build

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elagil 2025-08-25 21:10:59 +02:00 committed by Dario Nieuwenhuis
parent d3718c6d4e
commit e9783ee28e
5 changed files with 35 additions and 92 deletions
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15
embassy-stm32/src/dma/gpdma/linked_list.rs
View File

@ -163,6 +163,21 @@ impl<const ITEM_COUNT: usize> Table<ITEM_COUNT> {
Self { items }
}
/// Create a ping-pong linked-list table.
///
/// This uses two linked-list items, one for each half of the buffer.
pub unsafe fn new_ping_pong<W: Word>(request: Request, peri_addr: *mut W, buffer: &mut [W]) -> Table<2> {
// Buffer halves should be the same length.
let half_len = buffer.len() / 2;
assert_eq!(half_len * 2, buffer.len());
let items = [
LinearItem::new_read(request, peri_addr, &mut buffer[..half_len]),
LinearItem::new_read(request, peri_addr, &mut buffer[half_len..]),
];
Table::new(items)
}
/// Link the table as given by the run mode.
pub fn link(&mut self, run_mode: RunMode) {
if matches!(run_mode, RunMode::Once | RunMode::Circular) {

100
embassy-stm32/src/dma/gpdma/ringbuffered.rs
View File

@ -9,7 +9,7 @@ use core::task::Waker;
use embassy_hal_internal::Peri;
use super::{AnyChannel, TransferOptions, STATE};
use crate::dma::gpdma::linked_list::{LinearItem, RunMode, Table};
use crate::dma::gpdma::linked_list::{RunMode, Table};
use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
use crate::dma::word::Word;
use crate::dma::{Channel, Request};
@ -48,14 +48,14 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
}
/// Ringbuffer for receiving data using GPDMA linked-list mode.
pub struct ReadableRingBuffer<'a, W: Word, const L: usize> {
pub struct ReadableRingBuffer<'a, W: Word> {
channel: Peri<'a, AnyChannel>,
ringbuf: ReadableDmaRingBuffer<'a, W>,
table: Table<L>,
table: Table<2>,
options: TransferOptions,
}
impl<'a, W: Word> ReadableRingBuffer<'a, W, 2> {
impl<'a, W: Word> ReadableRingBuffer<'a, W> {
/// Create a new ring buffer.
///
/// Transfer options are applied to the individual linked list items.
@ -67,7 +67,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W, 2> {
options: TransferOptions,
) -> Self {
let channel: Peri<'a, AnyChannel> = channel.into();
let table = Self::new_ping_pong_table(request, peri_addr, buffer);
let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer);
Self {
channel,
@ -76,42 +76,6 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W, 2> {
options,
}
}
}
impl<'a, W: Word, const L: usize> ReadableRingBuffer<'a, W, L> {
/// Create a new ring buffer with a provided linked-list table.
///
/// Transfer options are applied to the individual linked list items.
pub fn new_with_table(
channel: Peri<'a, impl Channel>,
buffer: &'a mut [W],
options: TransferOptions,
table: Table<L>,
) -> Self {
let channel: Peri<'a, AnyChannel> = channel.into();
Self {
channel,
ringbuf: ReadableDmaRingBuffer::new(buffer),
table,
options,
}
}
/// Create a new simple linked-list table.
///
/// This uses two linked-list items, one for each half of the buffer.
pub unsafe fn new_ping_pong_table(request: Request, peri_addr: *mut W, buffer: &mut [W]) -> Table<2> {
// Buffer halves should be the same length.
let half_len = buffer.len() / 2;
assert_eq!(half_len * 2, buffer.len());
let items = [
LinearItem::new_read(request, peri_addr, &mut buffer[..half_len]),
LinearItem::new_read(request, peri_addr, &mut buffer[half_len..]),
];
Table::new(items)
}
/// Start the ring buffer operation.
pub fn start(&mut self) {
@ -172,7 +136,7 @@ impl<'a, W: Word, const L: usize> ReadableRingBuffer<'a, W, L> {
/// To resume the transfer, call [`request_resume`](Self::request_resume) again.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_suspend(&mut self) {
pub fn request_pause(&mut self) {
self.channel.request_suspend()
}
@ -216,9 +180,9 @@ impl<'a, W: Word, const L: usize> ReadableRingBuffer<'a, W, L> {
}
}
impl<'a, W: Word, const L: usize> Drop for ReadableRingBuffer<'a, W, L> {
impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
fn drop(&mut self) {
self.request_suspend();
self.request_pause();
while self.is_running() {}
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
@ -227,14 +191,14 @@ impl<'a, W: Word, const L: usize> Drop for ReadableRingBuffer<'a, W, L> {
}
/// Ringbuffer for writing data using GPDMA linked-list mode.
pub struct WritableRingBuffer<'a, W: Word, const L: usize> {
pub struct WritableRingBuffer<'a, W: Word> {
channel: Peri<'a, AnyChannel>,
ringbuf: WritableDmaRingBuffer<'a, W>,
table: Table<L>,
table: Table<2>,
options: TransferOptions,
}
impl<'a, W: Word> WritableRingBuffer<'a, W, 2> {
impl<'a, W: Word> WritableRingBuffer<'a, W> {
/// Create a new ring buffer.
///
/// Transfer options are applied to the individual linked list items.
@ -246,7 +210,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W, 2> {
options: TransferOptions,
) -> Self {
let channel: Peri<'a, AnyChannel> = channel.into();
let table = Self::new_ping_pong_table(request, peri_addr, buffer);
let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer);
Self {
channel,
@ -255,42 +219,6 @@ impl<'a, W: Word> WritableRingBuffer<'a, W, 2> {
options,
}
}
}
impl<'a, W: Word, const L: usize> WritableRingBuffer<'a, W, L> {
/// Create a new ring buffer with a provided linked-list table.
///
/// Transfer options are applied to the individual linked list items.
pub fn new_with_table(
channel: Peri<'a, impl Channel>,
buffer: &'a mut [W],
options: TransferOptions,
table: Table<L>,
) -> Self {
let channel: Peri<'a, AnyChannel> = channel.into();
Self {
channel,
ringbuf: WritableDmaRingBuffer::new(buffer),
table,
options,
}
}
/// Create a new simple linked-list table.
///
/// This uses two linked-list items, one for each half of the buffer.
pub unsafe fn new_ping_pong_table(request: Request, peri_addr: *mut W, buffer: &[W]) -> Table<2> {
// Buffer halves should be the same length.
let half_len = buffer.len() / 2;
assert_eq!(half_len * 2, buffer.len());
let items = [
LinearItem::new_write(request, &buffer[..half_len], peri_addr),
LinearItem::new_write(request, &buffer[half_len..], peri_addr),
];
Table::new(items)
}
/// Start the ring buffer operation.
pub fn start(&mut self) {
@ -351,7 +279,7 @@ impl<'a, W: Word, const L: usize> WritableRingBuffer<'a, W, L> {
/// To resume the transfer, call [`request_resume`](Self::request_resume) again.
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_suspend(&mut self) {
pub fn request_pause(&mut self) {
self.channel.request_suspend()
}
@ -395,7 +323,7 @@ impl<'a, W: Word, const L: usize> WritableRingBuffer<'a, W, L> {
}
}
impl<'a, W: Word, const L: usize> Drop for WritableRingBuffer<'a, W, L> {
impl<'a, W: Word> Drop for WritableRingBuffer<'a, W> {
fn drop(&mut self) {
self.request_suspend();
while self.is_running() {}

4
embassy-stm32/src/sai/mod.rs
View File

@ -650,8 +650,8 @@ impl Config {
}
enum RingBuffer<'d, W: word::Word> {
Writable(WritableRingBuffer<'d, W, 2>),
Readable(ReadableRingBuffer<'d, W, 2>),
Writable(WritableRingBuffer<'d, W>),
Readable(ReadableRingBuffer<'d, W>),
}
fn dr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: WhichSubBlock) -> *mut W {

4
embassy-stm32/src/ucpd.rs
View File

@ -490,14 +490,14 @@ impl<'d, T: Instance> PdPhy<'d, T> {
let sr = r.sr().read();
if sr.rxhrstdet() {
dma.request_suspend();
dma.request_pause();
// Clean and re-enable hard reset receive interrupt.
r.icr().write(|w| w.set_rxhrstdetcf(true));
r.imr().modify(|w| w.set_rxhrstdetie(true));
Poll::Ready(Err(RxError::HardReset))
} else if sr.rxmsgend() {
dma.request_suspend();
dma.request_pause();
// Should be read immediately on interrupt.
rxpaysz = r.rx_payszr().read().rxpaysz().into();

4
embassy-stm32/src/usart/ringbuffered.rs
View File

@ -83,7 +83,7 @@ pub struct RingBufferedUartRx<'d> {
kernel_clock: Hertz,
rx: Option<Peri<'d, AnyPin>>,
rts: Option<Peri<'d, AnyPin>>,
ring_buf: ReadableRingBuffer<'d, u8, 2>,
ring_buf: ReadableRingBuffer<'d, u8>,
}
impl<'d> SetConfig for RingBufferedUartRx<'d> {
@ -165,7 +165,7 @@ impl<'d> RingBufferedUartRx<'d> {
/// Stop DMA backed UART receiver
fn stop_uart(&mut self) {
self.ring_buf.request_suspend();
self.ring_buf.request_pause();
let r = self.info.regs;
// clear all interrupts and DMA Rx Request