From f0fc1a15da774f2cc6338697e40f9d1fc7975eb5 Mon Sep 17 00:00:00 2001 From: elagil Date: Mon, 25 Aug 2025 21:10:59 +0200 Subject: [PATCH] fix: disable half-complete interrupt --- embassy-stm32/src/dma/gpdma/ringbuffered.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs index c5c18930b..6bd48258b 100644 --- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs +++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs @@ -82,7 +82,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> { let half_len = buffer.len() / 2; assert_eq!(half_len * 2, buffer.len()); - options.half_transfer_ir = true; + options.half_transfer_ir = false; options.complete_transfer_ir = true; let items = [ @@ -233,7 +233,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> { let half_len = buffer.len() / 2; assert_eq!(half_len * 2, buffer.len()); - options.half_transfer_ir = true; + options.half_transfer_ir = false; options.complete_transfer_ir = true; let items = [