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stm32-metapack: Corrects the RTC register map for l4p and l4q.

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It also includes improvements in accuracy of the l412 and l422 RTC register map.
This commit is contained in:
Piotr Esden-Tempski 2025-09-24 16:43:19 -07:00
parent 56019ba197
commit fc8c3e1e4b
2 changed files with 4 additions and 2 deletions
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2
embassy-stm32/CHANGELOG.md
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@ -23,6 +23,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- feat: Allow OSPI DMA writes larger than 64kB using chunking
- feat: More ADC enums for g0 PAC, API change for oversampling, allow separate sample times
- feat: Add USB CRS sync support for STM32C071
- fix: RTC register definition for STM32L4P5 and L4Q5 as they use v3 register map.
- fix: Cut down the capabilities of the STM32L412 and L422 RTC as those are missing binary timer mode and underflow interrupt.
## 0.4.0 - 2025-08-26

4
embassy-stm32/Cargo.toml
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@ -174,7 +174,7 @@ futures-util = { version = "0.3.30", default-features = false }
sdio-host = "0.9.0"
critical-section = "1.1"
#stm32-metapac = { version = "18" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b46fcc32f329f05fbdca4c007ed4bc305b0ade85" }
vcell = "0.1.3"
nb = "1.0.0"
@ -204,7 +204,7 @@ proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cf72eac610259fd78ef16f1c63be69a144d75f7", default-features = false, features = ["metadata"] }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b46fcc32f329f05fbdca4c007ed4bc305b0ade85", default-features = false, features = ["metadata"] }
[features]
default = ["rt"]