etiennecollin
a2daa9739f
fix: removed functions exposing channel registers
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These functions could be used to cause UB.
2025-09-05 14:43:29 +02:00
etiennecollin
2f24568de0
feat: custom dma configuration using RegisterUpdaters struct
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See this PR comment:
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2889283939
2025-09-05 14:43:29 +02:00
etiennecollin
f67365a067
fix: suspend before reset
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This follows the procedure outlined in the STM32U5 reference manual at
page 696.
2025-09-05 14:43:29 +02:00
etiennecollin
4999069198
feat: use provided TransferOptions instead of defaults
2025-09-05 14:43:29 +02:00
etiennecollin
277c59857b
feat: custom DMA channel configuration
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See
https://github.com/embassy-rs/embassy/pull/3923#issuecomment-2888810087
The default configuration of the channel which was done in `start()` is
now done in `new()` this allows overriding some settings through the new
`get_dma_channel` function. Only ringbuffers support this;
`LinkedListTransfer` and `Transfer` do not support that yet.
2025-09-05 14:43:29 +02:00
etiennecollin
c0b8e9c7e5
fix: writing reserved bits
2025-09-05 14:43:29 +02:00
etiennecollin
fec14213ea
fix: modified dma channel state management
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See
https://github.com/embassy-rs/embassy/pull/3923#discussion_r2094570176
2025-09-05 14:43:29 +02:00
elagil
7d224d94c4
fix: docstring
2025-09-05 14:43:29 +02:00
elagil
40a0d5d8f2
fix: build warnings
2025-09-05 14:43:29 +02:00
elagil
3d161e98a1
fix: simplify
2025-09-05 14:43:29 +02:00
elagil
7a62b8eee8
fix: build issues
2025-09-05 14:43:29 +02:00
elagil
a4d3b4b6ae
feat: wip, write buffer in halves
2025-09-05 14:43:29 +02:00
elagil
78364b966e
chore: change naming
2025-09-05 14:43:29 +02:00
elagil
2baa4399a7
fix: wip gpdma
2025-09-05 14:43:29 +02:00
elagil
50224583db
fix: load/store ordering
2025-09-05 14:43:29 +02:00
elagil
bfd82ff82c
fix: read transfer options
2025-09-05 14:43:29 +02:00
elagil
1541f1e0c2
chore: clean up transfer options
2025-09-05 14:43:29 +02:00
elagil
be88187591
fix: transfer options
2025-09-05 14:43:29 +02:00
elagil
f0fc1a15da
fix: disable half-complete interrupt
2025-09-05 14:43:29 +02:00
elagil
51b28aaa31
style: formatting
2025-09-05 14:43:29 +02:00
elagil
4155adbf8a
feat: ping-pong buffers
2025-09-05 14:43:29 +02:00
elagil
cf5b1ea9f5
feat: gpdma support (wip)
2025-09-05 14:43:29 +02:00
elagil
3c3b43fb00
feat: GPDAM linked-list + ringbuffer support
2025-09-05 14:43:29 +02:00
r.marple
089b6722c6
Added timer set polarity functions for main and complementary outputs individually
2025-09-03 16:14:08 +10:00
Fabian Wolter
0835b58deb
Update changelog
2025-09-02 21:25:42 +02:00
Fabian Wolter
56f3c7a8c7
stm32/i2c: fix failure of subsequent transmissions after NACK
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When a slave responds with a NACK in blocking I²C master mode, all subsequent transmissions send only the address followed immediately by a STOP.
This happens because the current implementation sets I2C_CR2.STOP = 1 whenever any error (including a NACK) occurs. As a result, the STOP bit is already set when the next transmission starts.
According to the reference manual: "If a NACK is received: […] a STOP condition is automatically sent […]"
This bug was not triggered until #4454 was merged.
2025-09-02 21:18:08 +02:00
Süha Ünüvar
010f4b08aa
derive Clone, Copy for qspi transfer config
2025-09-02 23:41:25 +08:00
Süha Ünüvar
91e33015c3
update changelog
2025-09-02 23:23:01 +08:00
Süha Ünüvar
698109acfe
derive Clone, Copy for qspi config
2025-09-02 23:20:01 +08:00
Gabriel Smith
fb8757c690
fix: stm32/usb: Fixed STM32H5 build requiring time feature
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A busy loop has been added for when the "time" feature is not enabled.
2025-08-29 10:46:33 -04:00
Dario Nieuwenhuis
f86cf87f2f
Merge pull request #4606 from diondokter/taskmeta-update-2
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Taskmeta update
2025-08-29 12:04:29 +00:00
Dario Nieuwenhuis
8aec341f28
executor: return error when creating the spawntoken, not when spawning.
2025-08-29 13:23:21 +02:00
Dario Nieuwenhuis
df10e8a6bc
Merge pull request #4602 from meowcakes/fix-stm32h7rs-boot
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Fix stm32h7rs init when using external flash via XSPI
2025-08-29 11:09:05 +00:00
Rogan Morrow
5fb4bbfc3e
don't save and reset XSPI clock source; let mux config handle it
2025-08-29 17:51:52 +10:00
Rogan Morrow
13fc222ef4
set XSPI clock source to HSI and reset after clock init; dont reset SYSCFG
2025-08-29 16:08:50 +10:00
Ulf Lilleengen
3e8d8fec15
fix: update more minor versions
2025-08-27 08:44:05 +02:00
Ulf Lilleengen
83f2557eac
chore: prepare embassy crate releases
2025-08-26 16:05:09 +02:00
Tomaz Maia Suller
0203b2b257
Merge branch 'main' into feat-independent-nodiv
2025-08-26 11:43:08 +02:00
tomaz-suller
541de3f4b4
Update changelog
2025-08-26 11:22:57 +02:00
tomaz-suller
f2bc5b7c8e
Update changelog
2025-08-26 11:21:34 +02:00
tomaz-suller
621c394f25
stm32/sai: make NODIV independent of MCKDIV
2025-08-26 11:08:57 +02:00
tomaz-suller
5e6669349c
stm32/sai: fix WB MCKDIV
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WB MCKDIV has a width of 6 bits (RM0434 Rev 14, p. 1269).
2025-08-26 10:52:04 +02:00
Ulf Lilleengen
c40c205636
fix: stm32 wb sai
2025-08-25 20:36:35 +02:00
Ulf Lilleengen
c1116d68c9
fix: bump metapac version
2025-08-25 20:17:29 +02:00
Dario Nieuwenhuis
9f12852c38
Read crate configs from metadata.
2025-08-25 19:44:50 +02:00
Ulf Lilleengen
6a347f1f09
feat: add semver checks and releasing to releaser
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* List dependencies of a crate
* List dependents of a crate
* Perform semver-checks of a crate
* Prepare a release for a crate and all dependents
* Use a single release.toml for cargo-release
* Add changelogs where missing
2025-08-25 19:44:49 +02:00
Ulf Lilleengen
cfe71df123
Merge branch 'main' into looping-adc-read
2025-08-25 09:53:18 +02:00
Gabriel Smith
5a1be543ac
stm32/adc/v3: allow DMA reads to loop through enabled channels
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Tested on an STM32H533RE. Documentation of other chips has been
reviewed, but not extensively.
2025-08-22 14:56:19 -04:00
Kevin Lannen
9db5a173d0
STM32 XSPI: Disable alternate bytes if not requested
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If a previous command used alternate bytes and the next command does not have them the alternate bytes need to be turned off
2025-08-22 09:27:24 -06:00
René van Dorst
52464b3536
Merge branch 'main' into i2c-pull-down-fix
2025-08-19 17:02:36 +02:00
