mirror of
https://github.com/embassy-rs/embassy.git
synced 2025-09-27 04:10:25 +00:00
766 lines
21 KiB
Rust
766 lines
21 KiB
Rust
use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::slice;
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use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
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use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
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use embassy_hal_internal::{into_ref, Peripheral};
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(not(any(usart_v1, usart_v2)))]
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use super::DePin;
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use super::{
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clear_interrupt_flags, configure, rdr, reconfigure, sr, tdr, Config, ConfigError, CtsPin, Error, Info, Instance,
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Regs, RtsPin, RxPin, TxPin,
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};
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use crate::gpio::AFType;
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use crate::interrupt::typelevel::Interrupt as _;
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use crate::interrupt::{self, InterruptExt};
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use crate::rcc;
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use crate::time::Hertz;
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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on_interrupt(T::info().regs, T::buffered_state())
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}
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}
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unsafe fn on_interrupt(r: Regs, state: &'static State) {
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// RX
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let sr_val = sr(r).read();
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// On v1 & v2, reading DR clears the rxne, error and idle interrupt
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// flags. Keep this close to the SR read to reduce the chance of a
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// flag being set in-between.
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let dr = if sr_val.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr_val.ore() || sr_val.idle()) {
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Some(rdr(r).read_volatile())
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} else {
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None
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};
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clear_interrupt_flags(r, sr_val);
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if sr_val.pe() {
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warn!("Parity error");
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}
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if sr_val.fe() {
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warn!("Framing error");
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}
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if sr_val.ne() {
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warn!("Noise error");
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}
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if sr_val.ore() {
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warn!("Overrun error");
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}
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if sr_val.rxne() {
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let mut rx_writer = state.rx_buf.writer();
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let buf = rx_writer.push_slice();
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if !buf.is_empty() {
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if let Some(byte) = dr {
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buf[0] = byte;
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rx_writer.push_done(1);
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}
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} else {
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// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
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}
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if !state.rx_buf.is_empty() {
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state.rx_waker.wake();
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}
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}
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if sr_val.idle() {
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state.rx_waker.wake();
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}
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// With `usart_v4` hardware FIFO is enabled and Transmission complete (TC)
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// indicates that all bytes are pushed out from the FIFO.
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// For other usart variants it shows that last byte from the buffer was just sent.
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if sr_val.tc() {
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// For others it is cleared above with `clear_interrupt_flags`.
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#[cfg(any(usart_v1, usart_v2))]
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sr(r).modify(|w| w.set_tc(false));
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r.cr1().modify(|w| {
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w.set_tcie(false);
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});
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state.tx_done.store(true, Ordering::Release);
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state.tx_waker.wake();
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}
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// TX
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if sr(r).read().txe() {
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let mut tx_reader = state.tx_buf.reader();
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let buf = tx_reader.pop_slice();
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if !buf.is_empty() {
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r.cr1().modify(|w| {
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w.set_txeie(true);
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});
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// Enable transmission complete interrupt when last byte is going to be sent out.
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if buf.len() == 1 {
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r.cr1().modify(|w| {
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w.set_tcie(true);
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});
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}
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tdr(r).write_volatile(buf[0].into());
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tx_reader.pop_done(1);
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} else {
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// Disable interrupt until we have something to transmit again.
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r.cr1().modify(|w| {
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w.set_txeie(false);
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});
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}
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}
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}
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pub(super) struct State {
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rx_waker: AtomicWaker,
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rx_buf: RingBuffer,
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tx_waker: AtomicWaker,
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tx_buf: RingBuffer,
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tx_done: AtomicBool,
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tx_rx_refcount: AtomicU8,
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}
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impl State {
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pub(super) const fn new() -> Self {
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Self {
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rx_buf: RingBuffer::new(),
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tx_buf: RingBuffer::new(),
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rx_waker: AtomicWaker::new(),
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tx_waker: AtomicWaker::new(),
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tx_done: AtomicBool::new(true),
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tx_rx_refcount: AtomicU8::new(0),
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}
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}
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}
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/// Bidirectional buffered UART
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pub struct BufferedUart<'d> {
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rx: BufferedUartRx<'d>,
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tx: BufferedUartTx<'d>,
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}
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/// Tx-only buffered UART
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///
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/// Created with [BufferedUart::split]
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pub struct BufferedUartTx<'d> {
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info: &'static Info,
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state: &'static State,
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kernel_clock: Hertz,
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_phantom: PhantomData<&'d mut ()>,
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}
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/// Rx-only buffered UART
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///
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/// Created with [BufferedUart::split]
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pub struct BufferedUartRx<'d> {
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info: &'static Info,
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state: &'static State,
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kernel_clock: Hertz,
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_phantom: PhantomData<&'d mut ()>,
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}
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impl<'d> SetConfig for BufferedUart<'d> {
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type Config = Config;
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type ConfigError = ConfigError;
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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self.set_config(config)
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}
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}
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impl<'d> SetConfig for BufferedUartRx<'d> {
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type Config = Config;
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type ConfigError = ConfigError;
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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self.set_config(config)
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}
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}
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impl<'d> SetConfig for BufferedUartTx<'d> {
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type Config = Config;
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type ConfigError = ConfigError;
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fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
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self.set_config(config)
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}
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}
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impl<'d> BufferedUart<'d> {
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/// Create a new bidirectional buffered UART driver
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pub fn new<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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}
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/// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
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pub fn new_with_rtscts<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(cts, rts);
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rcc::enable_and_reset::<T>();
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rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
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cts.set_as_af(cts.af_num(), AFType::Input);
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T::info().regs.cr3().write(|w| {
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w.set_rtse(true);
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w.set_ctse(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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}
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/// Create a new bidirectional buffered UART driver with a driver-enable pin
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#[cfg(not(any(usart_v1, usart_v2)))]
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pub fn new_with_de<T: Instance>(
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peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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de: impl Peripheral<P = impl DePin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(de);
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rcc::enable_and_reset::<T>();
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de.set_as_af(de.af_num(), AFType::OutputPushPull);
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T::info().regs.cr3().write(|w| {
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w.set_dem(true);
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});
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Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
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}
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fn new_inner<T: Instance>(
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_peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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into_ref!(_peri, rx, tx);
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let info = T::info();
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let state = T::buffered_state();
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let kernel_clock = T::frequency();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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let r = info.regs;
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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configure(info, kernel_clock, &config, true, true)?;
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r.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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Ok(Self {
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rx: BufferedUartRx {
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info,
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state,
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kernel_clock,
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_phantom: PhantomData,
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},
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tx: BufferedUartTx {
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info,
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state,
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kernel_clock,
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_phantom: PhantomData,
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},
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})
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}
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/// Split the driver into a Tx and Rx part (useful for sending to separate tasks)
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pub fn split(self) -> (BufferedUartTx<'d>, BufferedUartRx<'d>) {
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(self.tx, self.rx)
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}
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/// Reconfigure the driver
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pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
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reconfigure(self.rx.info, self.rx.kernel_clock, config)?;
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self.rx.info.regs.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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Ok(())
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}
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}
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impl<'d> BufferedUartRx<'d> {
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async fn read(&self, buf: &mut [u8]) -> Result<usize, Error> {
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poll_fn(move |cx| {
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let state = self.state;
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let data = rx_reader.pop_slice();
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if !data.is_empty() {
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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let do_pend = state.rx_buf.is_full();
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rx_reader.pop_done(len);
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if do_pend {
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self.info.interrupt.pend();
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}
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return Poll::Ready(Ok(len));
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}
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state.rx_waker.register(cx.waker());
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Poll::Pending
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})
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.await
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}
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fn blocking_read(&self, buf: &mut [u8]) -> Result<usize, Error> {
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loop {
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let state = self.state;
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let data = rx_reader.pop_slice();
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if !data.is_empty() {
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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let do_pend = state.rx_buf.is_full();
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rx_reader.pop_done(len);
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if do_pend {
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self.info.interrupt.pend();
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}
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return Ok(len);
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}
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}
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}
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async fn fill_buf(&self) -> Result<&[u8], Error> {
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poll_fn(move |cx| {
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let state = self.state;
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let (p, n) = rx_reader.pop_buf();
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if n == 0 {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let buf = unsafe { slice::from_raw_parts(p, n) };
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Poll::Ready(Ok(buf))
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})
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.await
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}
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fn consume(&self, amt: usize) {
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let state = self.state;
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let full = state.rx_buf.is_full();
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rx_reader.pop_done(amt);
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if full {
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self.info.interrupt.pend();
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}
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}
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/// Reconfigure the driver
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pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
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reconfigure(self.info, self.kernel_clock, config)?;
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self.info.regs.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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Ok(())
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}
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}
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impl<'d> BufferedUartTx<'d> {
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async fn write(&self, buf: &[u8]) -> Result<usize, Error> {
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poll_fn(move |cx| {
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let state = self.state;
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state.tx_done.store(false, Ordering::Release);
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let empty = state.tx_buf.is_empty();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let data = tx_writer.push_slice();
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if data.is_empty() {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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tx_writer.push_done(n);
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if empty {
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self.info.interrupt.pend();
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}
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Poll::Ready(Ok(n))
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})
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.await
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}
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async fn flush(&self) -> Result<(), Error> {
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poll_fn(move |cx| {
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let state = self.state;
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if !state.tx_done.load(Ordering::Acquire) {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Poll::Ready(Ok(()))
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})
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.await
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}
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fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> {
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loop {
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let state = self.state;
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let empty = state.tx_buf.is_empty();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let data = tx_writer.push_slice();
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if !data.is_empty() {
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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tx_writer.push_done(n);
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if empty {
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self.info.interrupt.pend();
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}
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return Ok(n);
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}
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}
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}
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fn blocking_flush(&self) -> Result<(), Error> {
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loop {
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let state = self.state;
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if state.tx_buf.is_empty() {
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return Ok(());
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}
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}
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}
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|
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/// Reconfigure the driver
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pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
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reconfigure(self.info, self.kernel_clock, config)?;
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self.info.regs.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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Ok(())
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}
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}
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|
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impl<'d> Drop for BufferedUartRx<'d> {
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fn drop(&mut self) {
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let state = self.state;
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unsafe {
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state.rx_buf.deinit();
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|
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// TX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.tx_buf.len() == 0 {
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self.info.interrupt.disable();
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}
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}
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drop_tx_rx(self.info, state);
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}
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}
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impl<'d> Drop for BufferedUartTx<'d> {
|
|
fn drop(&mut self) {
|
|
let state = self.state;
|
|
unsafe {
|
|
state.tx_buf.deinit();
|
|
|
|
// RX is inactive if the the buffer is not available.
|
|
// We can now unregister the interrupt handler
|
|
if state.rx_buf.len() == 0 {
|
|
self.info.interrupt.disable();
|
|
}
|
|
}
|
|
|
|
drop_tx_rx(self.info, state);
|
|
}
|
|
}
|
|
|
|
fn drop_tx_rx(info: &Info, state: &State) {
|
|
// We cannot use atomic subtraction here, because it's not supported for all targets
|
|
let is_last_drop = critical_section::with(|_| {
|
|
let refcount = state.tx_rx_refcount.load(Ordering::Relaxed);
|
|
assert!(refcount >= 1);
|
|
state.tx_rx_refcount.store(refcount - 1, Ordering::Relaxed);
|
|
refcount == 1
|
|
});
|
|
if is_last_drop {
|
|
info.rcc.disable();
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::ErrorType for BufferedUart<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_io_async::ErrorType for BufferedUartRx<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_io_async::ErrorType for BufferedUartTx<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_io_async::Read for BufferedUart<'d> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.rx.read(buf).await
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::Read for BufferedUartRx<'d> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
Self::read(self, buf).await
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::BufRead for BufferedUart<'d> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
self.rx.fill_buf().await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
self.rx.consume(amt)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::BufRead for BufferedUartRx<'d> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
Self::fill_buf(self).await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
Self::consume(self, amt)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::Write for BufferedUart<'d> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.tx.write(buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.tx.flush().await
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io_async::Write for BufferedUartTx<'d> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
Self::write(self, buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Self::flush(self).await
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io::Read for BufferedUart<'d> {
|
|
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.rx.blocking_read(buf)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io::Read for BufferedUartRx<'d> {
|
|
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.blocking_read(buf)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io::Write for BufferedUart<'d> {
|
|
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.tx.blocking_write(buf)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.tx.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_io::Write for BufferedUartTx<'d> {
|
|
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
Self::blocking_write(self, buf)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Self::blocking_flush(self)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
let r = self.info.regs;
|
|
unsafe {
|
|
let sr = sr(r).read();
|
|
if sr.pe() {
|
|
rdr(r).read_volatile();
|
|
Err(nb::Error::Other(Error::Parity))
|
|
} else if sr.fe() {
|
|
rdr(r).read_volatile();
|
|
Err(nb::Error::Other(Error::Framing))
|
|
} else if sr.ne() {
|
|
rdr(r).read_volatile();
|
|
Err(nb::Error::Other(Error::Noise))
|
|
} else if sr.ore() {
|
|
rdr(r).read_volatile();
|
|
Err(nb::Error::Other(Error::Overrun))
|
|
} else if sr.rxne() {
|
|
Ok(rdr(r).read_volatile())
|
|
} else {
|
|
Err(nb::Error::WouldBlock)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
|
|
while !buffer.is_empty() {
|
|
match self.blocking_write(buffer) {
|
|
Ok(0) => panic!("zero-length write."),
|
|
Ok(n) => buffer = &buffer[n..],
|
|
Err(e) => return Err(e),
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUart<'d> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
embedded_hal_02::serial::Read::read(&mut self.rx)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
|
|
while !buffer.is_empty() {
|
|
match self.tx.blocking_write(buffer) {
|
|
Ok(0) => panic!("zero-length write."),
|
|
Ok(n) => buffer = &buffer[n..],
|
|
Err(e) => return Err(e),
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.tx.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUart<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::Read for BufferedUartRx<'d> {
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
embedded_hal_02::serial::Read::read(self)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::Write for BufferedUartTx<'d> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::Read for BufferedUart<'d> {
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
embedded_hal_02::serial::Read::read(&mut self.rx)
|
|
}
|
|
}
|
|
|
|
impl<'d> embedded_hal_nb::serial::Write for BufferedUart<'d> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.tx.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.tx.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|