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esp-storage now depends on esp-hal (#4173)

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* esp-storage now depends on esp-hal

* clean up cfg gates

* changelog
This commit is contained in:
Juraj Sadel 2025-09-24 10:55:26 +02:00 committed by GitHub
parent f3907af22b
commit 0180a38ba0
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
26 changed files with 304 additions and 297 deletions
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15
esp-metadata-generated/src/_build_script_utils.rs
View File

@ -201,6 +201,7 @@ impl Chip {
"soc_has_cpu_ctrl", "soc_has_cpu_ctrl",
"soc_has_dac1", "soc_has_dac1",
"soc_has_dac2", "soc_has_dac2",
"soc_has_flash",
"soc_has_psram", "soc_has_psram",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_touch", "soc_has_touch",
@ -363,6 +364,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_cpu_ctrl", "cargo:rustc-cfg=soc_has_cpu_ctrl",
"cargo:rustc-cfg=soc_has_dac1", "cargo:rustc-cfg=soc_has_dac1",
"cargo:rustc-cfg=soc_has_dac2", "cargo:rustc-cfg=soc_has_dac2",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_psram", "cargo:rustc-cfg=soc_has_psram",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_touch", "cargo:rustc-cfg=soc_has_touch",
@ -502,6 +504,7 @@ impl Chip {
"soc_has_dma_ch0", "soc_has_dma_ch0",
"soc_has_adc1", "soc_has_adc1",
"soc_has_bt", "soc_has_bt",
"soc_has_flash",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_wifi", "soc_has_wifi",
"soc_has_mem2mem1", "soc_has_mem2mem1",
@ -622,6 +625,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_dma_ch0", "cargo:rustc-cfg=soc_has_dma_ch0",
"cargo:rustc-cfg=soc_has_adc1", "cargo:rustc-cfg=soc_has_adc1",
"cargo:rustc-cfg=soc_has_bt", "cargo:rustc-cfg=soc_has_bt",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_wifi", "cargo:rustc-cfg=soc_has_wifi",
"cargo:rustc-cfg=soc_has_mem2mem1", "cargo:rustc-cfg=soc_has_mem2mem1",
@ -761,6 +765,7 @@ impl Chip {
"soc_has_adc1", "soc_has_adc1",
"soc_has_adc2", "soc_has_adc2",
"soc_has_bt", "soc_has_bt",
"soc_has_flash",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_tsens", "soc_has_tsens",
"soc_has_wifi", "soc_has_wifi",
@ -923,6 +928,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_adc1", "cargo:rustc-cfg=soc_has_adc1",
"cargo:rustc-cfg=soc_has_adc2", "cargo:rustc-cfg=soc_has_adc2",
"cargo:rustc-cfg=soc_has_bt", "cargo:rustc-cfg=soc_has_bt",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_tsens", "cargo:rustc-cfg=soc_has_tsens",
"cargo:rustc-cfg=soc_has_wifi", "cargo:rustc-cfg=soc_has_wifi",
@ -1117,6 +1123,7 @@ impl Chip {
"soc_has_dma_ch2", "soc_has_dma_ch2",
"soc_has_adc1", "soc_has_adc1",
"soc_has_bt", "soc_has_bt",
"soc_has_flash",
"soc_has_lp_core", "soc_has_lp_core",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_tsens", "soc_has_tsens",
@ -1335,6 +1342,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_dma_ch2", "cargo:rustc-cfg=soc_has_dma_ch2",
"cargo:rustc-cfg=soc_has_adc1", "cargo:rustc-cfg=soc_has_adc1",
"cargo:rustc-cfg=soc_has_bt", "cargo:rustc-cfg=soc_has_bt",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_lp_core", "cargo:rustc-cfg=soc_has_lp_core",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_tsens", "cargo:rustc-cfg=soc_has_tsens",
@ -1548,6 +1556,7 @@ impl Chip {
"soc_has_dma_ch2", "soc_has_dma_ch2",
"soc_has_adc1", "soc_has_adc1",
"soc_has_bt", "soc_has_bt",
"soc_has_flash",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_mem2mem1", "soc_has_mem2mem1",
"soc_has_mem2mem4", "soc_has_mem2mem4",
@ -1737,6 +1746,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_dma_ch2", "cargo:rustc-cfg=soc_has_dma_ch2",
"cargo:rustc-cfg=soc_has_adc1", "cargo:rustc-cfg=soc_has_adc1",
"cargo:rustc-cfg=soc_has_bt", "cargo:rustc-cfg=soc_has_bt",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_mem2mem1", "cargo:rustc-cfg=soc_has_mem2mem1",
"cargo:rustc-cfg=soc_has_mem2mem4", "cargo:rustc-cfg=soc_has_mem2mem4",
@ -1920,6 +1930,7 @@ impl Chip {
"soc_has_adc2", "soc_has_adc2",
"soc_has_dac1", "soc_has_dac1",
"soc_has_dac2", "soc_has_dac2",
"soc_has_flash",
"soc_has_psram", "soc_has_psram",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_ulp_riscv_core", "soc_has_ulp_riscv_core",
@ -2098,6 +2109,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_adc2", "cargo:rustc-cfg=soc_has_adc2",
"cargo:rustc-cfg=soc_has_dac1", "cargo:rustc-cfg=soc_has_dac1",
"cargo:rustc-cfg=soc_has_dac2", "cargo:rustc-cfg=soc_has_dac2",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_psram", "cargo:rustc-cfg=soc_has_psram",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_ulp_riscv_core", "cargo:rustc-cfg=soc_has_ulp_riscv_core",
@ -2287,6 +2299,7 @@ impl Chip {
"soc_has_adc2", "soc_has_adc2",
"soc_has_bt", "soc_has_bt",
"soc_has_cpu_ctrl", "soc_has_cpu_ctrl",
"soc_has_flash",
"soc_has_psram", "soc_has_psram",
"soc_has_sw_interrupt", "soc_has_sw_interrupt",
"soc_has_ulp_riscv_core", "soc_has_ulp_riscv_core",
@ -2487,6 +2500,7 @@ impl Chip {
"cargo:rustc-cfg=soc_has_adc2", "cargo:rustc-cfg=soc_has_adc2",
"cargo:rustc-cfg=soc_has_bt", "cargo:rustc-cfg=soc_has_bt",
"cargo:rustc-cfg=soc_has_cpu_ctrl", "cargo:rustc-cfg=soc_has_cpu_ctrl",
"cargo:rustc-cfg=soc_has_flash",
"cargo:rustc-cfg=soc_has_psram", "cargo:rustc-cfg=soc_has_psram",
"cargo:rustc-cfg=soc_has_sw_interrupt", "cargo:rustc-cfg=soc_has_sw_interrupt",
"cargo:rustc-cfg=soc_has_ulp_riscv_core", "cargo:rustc-cfg=soc_has_ulp_riscv_core",
@ -2704,6 +2718,7 @@ pub fn emit_check_cfg_directives() {
println!("cargo:rustc-check-cfg=cfg(soc_has_cpu_ctrl)"); println!("cargo:rustc-check-cfg=cfg(soc_has_cpu_ctrl)");
println!("cargo:rustc-check-cfg=cfg(soc_has_dac1)"); println!("cargo:rustc-check-cfg=cfg(soc_has_dac1)");
println!("cargo:rustc-check-cfg=cfg(soc_has_dac2)"); println!("cargo:rustc-check-cfg=cfg(soc_has_dac2)");
println!("cargo:rustc-check-cfg=cfg(soc_has_flash)");
println!("cargo:rustc-check-cfg=cfg(soc_has_psram)"); println!("cargo:rustc-check-cfg=cfg(soc_has_psram)");
println!("cargo:rustc-check-cfg=cfg(soc_has_sw_interrupt)"); println!("cargo:rustc-check-cfg=cfg(soc_has_sw_interrupt)");
println!("cargo:rustc-check-cfg=cfg(soc_has_touch)"); println!("cargo:rustc-check-cfg=cfg(soc_has_touch)");

97
esp-metadata-generated/src/_generated_esp32.rs
View File

@ -567,54 +567,55 @@ macro_rules! for_each_peripheral {
_for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <= _for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <=
virtual() (unstable))); _for_each_inner!((CPU_CTRL <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((CPU_CTRL <= virtual() (unstable)));
_for_each_inner!((DAC1 <= virtual() (unstable))); _for_each_inner!((DAC2 <= _for_each_inner!((DAC1 <= virtual() (unstable))); _for_each_inner!((DAC2 <=
virtual() (unstable))); _for_each_inner!((PSRAM <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((FLASH <= virtual() (unstable)));
_for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((TOUCH _for_each_inner!((PSRAM <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT
<= virtual() (unstable))); _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= <= virtual() (unstable))); _for_each_inner!((TOUCH <= virtual() (unstable)));
virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
(GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
(GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
(GPIO19 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO22 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
virtual()), (GPIO23 <= virtual()), (GPIO25 <= virtual()), (GPIO26 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO22 <= virtual()), (GPIO23 <=
(GPIO27 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), (GPIO34 <= virtual()), (GPIO25 <= virtual()), (GPIO26 <= virtual()), (GPIO27 <= virtual()),
virtual()), (GPIO35 <= virtual()), (GPIO36 <= virtual()), (GPIO37 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), (GPIO34 <= virtual()), (GPIO35 <=
(GPIO38 <= virtual()), (GPIO39 <= virtual()), (AES <= AES() (unstable)), virtual()), (GPIO36 <= virtual()), (GPIO37 <= virtual()), (GPIO38 <= virtual()),
(APB_CTRL <= APB_CTRL() (unstable)), (BB <= BB() (unstable)), (DPORT <= DPORT() (GPIO39 <= virtual()), (AES <= AES() (unstable)), (APB_CTRL <= APB_CTRL()
(unstable)), (SYSTEM <= DPORT() (unstable)), (EFUSE <= EFUSE() (unstable)), (unstable)), (BB <= BB() (unstable)), (DPORT <= DPORT() (unstable)), (SYSTEM <=
(EMAC_DMA <= EMAC_DMA() (unstable)), (EMAC_EXT <= EMAC_EXT() (unstable)), DPORT() (unstable)), (EFUSE <= EFUSE() (unstable)), (EMAC_DMA <= EMAC_DMA()
(EMAC_MAC <= EMAC_MAC() (unstable)), (FLASH_ENCRYPTION <= FLASH_ENCRYPTION() (unstable)), (EMAC_EXT <= EMAC_EXT() (unstable)), (EMAC_MAC <= EMAC_MAC()
(unstable)), (FRC_TIMER <= FRC_TIMER() (unstable)), (GPIO <= GPIO() (unstable)), (unstable)), (FLASH_ENCRYPTION <= FLASH_ENCRYPTION() (unstable)), (FRC_TIMER <=
(GPIO_SD <= GPIO_SD() (unstable)), (HINF <= HINF() (unstable)), (I2C0 <= FRC_TIMER() (unstable)), (GPIO <= GPIO() (unstable)), (GPIO_SD <= GPIO_SD()
I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt, (unstable)), (HINF <= HINF() (unstable)), (I2C0 <= I2C0(I2C_EXT0 : {
disable_peri_interrupt })), (I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt, bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (I2C1 <=
enable_peri_interrupt, disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : { I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt,
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
(unstable)), (I2S1 <= I2S1(I2S1 : { bind_peri_interrupt, enable_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (I2S1 <= I2S1(I2S1
disable_peri_interrupt }) (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LEDC <= : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
LEDC() (unstable)), (MCPWM0 <= MCPWM0() (unstable)), (MCPWM1 <= MCPWM1() (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LEDC <= LEDC() (unstable)),
(unstable)), (NRX <= NRX() (unstable)), (PCNT <= PCNT() (unstable)), (RMT <= (MCPWM0 <= MCPWM0() (unstable)), (MCPWM1 <= MCPWM1() (unstable)), (NRX <= NRX()
RMT() (unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : { (unstable)), (PCNT <= PCNT() (unstable)), (RMT <= RMT() (unstable)), (RNG <=
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) RNG() (unstable)), (RSA <= RSA(RSA : { bind_peri_interrupt,
(unstable)), (LPWR <= RTC_CNTL() (unstable)), (RTC_I2C <= RTC_I2C() (unstable)), enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (LPWR <= RTC_CNTL()
(RTC_IO <= RTC_IO() (unstable)), (SDHOST <= SDHOST() (unstable)), (SENS <= SENS() (unstable)), (RTC_I2C <= RTC_I2C() (unstable)), (RTC_IO <= RTC_IO() (unstable)),
(unstable)), (SHA <= SHA() (unstable)), (SLC <= SLC() (unstable)), (SLCHOST <= (SDHOST <= SDHOST() (unstable)), (SENS <= SENS() (unstable)), (SHA <= SHA()
SLCHOST() (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <= SPI1() (unstable)), (unstable)), (SLC <= SLC() (unstable)), (SLCHOST <= SLCHOST() (unstable)), (SPI0
(SPI2 <= SPI2(SPI2_DMA : { bind_dma_interrupt, enable_dma_interrupt, <= SPI0() (unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <= SPI2(SPI2_DMA : {
disable_dma_interrupt }, SPI2 : { bind_peri_interrupt, enable_peri_interrupt, bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }, SPI2 : {
disable_peri_interrupt })), (SPI3 <= SPI3(SPI3_DMA : { bind_dma_interrupt, bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SPI3 <=
enable_dma_interrupt, disable_dma_interrupt }, SPI3 : { bind_peri_interrupt, SPI3(SPI3_DMA : { bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt
enable_peri_interrupt, disable_peri_interrupt })), (TIMG0 <= TIMG0() (unstable)), }, SPI3 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
(TIMG1 <= TIMG1() (unstable)), (TWAI0 <= TWAI0() (unstable)), (UART0 <= })), (TIMG0 <= TIMG0() (unstable)), (TIMG1 <= TIMG1() (unstable)), (TWAI0 <=
UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt, TWAI0() (unstable)), (UART0 <= UART0(UART0 : { bind_peri_interrupt,
disable_peri_interrupt })), (UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UART1 <= UART1(UART1 : {
enable_peri_interrupt, disable_peri_interrupt })), (UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UART2 <=
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UHCI0 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
UHCI0() (unstable)), (UHCI1 <= UHCI1() (unstable)), (WIFI <= WIFI() (unstable)), disable_peri_interrupt })), (UHCI0 <= UHCI0() (unstable)), (UHCI1 <= UHCI1()
(DMA_SPI2 <= SPI2() (unstable)), (DMA_SPI3 <= SPI3() (unstable)), (DMA_I2S0 <= (unstable)), (WIFI <= WIFI() (unstable)), (DMA_SPI2 <= SPI2() (unstable)),
I2S0() (unstable)), (DMA_I2S1 <= I2S1() (unstable)), (ADC1 <= virtual() (DMA_SPI3 <= SPI3() (unstable)), (DMA_I2S0 <= I2S0() (unstable)), (DMA_I2S1 <=
(unstable)), (ADC2 <= virtual() (unstable)), (BT <= virtual() (unstable)), I2S1() (unstable)), (ADC1 <= virtual() (unstable)), (ADC2 <= virtual()
(CPU_CTRL <= virtual() (unstable)), (DAC1 <= virtual() (unstable)), (DAC2 <= (unstable)), (BT <= virtual() (unstable)), (CPU_CTRL <= virtual() (unstable)),
(DAC1 <= virtual() (unstable)), (DAC2 <= virtual() (unstable)), (FLASH <=
virtual() (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <=
virtual() (unstable)), (TOUCH <= virtual() (unstable)))); virtual() (unstable)), (TOUCH <= virtual() (unstable))));
}; };

76
esp-metadata-generated/src/_generated_esp32c2.rs
View File

@ -385,44 +385,44 @@ macro_rules! for_each_peripheral {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }))); bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })));
_for_each_inner!((XTS_AES <= XTS_AES() (unstable))); _for_each_inner!((DMA_CH0 <= _for_each_inner!((XTS_AES <= XTS_AES() (unstable))); _for_each_inner!((DMA_CH0 <=
virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= _for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((FLASH <=
virtual() (unstable))); _for_each_inner!((WIFI <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable)));
_for_each_inner!((MEM2MEM1 <= virtual() (unstable))); _for_each_inner!((MEM2MEM2 _for_each_inner!((WIFI <= virtual() (unstable))); _for_each_inner!((MEM2MEM1 <=
<= virtual() (unstable))); _for_each_inner!((MEM2MEM3 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((MEM2MEM2 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM4 <= virtual() (unstable))); _for_each_inner!((MEM2MEM5 _for_each_inner!((MEM2MEM3 <= virtual() (unstable))); _for_each_inner!((MEM2MEM4
<= virtual() (unstable))); _for_each_inner!((MEM2MEM6 <= virtual() (unstable))); <= virtual() (unstable))); _for_each_inner!((MEM2MEM5 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM7 <= virtual() (unstable))); _for_each_inner!((MEM2MEM8 _for_each_inner!((MEM2MEM6 <= virtual() (unstable))); _for_each_inner!((MEM2MEM7
<= virtual() (unstable))); _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= <= virtual() (unstable))); _for_each_inner!((MEM2MEM8 <= virtual() (unstable)));
virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
(GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
(GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
(GPIO19 <= virtual()), (GPIO20 <= virtual()), (APB_CTRL <= APB_CTRL() virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
(unstable)), (APB_SARADC <= APB_SARADC() (unstable)), (BB <= BB() (unstable)), (GPIO20 <= virtual()), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <=
(ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (DMA <= DMA() (unstable)), (ECC <= APB_SARADC() (unstable)), (BB <= BB() (unstable)), (ASSIST_DEBUG <=
ECC() (unstable)), (EFUSE <= EFUSE() (unstable)), (EXTMEM <= EXTMEM() ASSIST_DEBUG() (unstable)), (DMA <= DMA() (unstable)), (ECC <= ECC() (unstable)),
(unstable)), (GPIO <= GPIO() (unstable)), (I2C_ANA_MST <= I2C_ANA_MST() (EFUSE <= EFUSE() (unstable)), (EXTMEM <= EXTMEM() (unstable)), (GPIO <= GPIO()
(unstable)), (I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, (unstable)), (I2C_ANA_MST <= I2C_ANA_MST() (unstable)), (I2C0 <= I2C0(I2C_EXT0 :
enable_peri_interrupt, disable_peri_interrupt })), (INTERRUPT_CORE0 <= { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })),
INTERRUPT_CORE0() (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LEDC <= LEDC() (INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (IO_MUX <= IO_MUX()
(unstable)), (RNG <= RNG() (unstable)), (LPWR <= RTC_CNTL() (unstable)), (unstable)), (LEDC <= LEDC() (unstable)), (RNG <= RNG() (unstable)), (LPWR <=
(MODEM_CLKRST <= MODEM_CLKRST() (unstable)), (SENSITIVE <= SENSITIVE() RTC_CNTL() (unstable)), (MODEM_CLKRST <= MODEM_CLKRST() (unstable)), (SENSITIVE
(unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, <= SENSITIVE() (unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt,
disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <= enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0()
SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt, (unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : {
enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM <= SYSTEM() bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM
(unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0() (unstable)), <= SYSTEM() (unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0()
(UART0 <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt, (unstable)), (UART0 <= UART0(UART0 : { bind_peri_interrupt,
disable_peri_interrupt })), (UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UART1 <= UART1(UART1 : {
enable_peri_interrupt, disable_peri_interrupt })), (XTS_AES <= XTS_AES() bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (XTS_AES
(unstable)), (DMA_CH0 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)), <= XTS_AES() (unstable)), (DMA_CH0 <= virtual() (unstable)), (ADC1 <= virtual()
(BT <= virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (WIFI <= (unstable)), (BT <= virtual() (unstable)), (FLASH <= virtual() (unstable)),
virtual() (unstable)), (MEM2MEM1 <= virtual() (unstable)), (MEM2MEM2 <= virtual() (SW_INTERRUPT <= virtual() (unstable)), (WIFI <= virtual() (unstable)), (MEM2MEM1
(unstable)), (MEM2MEM3 <= virtual() (unstable)), (MEM2MEM4 <= virtual() <= virtual() (unstable)), (MEM2MEM2 <= virtual() (unstable)), (MEM2MEM3 <=
(unstable)), (MEM2MEM5 <= virtual() (unstable)), (MEM2MEM6 <= virtual() virtual() (unstable)), (MEM2MEM4 <= virtual() (unstable)), (MEM2MEM5 <= virtual()
(unstable)), (MEM2MEM7 <= virtual() (unstable)), (MEM2MEM8 <= virtual() (unstable)), (MEM2MEM6 <= virtual() (unstable)), (MEM2MEM7 <= virtual()
(unstable)))); (unstable)), (MEM2MEM8 <= virtual() (unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

27
esp-metadata-generated/src/_generated_esp32c3.rs
View File

@ -604,16 +604,17 @@ macro_rules! for_each_peripheral {
_for_each_inner!((DMA_CH1 <= virtual() (unstable))); _for_each_inner!((DMA_CH2 <= _for_each_inner!((DMA_CH1 <= virtual() (unstable))); _for_each_inner!((DMA_CH2 <=
virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <= _for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <=
virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((FLASH <= virtual() (unstable)));
_for_each_inner!((TSENS <= virtual() (unstable))); _for_each_inner!((WIFI <= _for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((TSENS
virtual() (unstable))); _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= <= virtual() (unstable))); _for_each_inner!((WIFI <= virtual() (unstable)));
virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
(GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
(GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
(GPIO19 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (AES <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
AES(AES : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) (GPIO20 <= virtual()), (GPIO21 <= virtual()), (AES <= AES(AES : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <= APB_SARADC() (unstable)), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <= APB_SARADC()
(unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (BB <= BB() (unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (BB <= BB()
(unstable)), (DMA <= DMA() (unstable)), (DS <= DS() (unstable)), (EFUSE <= (unstable)), (DMA <= DMA() (unstable)), (DS <= DS() (unstable)), (EFUSE <=
@ -641,9 +642,9 @@ macro_rules! for_each_peripheral {
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (XTS_AES <= enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (XTS_AES <=
XTS_AES() (unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual() XTS_AES() (unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual()
(unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)), (unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)),
(ADC2 <= virtual() (unstable)), (BT <= virtual() (unstable)), (SW_INTERRUPT <= (ADC2 <= virtual() (unstable)), (BT <= virtual() (unstable)), (FLASH <= virtual()
virtual() (unstable)), (TSENS <= virtual() (unstable)), (WIFI <= virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (TSENS <= virtual()
(unstable)))); (unstable)), (WIFI <= virtual() (unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

28
esp-metadata-generated/src/_generated_esp32c6.rs
View File

@ -637,12 +637,13 @@ macro_rules! for_each_peripheral {
(unstable))); _for_each_inner!((DMA_CH0 <= virtual() (unstable))); (unstable))); _for_each_inner!((DMA_CH0 <= virtual() (unstable)));
_for_each_inner!((DMA_CH1 <= virtual() (unstable))); _for_each_inner!((DMA_CH2 <= _for_each_inner!((DMA_CH1 <= virtual() (unstable))); _for_each_inner!((DMA_CH2 <=
virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((LP_CORE <= _for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((FLASH <=
virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((LP_CORE <= virtual() (unstable)));
_for_each_inner!((TSENS <= virtual() (unstable))); _for_each_inner!((WIFI <= _for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((TSENS
virtual() (unstable))); _for_each_inner!((MEM2MEM1 <= virtual() (unstable))); <= virtual() (unstable))); _for_each_inner!((WIFI <= virtual() (unstable)));
_for_each_inner!((MEM2MEM4 <= virtual() (unstable))); _for_each_inner!((MEM2MEM5 _for_each_inner!((MEM2MEM1 <= virtual() (unstable))); _for_each_inner!((MEM2MEM4
<= virtual() (unstable))); _for_each_inner!((MEM2MEM10 <= virtual() (unstable))); <= virtual() (unstable))); _for_each_inner!((MEM2MEM5 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM10 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM11 <= virtual() (unstable))); _for_each_inner!((MEM2MEM11 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM12 <= virtual() (unstable))); _for_each_inner!((MEM2MEM12 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM13 <= virtual() (unstable))); _for_each_inner!((MEM2MEM13 <= virtual() (unstable)));
@ -699,13 +700,14 @@ macro_rules! for_each_peripheral {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual() (unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual()
(unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)), (unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)),
(BT <= virtual() (unstable)), (LP_CORE <= virtual() (unstable)), (SW_INTERRUPT <= (BT <= virtual() (unstable)), (FLASH <= virtual() (unstable)), (LP_CORE <=
virtual() (unstable)), (TSENS <= virtual() (unstable)), (WIFI <= virtual() virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (TSENS <=
(unstable)), (MEM2MEM1 <= virtual() (unstable)), (MEM2MEM4 <= virtual() virtual() (unstable)), (WIFI <= virtual() (unstable)), (MEM2MEM1 <= virtual()
(unstable)), (MEM2MEM5 <= virtual() (unstable)), (MEM2MEM10 <= virtual() (unstable)), (MEM2MEM4 <= virtual() (unstable)), (MEM2MEM5 <= virtual()
(unstable)), (MEM2MEM11 <= virtual() (unstable)), (MEM2MEM12 <= virtual() (unstable)), (MEM2MEM10 <= virtual() (unstable)), (MEM2MEM11 <= virtual()
(unstable)), (MEM2MEM13 <= virtual() (unstable)), (MEM2MEM14 <= virtual() (unstable)), (MEM2MEM12 <= virtual() (unstable)), (MEM2MEM13 <= virtual()
(unstable)), (MEM2MEM15 <= virtual() (unstable)))); (unstable)), (MEM2MEM14 <= virtual() (unstable)), (MEM2MEM15 <= virtual()
(unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

20
esp-metadata-generated/src/_generated_esp32h2.rs
View File

@ -614,10 +614,10 @@ macro_rules! for_each_peripheral {
(unstable))); _for_each_inner!((DMA_CH1 <= virtual() (unstable))); (unstable))); _for_each_inner!((DMA_CH1 <= virtual() (unstable)));
_for_each_inner!((DMA_CH2 <= virtual() (unstable))); _for_each_inner!((ADC1 <= _for_each_inner!((DMA_CH2 <= virtual() (unstable))); _for_each_inner!((ADC1 <=
virtual() (unstable))); _for_each_inner!((BT <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((BT <= virtual() (unstable)));
_for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((FLASH <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT
_for_each_inner!((MEM2MEM1 <= virtual() (unstable))); _for_each_inner!((MEM2MEM4 <= virtual() (unstable))); _for_each_inner!((MEM2MEM1 <= virtual() (unstable)));
<= virtual() (unstable))); _for_each_inner!((MEM2MEM5 <= virtual() (unstable))); _for_each_inner!((MEM2MEM4 <= virtual() (unstable))); _for_each_inner!((MEM2MEM5
_for_each_inner!((MEM2MEM10 <= virtual() (unstable))); <= virtual() (unstable))); _for_each_inner!((MEM2MEM10 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM11 <= virtual() (unstable))); _for_each_inner!((MEM2MEM11 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM12 <= virtual() (unstable))); _for_each_inner!((MEM2MEM12 <= virtual() (unstable)));
_for_each_inner!((MEM2MEM13 <= virtual() (unstable))); _for_each_inner!((MEM2MEM13 <= virtual() (unstable)));
@ -669,12 +669,12 @@ macro_rules! for_each_peripheral {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual() (unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual()
(unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)), (unstable)), (DMA_CH2 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)),
(BT <= virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (MEM2MEM1 (BT <= virtual() (unstable)), (FLASH <= virtual() (unstable)), (SW_INTERRUPT <=
<= virtual() (unstable)), (MEM2MEM4 <= virtual() (unstable)), (MEM2MEM5 <= virtual() (unstable)), (MEM2MEM1 <= virtual() (unstable)), (MEM2MEM4 <= virtual()
virtual() (unstable)), (MEM2MEM10 <= virtual() (unstable)), (MEM2MEM11 <= (unstable)), (MEM2MEM5 <= virtual() (unstable)), (MEM2MEM10 <= virtual()
virtual() (unstable)), (MEM2MEM12 <= virtual() (unstable)), (MEM2MEM13 <= (unstable)), (MEM2MEM11 <= virtual() (unstable)), (MEM2MEM12 <= virtual()
virtual() (unstable)), (MEM2MEM14 <= virtual() (unstable)), (MEM2MEM15 <= (unstable)), (MEM2MEM13 <= virtual() (unstable)), (MEM2MEM14 <= virtual()
virtual() (unstable)))); (unstable)), (MEM2MEM15 <= virtual() (unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

36
esp-metadata-generated/src/_generated_esp32s2.rs
View File

@ -657,21 +657,22 @@ macro_rules! for_each_peripheral {
(unstable))); _for_each_inner!((ADC1 <= virtual() (unstable))); (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((DAC1 <= _for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((DAC1 <=
virtual() (unstable))); _for_each_inner!((DAC2 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((DAC2 <= virtual() (unstable)));
_for_each_inner!((PSRAM <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT _for_each_inner!((FLASH <= virtual() (unstable))); _for_each_inner!((PSRAM <=
<= virtual() (unstable))); _for_each_inner!((ULP_RISCV_CORE <= virtual() virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable)));
(unstable))); _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), _for_each_inner!((ULP_RISCV_CORE <= virtual() (unstable)));
(GPIO2 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
(GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
(GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO26 <= virtual()), virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
(GPIO27 <= virtual()), (GPIO28 <= virtual()), (GPIO29 <= virtual()), (GPIO30 <= (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO26 <= virtual()), (GPIO27 <=
virtual()), (GPIO31 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), virtual()), (GPIO28 <= virtual()), (GPIO29 <= virtual()), (GPIO30 <= virtual()),
(GPIO34 <= virtual()), (GPIO35 <= virtual()), (GPIO36 <= virtual()), (GPIO37 <= (GPIO31 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), (GPIO34 <=
virtual()), (GPIO38 <= virtual()), (GPIO39 <= virtual()), (GPIO40 <= virtual()), virtual()), (GPIO35 <= virtual()), (GPIO36 <= virtual()), (GPIO37 <= virtual()),
(GPIO41 <= virtual()), (GPIO42 <= virtual()), (GPIO43 <= virtual()), (GPIO44 <= (GPIO38 <= virtual()), (GPIO39 <= virtual()), (GPIO40 <= virtual()), (GPIO41 <=
virtual()), (GPIO45 <= virtual()), (GPIO46 <= virtual()), (AES <= AES(AES : { virtual()), (GPIO42 <= virtual()), (GPIO43 <= virtual()), (GPIO44 <= virtual()),
(GPIO45 <= virtual()), (GPIO46 <= virtual()), (AES <= AES(AES : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (APB_SARADC <= APB_SARADC() (unstable)), (DEDICATED_GPIO <= (unstable)), (APB_SARADC <= APB_SARADC() (unstable)), (DEDICATED_GPIO <=
DEDICATED_GPIO() (unstable)), (DS <= DS() (unstable)), (EFUSE <= EFUSE() DEDICATED_GPIO() (unstable)), (DS <= DS() (unstable)), (EFUSE <= EFUSE()
@ -706,8 +707,9 @@ macro_rules! for_each_peripheral {
(DMA_SPI3 <= SPI3() (unstable)), (DMA_I2S0 <= I2S0() (unstable)), (DMA_CRYPTO <= (DMA_SPI3 <= SPI3() (unstable)), (DMA_I2S0 <= I2S0() (unstable)), (DMA_CRYPTO <=
CRYPTO_DMA() (unstable)), (DMA_COPY <= COPY_DMA() (unstable)), (ADC1 <= virtual() CRYPTO_DMA() (unstable)), (DMA_COPY <= COPY_DMA() (unstable)), (ADC1 <= virtual()
(unstable)), (ADC2 <= virtual() (unstable)), (DAC1 <= virtual() (unstable)), (unstable)), (ADC2 <= virtual() (unstable)), (DAC1 <= virtual() (unstable)),
(DAC2 <= virtual() (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <= (DAC2 <= virtual() (unstable)), (FLASH <= virtual() (unstable)), (PSRAM <=
virtual() (unstable)), (ULP_RISCV_CORE <= virtual() (unstable)))); virtual() (unstable)), (SW_INTERRUPT <= virtual() (unstable)), (ULP_RISCV_CORE <=
virtual() (unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

117
esp-metadata-generated/src/_generated_esp32s3.rs
View File

@ -668,65 +668,66 @@ macro_rules! for_each_peripheral {
_for_each_inner!((DMA_CH4 <= virtual() (unstable))); _for_each_inner!((ADC1 <= _for_each_inner!((DMA_CH4 <= virtual() (unstable))); _for_each_inner!((ADC1 <=
virtual() (unstable))); _for_each_inner!((ADC2 <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((ADC2 <= virtual() (unstable)));
_for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((CPU_CTRL <= _for_each_inner!((BT <= virtual() (unstable))); _for_each_inner!((CPU_CTRL <=
virtual() (unstable))); _for_each_inner!((PSRAM <= virtual() (unstable))); virtual() (unstable))); _for_each_inner!((FLASH <= virtual() (unstable)));
_for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((PSRAM <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT
_for_each_inner!((ULP_RISCV_CORE <= virtual() (unstable))); <= virtual() (unstable))); _for_each_inner!((ULP_RISCV_CORE <= virtual()
_for_each_inner!((WIFI <= virtual() (unstable))); _for_each_inner!((all(GPIO0 <= (unstable))); _for_each_inner!((WIFI <= virtual() (unstable)));
virtual()), (GPIO1 <= virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()), _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
(GPIO4 <= virtual()), (GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
virtual()), (GPIO8 <= virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
(GPIO11 <= virtual()), (GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
virtual()), (GPIO15 <= virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
(GPIO18 <= virtual()), (GPIO19 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
virtual()), (GPIO26 <= virtual()), (GPIO27 <= virtual()), (GPIO28 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO26 <= virtual()), (GPIO27 <=
(GPIO29 <= virtual()), (GPIO30 <= virtual()), (GPIO31 <= virtual()), (GPIO32 <= virtual()), (GPIO28 <= virtual()), (GPIO29 <= virtual()), (GPIO30 <= virtual()),
virtual()), (GPIO33 <= virtual()), (GPIO34 <= virtual()), (GPIO35 <= virtual()), (GPIO31 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), (GPIO34 <=
(GPIO36 <= virtual()), (GPIO37 <= virtual()), (GPIO38 <= virtual()), (GPIO39 <= virtual()), (GPIO35 <= virtual()), (GPIO36 <= virtual()), (GPIO37 <= virtual()),
virtual()), (GPIO40 <= virtual()), (GPIO41 <= virtual()), (GPIO42 <= virtual()), (GPIO38 <= virtual()), (GPIO39 <= virtual()), (GPIO40 <= virtual()), (GPIO41 <=
(GPIO43 <= virtual()), (GPIO44 <= virtual()), (GPIO45 <= virtual()), (GPIO46 <= virtual()), (GPIO42 <= virtual()), (GPIO43 <= virtual()), (GPIO44 <= virtual()),
virtual()), (GPIO47 <= virtual()), (GPIO48 <= virtual()), (AES <= AES(AES : { (GPIO45 <= virtual()), (GPIO46 <= virtual()), (GPIO47 <= virtual()), (GPIO48 <=
virtual()), (AES <= AES(AES : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (APB_CTRL <= APB_CTRL() (unstable)),
(APB_SARADC <= APB_SARADC() (unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG()
(unstable)), (DMA <= DMA() (unstable)), (DS <= DS() (unstable)), (EFUSE <=
EFUSE() (unstable)), (EXTMEM <= EXTMEM() (unstable)), (GPIO <= GPIO()
(unstable)), (GPIO_SD <= GPIO_SD() (unstable)), (HMAC <= HMAC() (unstable)),
(I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <= APB_SARADC() (unstable)), (I2S1 <= I2S1(I2S1 : { bind_peri_interrupt, enable_peri_interrupt,
(unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (DMA <= DMA() disable_peri_interrupt }) (unstable)), (INTERRUPT_CORE0 <= INTERRUPT_CORE0()
(unstable)), (DS <= DS() (unstable)), (EFUSE <= EFUSE() (unstable)), (EXTMEM <= (unstable)), (INTERRUPT_CORE1 <= INTERRUPT_CORE1() (unstable)), (IO_MUX <=
EXTMEM() (unstable)), (GPIO <= GPIO() (unstable)), (GPIO_SD <= GPIO_SD() IO_MUX() (unstable)), (LCD_CAM <= LCD_CAM() (unstable)), (LEDC <= LEDC()
(unstable)), (HMAC <= HMAC() (unstable)), (I2C0 <= I2C0(I2C_EXT0 : { (unstable)), (LPWR <= RTC_CNTL() (unstable)), (MCPWM0 <= MCPWM0() (unstable)),
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (I2C1 <= (MCPWM1 <= MCPWM1() (unstable)), (PCNT <= PCNT() (unstable)), (PERI_BACKUP <=
I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt, PERI_BACKUP() (unstable)), (RMT <= RMT() (unstable)), (RNG <= RNG() (unstable)),
disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : { bind_peri_interrupt, (RSA <= RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (I2S1 <= I2S1(I2S1 disable_peri_interrupt }) (unstable)), (RTC_CNTL <= RTC_CNTL() (unstable)),
: { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) (RTC_I2C <= RTC_I2C() (unstable)), (RTC_IO <= RTC_IO() (unstable)), (SDHOST <=
(unstable)), (INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (INTERRUPT_CORE1 SDHOST() (unstable)), (SENS <= SENS() (unstable)), (SENSITIVE <= SENSITIVE()
<= INTERRUPT_CORE1() (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LCD_CAM <= (unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
LCD_CAM() (unstable)), (LEDC <= LEDC() (unstable)), (LPWR <= RTC_CNTL() disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
(unstable)), (MCPWM0 <= MCPWM0() (unstable)), (MCPWM1 <= MCPWM1() (unstable)), SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
(PCNT <= PCNT() (unstable)), (PERI_BACKUP <= PERI_BACKUP() (unstable)), (RMT <= enable_peri_interrupt, disable_peri_interrupt })), (SPI3 <= SPI3(SPI3 : {
RMT() (unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) <= SYSTEM() (unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0()
(unstable)), (RTC_CNTL <= RTC_CNTL() (unstable)), (RTC_I2C <= RTC_I2C() (unstable)), (TIMG1 <= TIMG1() (unstable)), (TWAI0 <= TWAI0() (unstable)), (UART0
(unstable)), (RTC_IO <= RTC_IO() (unstable)), (SDHOST <= SDHOST() (unstable)), <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
(SENS <= SENS() (unstable)), (SENSITIVE <= SENSITIVE() (unstable)), (SHA <= disable_peri_interrupt })), (UART1 <= UART1(UART1 : { bind_peri_interrupt,
SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) enable_peri_interrupt, disable_peri_interrupt })), (UART2 <= UART2(UART2 : {
(unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <= bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UHCI0 <=
SPI2(SPI2 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt UHCI0() (unstable)), (USB0 <= USB0() (unstable)), (USB_DEVICE <=
})), (SPI3 <= SPI3(SPI3 : { bind_peri_interrupt, enable_peri_interrupt, USB_DEVICE(USB_DEVICE : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (SYSTEM <= SYSTEM() (unstable)), (SYSTIMER <= disable_peri_interrupt }) (unstable)), (USB_WRAP <= USB_WRAP() (unstable)), (WCL
SYSTIMER() (unstable)), (TIMG0 <= TIMG0() (unstable)), (TIMG1 <= TIMG1() <= WCL() (unstable)), (XTS_AES <= XTS_AES() (unstable)), (DMA_CH0 <= virtual()
(unstable)), (TWAI0 <= TWAI0() (unstable)), (UART0 <= UART0(UART0 : { (unstable)), (DMA_CH1 <= virtual() (unstable)), (DMA_CH2 <= virtual()
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UART1 <= (unstable)), (DMA_CH3 <= virtual() (unstable)), (DMA_CH4 <= virtual()
UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt, (unstable)), (ADC1 <= virtual() (unstable)), (ADC2 <= virtual() (unstable)), (BT
disable_peri_interrupt })), (UART2 <= UART2(UART2 : { bind_peri_interrupt, <= virtual() (unstable)), (CPU_CTRL <= virtual() (unstable)), (FLASH <= virtual()
enable_peri_interrupt, disable_peri_interrupt })), (UHCI0 <= UHCI0() (unstable)), (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <= virtual()
(USB0 <= USB0() (unstable)), (USB_DEVICE <= USB_DEVICE(USB_DEVICE : { (unstable)), (ULP_RISCV_CORE <= virtual() (unstable)), (WIFI <= virtual()
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt }) (unstable))));
(unstable)), (USB_WRAP <= USB_WRAP() (unstable)), (WCL <= WCL() (unstable)),
(XTS_AES <= XTS_AES() (unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <=
virtual() (unstable)), (DMA_CH2 <= virtual() (unstable)), (DMA_CH3 <= virtual()
(unstable)), (DMA_CH4 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)),
(ADC2 <= virtual() (unstable)), (BT <= virtual() (unstable)), (CPU_CTRL <=
virtual() (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <=
virtual() (unstable)), (ULP_RISCV_CORE <= virtual() (unstable)), (WIFI <=
virtual() (unstable))));
}; };
} }
/// This macro can be used to generate code for each `GPIOn` instance. /// This macro can be used to generate code for each `GPIOn` instance.

3
esp-metadata/devices/esp32.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -73,6 +73,7 @@ peripherals = [
{ name = "CPU_CTRL", virtual = true }, { name = "CPU_CTRL", virtual = true },
{ name = "DAC1", virtual = true }, { name = "DAC1", virtual = true },
{ name = "DAC2", virtual = true }, { name = "DAC2", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "PSRAM", virtual = true }, { name = "PSRAM", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "TOUCH", virtual = true }, { name = "TOUCH", virtual = true },

3
esp-metadata/devices/esp32c2.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -46,6 +46,7 @@ peripherals = [
{ name = "ADC1", virtual = true }, { name = "ADC1", virtual = true },
{ name = "BT", virtual = true }, { name = "BT", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "WIFI", virtual = true }, { name = "WIFI", virtual = true },
{ name = "MEM2MEM1", virtual = true }, { name = "MEM2MEM1", virtual = true },

3
esp-metadata/devices/esp32c3.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -61,6 +61,7 @@ peripherals = [
{ name = "ADC1", virtual = true }, { name = "ADC1", virtual = true },
{ name = "ADC2", virtual = true }, { name = "ADC2", virtual = true },
{ name = "BT", virtual = true }, { name = "BT", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "TSENS", virtual = true }, { name = "TSENS", virtual = true },
{ name = "WIFI", virtual = true }, { name = "WIFI", virtual = true },

3
esp-metadata/devices/esp32c6.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -89,6 +89,7 @@ peripherals = [
{ name = "ADC1", virtual = true }, { name = "ADC1", virtual = true },
{ name = "BT", virtual = true }, { name = "BT", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "LP_CORE", virtual = true }, { name = "LP_CORE", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "TSENS", virtual = true }, { name = "TSENS", virtual = true },

3
esp-metadata/devices/esp32h2.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -80,6 +80,7 @@ peripherals = [
{ name = "ADC1", virtual = true }, { name = "ADC1", virtual = true },
{ name = "BT", virtual = true }, { name = "BT", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "MEM2MEM1", virtual = true }, { name = "MEM2MEM1", virtual = true },
{ name = "MEM2MEM4", virtual = true }, { name = "MEM2MEM4", virtual = true },

2
esp-metadata/devices/esp32p4.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]

3
esp-metadata/devices/esp32s2.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -70,6 +70,7 @@ peripherals = [
{ name = "ADC2", virtual = true }, { name = "ADC2", virtual = true },
{ name = "DAC1", virtual = true }, { name = "DAC1", virtual = true },
{ name = "DAC2", virtual = true }, { name = "DAC2", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "PSRAM", virtual = true }, { name = "PSRAM", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "ULP_RISCV_CORE", virtual = true }, { name = "ULP_RISCV_CORE", virtual = true },

3
esp-metadata/devices/esp32s3.toml
View File

@ -2,7 +2,7 @@
# #
# Empty [`device.driver`] tables imply `partial` support status. # Empty [`device.driver`] tables imply `partial` support status.
# #
# If you modify a driver support status, run `cargo xtask update-chip-support-table` to # If you modify a driver support status, run `cargo xtask update-metadata` to
# update the table in the esp-hal README. # update the table in the esp-hal README.
[device] [device]
@ -77,6 +77,7 @@ peripherals = [
{ name = "ADC2", virtual = true }, { name = "ADC2", virtual = true },
{ name = "BT", virtual = true }, { name = "BT", virtual = true },
{ name = "CPU_CTRL", virtual = true }, { name = "CPU_CTRL", virtual = true },
{ name = "FLASH", virtual = true },
{ name = "PSRAM", virtual = true }, { name = "PSRAM", virtual = true },
{ name = "SW_INTERRUPT", virtual = true }, { name = "SW_INTERRUPT", virtual = true },
{ name = "ULP_RISCV_CORE", virtual = true }, { name = "ULP_RISCV_CORE", virtual = true },

3
esp-storage/CHANGELOG.md
View File

@ -11,11 +11,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- `defmt` feature and `FlashStorage`, `FlashStorageError` now implements `Defmt` (#4127) - `defmt` feature and `FlashStorage`, `FlashStorageError` now implements `Defmt` (#4127)
- `Drop` impl for `FlashStorage` (#4132) - `Drop` impl for `FlashStorage` (#4132)
- `FlashStorage::new()` now takes a `Flash` argument (#4173)
### Changed ### Changed
- `FlashStorage::new()` now panics when it's already being in use (#4132)
### Fixed ### Fixed

15
esp-storage/Cargo.toml
View File

@ -41,6 +41,7 @@ embedded-storage = "0.3.1"
procmacros = { version = "0.19.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" } procmacros = { version = "0.19.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
cfg-if = "1.0.0" cfg-if = "1.0.0"
portable-atomic = { version = "1.11.0", default-features = false } portable-atomic = { version = "1.11.0", default-features = false }
esp-hal = { version = "1.0.0-rc.0", path = "../esp-hal", default-features = false, optional = true}
# Optional dependencies # Optional dependencies
esp-sync = { version = "0.0.0", path = "../esp-sync", optional = true } esp-sync = { version = "0.0.0", path = "../esp-sync", optional = true }
@ -75,18 +76,18 @@ defmt = ["dep:defmt"]
#! One of the following features must be enabled to select the target chip: #! One of the following features must be enabled to select the target chip:
## ##
esp32c2 = ["esp-rom-sys/esp32c2", "esp-sync/esp32c2"] esp32c2 = ["esp-hal/esp32c2", "esp-hal/unstable", "esp-rom-sys/esp32c2", "esp-sync/esp32c2"]
## ##
esp32c3 = ["esp-rom-sys/esp32c3", "esp-sync/esp32c3"] esp32c3 = ["esp-hal/esp32c3", "esp-hal/unstable", "esp-rom-sys/esp32c3", "esp-sync/esp32c3"]
## ##
esp32c6 = ["esp-rom-sys/esp32c6", "esp-sync/esp32c6"] esp32c6 = ["esp-hal/esp32c6", "esp-hal/unstable", "esp-rom-sys/esp32c6", "esp-sync/esp32c6"]
## ##
esp32h2 = ["esp-rom-sys/esp32h2", "esp-sync/esp32h2"] esp32h2 = ["esp-hal/esp32h2", "esp-hal/unstable", "esp-rom-sys/esp32h2", "esp-sync/esp32h2"]
## ##
esp32 = ["esp-rom-sys/esp32", "esp-sync/esp32", "xtensa-lx"] esp32 = ["esp-hal/esp32", "esp-hal/unstable", "esp-rom-sys/esp32", "esp-sync/esp32", "xtensa-lx"]
## ##
esp32s2 = ["esp-rom-sys/esp32s2", "esp-sync/esp32s2"] esp32s2 = ["esp-hal/esp32s2", "esp-hal/unstable", "esp-rom-sys/esp32s2", "esp-sync/esp32s2"]
## ##
esp32s3 = ["esp-rom-sys/esp32s3", "esp-sync/esp32s3", "xtensa-lx"] esp32s3 = ["esp-hal/esp32s3", "esp-hal/unstable", "esp-rom-sys/esp32s3", "esp-sync/esp32s3", "xtensa-lx"]
## Used for testing on a host. ## Used for testing on a host.
emulation = [] emulation = []

79
esp-storage/src/common.rs
View File

@ -1,16 +1,12 @@
use core::{ use core::mem::MaybeUninit;
mem::MaybeUninit,
sync::atomic::Ordering::{Acquire, Release},
};
use portable_atomic::AtomicBool; #[cfg(not(feature = "emulation"))]
pub use esp_hal::peripherals::FLASH as Flash;
use crate::chip_specific; use crate::chip_specific;
#[cfg(multi_core)] #[cfg(multi_core)]
use crate::multi_core::MultiCoreStrategy; use crate::multi_core::MultiCoreStrategy;
static IS_TAKEN: AtomicBool = AtomicBool::new(false);
#[derive(Clone, Copy, Debug, Eq, PartialEq)] #[derive(Clone, Copy, Debug, Eq, PartialEq)]
#[non_exhaustive] #[non_exhaustive]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -47,23 +43,33 @@ pub fn check_rc(rc: i32) -> Result<(), FlashStorageError> {
} }
} }
#[cfg(feature = "emulation")]
#[derive(Debug)]
pub struct Flash<'d> {
_phantom: core::marker::PhantomData<&'d ()>,
}
#[cfg(feature = "emulation")]
impl<'d> Flash<'d> {
pub fn new() -> Self {
Flash {
_phantom: core::marker::PhantomData,
}
}
}
#[derive(Debug)] #[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
/// Flash storage abstraction. /// Flash storage abstraction.
pub struct FlashStorage { pub struct FlashStorage<'d> {
pub(crate) capacity: usize, pub(crate) capacity: usize,
unlocked: bool, unlocked: bool,
#[cfg(multi_core)] #[cfg(multi_core)]
pub(crate) multi_core_strategy: MultiCoreStrategy, pub(crate) multi_core_strategy: MultiCoreStrategy,
_flash: Flash<'d>,
} }
impl Default for FlashStorage { impl<'d> FlashStorage<'d> {
fn default() -> Self {
Self::new()
}
}
impl FlashStorage {
/// Flash word size in bytes. /// Flash word size in bytes.
pub const WORD_SIZE: u32 = 4; pub const WORD_SIZE: u32 = 4;
/// Flash sector size in bytes. /// Flash sector size in bytes.
@ -74,11 +80,7 @@ impl FlashStorage {
/// # Panics /// # Panics
/// ///
/// Panics if called more than once. /// Panics if called more than once.
pub fn new() -> Self { pub fn new(flash: Flash<'d>) -> Self {
if IS_TAKEN.fetch_or(true, Acquire) {
panic!("FlashStorage::new() called more than once!");
}
#[cfg(not(any(feature = "esp32", feature = "esp32s2")))] #[cfg(not(any(feature = "esp32", feature = "esp32s2")))]
const ADDR: u32 = 0x0000; const ADDR: u32 = 0x0000;
#[cfg(any(feature = "esp32", feature = "esp32s2"))] #[cfg(any(feature = "esp32", feature = "esp32s2"))]
@ -89,6 +91,7 @@ impl FlashStorage {
unlocked: false, unlocked: false,
#[cfg(multi_core)] #[cfg(multi_core)]
multi_core_strategy: MultiCoreStrategy::Error, multi_core_strategy: MultiCoreStrategy::Error,
_flash: flash,
}; };
let mut buffer = crate::buffer::FlashWordBuffer::uninit(); let mut buffer = crate::buffer::FlashWordBuffer::uninit();
@ -188,39 +191,3 @@ impl FlashStorage {
Ok(()) Ok(())
} }
} }
impl Drop for FlashStorage {
fn drop(&mut self) {
IS_TAKEN.store(false, Release);
}
}
#[cfg(test)]
mod tests {
use crate::FlashStorage;
#[test]
fn test_singleton_behavior() {
// First call should succeed
let flash1 = FlashStorage::new();
assert_eq!(flash1.capacity > 0, true); // or check some field
// Second call should panic
let result = std::panic::catch_unwind(|| {
FlashStorage::new();
});
assert!(result.is_err(), "expected panic on second init");
// Third call should also panic
let result = std::panic::catch_unwind(|| {
FlashStorage::new();
});
assert!(result.is_err(), "expected panic on third init");
}
#[test]
#[should_panic(expected = "FlashStorage::new() called more than once!")]
fn test_expect_panics() {
let _flash1 = FlashStorage::new(); // first call is fine
let _flash2 = FlashStorage::new(); // this panics
}
}

6
esp-storage/src/multi_core.rs
View File

@ -38,10 +38,10 @@ pub(crate) enum MultiCoreStrategy {
Ignore, Ignore,
} }
impl FlashStorage { impl<'d> FlashStorage<'d> {
/// Enable auto parking of the second core before writing to flash /// Enable auto parking of the second core before writing to flash
/// The other core will be automatically un-parked when the write is complete /// The other core will be automatically un-parked when the write is complete
pub fn multicore_auto_park(mut self) -> FlashStorage { pub fn multicore_auto_park(mut self) -> FlashStorage<'d> {
self.multi_core_strategy = MultiCoreStrategy::AutoPark; self.multi_core_strategy = MultiCoreStrategy::AutoPark;
self self
} }
@ -51,7 +51,7 @@ impl FlashStorage {
/// # Safety /// # Safety
/// Only enable this if you are sure that the second core is not fetching instructions from the /// Only enable this if you are sure that the second core is not fetching instructions from the
/// flash during the write /// flash during the write
pub unsafe fn multicore_ignore(mut self) -> FlashStorage { pub unsafe fn multicore_ignore(mut self) -> FlashStorage<'d> {
self.multi_core_strategy = MultiCoreStrategy::Ignore; self.multi_core_strategy = MultiCoreStrategy::Ignore;
self self
} }

32
esp-storage/src/nor_flash.rs
View File

@ -15,7 +15,7 @@ use crate::{
buffer::{FlashSectorBuffer, uninit_slice, uninit_slice_mut}, buffer::{FlashSectorBuffer, uninit_slice, uninit_slice_mut},
}; };
impl FlashStorage { impl FlashStorage<'_> {
#[inline(always)] #[inline(always)]
fn is_word_aligned(bytes: &[u8]) -> bool { fn is_word_aligned(bytes: &[u8]) -> bool {
// TODO: Use is_aligned_to when stabilized (see `pointer_is_aligned`) // TODO: Use is_aligned_to when stabilized (see `pointer_is_aligned`)
@ -33,11 +33,11 @@ impl NorFlashError for FlashStorageError {
} }
} }
impl ErrorType for FlashStorage { impl ErrorType for FlashStorage<'_> {
type Error = FlashStorageError; type Error = FlashStorageError;
} }
impl ReadNorFlash for FlashStorage { impl ReadNorFlash for FlashStorage<'_> {
#[cfg(not(feature = "bytewise-read"))] #[cfg(not(feature = "bytewise-read"))]
const READ_SIZE: usize = Self::WORD_SIZE as _; const READ_SIZE: usize = Self::WORD_SIZE as _;
@ -45,7 +45,8 @@ impl ReadNorFlash for FlashStorage {
const READ_SIZE: usize = 1; const READ_SIZE: usize = 1;
fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> { fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
self.check_alignment::<{ Self::READ_SIZE as _ }>(offset, bytes.len())?; const RS: u32 = FlashStorage::READ_SIZE as u32;
self.check_alignment::<{ RS }>(offset, bytes.len())?;
self.check_bounds(offset, bytes.len())?; self.check_bounds(offset, bytes.len())?;
#[cfg(feature = "bytewise-read")] #[cfg(feature = "bytewise-read")]
@ -135,12 +136,13 @@ impl ReadNorFlash for FlashStorage {
} }
} }
impl NorFlash for FlashStorage { impl NorFlash for FlashStorage<'_> {
const WRITE_SIZE: usize = Self::WORD_SIZE as _; const WRITE_SIZE: usize = Self::WORD_SIZE as _;
const ERASE_SIZE: usize = Self::SECTOR_SIZE as _; const ERASE_SIZE: usize = Self::SECTOR_SIZE as _;
fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> { fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
self.check_alignment::<{ Self::WORD_SIZE }>(offset, bytes.len())?; const WS: u32 = FlashStorage::WORD_SIZE;
self.check_alignment::<{ WS }>(offset, bytes.len())?;
self.check_bounds(offset, bytes.len())?; self.check_bounds(offset, bytes.len())?;
if Self::is_word_aligned(bytes) { if Self::is_word_aligned(bytes) {
@ -174,7 +176,8 @@ impl NorFlash for FlashStorage {
fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> { fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
let len = (to - from) as _; let len = (to - from) as _;
self.check_alignment::<{ Self::SECTOR_SIZE }>(from, len)?; const SZ: u32 = FlashStorage::SECTOR_SIZE;
self.check_alignment::<{ SZ }>(from, len)?;
self.check_bounds(from, len)?; self.check_bounds(from, len)?;
for sector in from / Self::SECTOR_SIZE..to / Self::SECTOR_SIZE { for sector in from / Self::SECTOR_SIZE..to / Self::SECTOR_SIZE {
@ -185,12 +188,13 @@ impl NorFlash for FlashStorage {
} }
} }
impl MultiwriteNorFlash for FlashStorage {} impl MultiwriteNorFlash for FlashStorage<'_> {}
// Run the tests with `--test-threads=1` - the emulation is not multithread safe // Run the tests with `--test-threads=1` - the emulation is not multithread safe
#[cfg(test)] #[cfg(test)]
mod tests { mod tests {
use super::*; use super::*;
use crate::common::Flash;
const WORD_SIZE: u32 = 4; const WORD_SIZE: u32 = 4;
const SECTOR_SIZE: u32 = 4 << 10; const SECTOR_SIZE: u32 = 4 << 10;
@ -264,7 +268,7 @@ mod tests {
#[test] #[test]
#[cfg(not(feature = "bytewise-read"))] #[cfg(not(feature = "bytewise-read"))]
fn aligned_read() { fn aligned_read() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let src = TestBuffer::seq(); let src = TestBuffer::seq();
let mut data = TestBuffer::default(); let mut data = TestBuffer::default();
@ -284,7 +288,7 @@ mod tests {
#[test] #[test]
#[cfg(not(feature = "bytewise-read"))] #[cfg(not(feature = "bytewise-read"))]
fn not_aligned_read_aligned_buffer() { fn not_aligned_read_aligned_buffer() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let mut data = TestBuffer::default(); let mut data = TestBuffer::default();
@ -296,7 +300,7 @@ mod tests {
#[test] #[test]
#[cfg(not(feature = "bytewise-read"))] #[cfg(not(feature = "bytewise-read"))]
fn aligned_read_not_aligned_buffer() { fn aligned_read_not_aligned_buffer() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let src = TestBuffer::seq(); let src = TestBuffer::seq();
let mut data = TestBuffer::default(); let mut data = TestBuffer::default();
@ -318,7 +322,7 @@ mod tests {
#[test] #[test]
#[cfg(feature = "bytewise-read")] #[cfg(feature = "bytewise-read")]
fn bytewise_read_aligned_buffer() { fn bytewise_read_aligned_buffer() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let src = TestBuffer::seq(); let src = TestBuffer::seq();
@ -339,7 +343,7 @@ mod tests {
#[test] #[test]
#[cfg(feature = "bytewise-read")] #[cfg(feature = "bytewise-read")]
fn bytewise_read_not_aligned_buffer() { fn bytewise_read_not_aligned_buffer() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let src = TestBuffer::seq(); let src = TestBuffer::seq();
@ -361,7 +365,7 @@ mod tests {
#[test] #[test]
fn write_not_aligned_buffer() { fn write_not_aligned_buffer() {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(Flash::new());
flash.capacity = 4 * 4096; flash.capacity = 4 * 4096;
let mut read_data = TestBuffer::default(); let mut read_data = TestBuffer::default();
let write_data = TestBuffer::seq(); let write_data = TestBuffer::seq();

4
esp-storage/src/storage.rs
View File

@ -2,7 +2,7 @@ use embedded_storage::{ReadStorage, Storage};
use crate::{FlashStorage, FlashStorageError, buffer::FlashSectorBuffer}; use crate::{FlashStorage, FlashStorageError, buffer::FlashSectorBuffer};
impl ReadStorage for FlashStorage { impl ReadStorage for FlashStorage<'_> {
type Error = FlashStorageError; type Error = FlashStorageError;
fn read(&mut self, offset: u32, mut bytes: &mut [u8]) -> Result<(), Self::Error> { fn read(&mut self, offset: u32, mut bytes: &mut [u8]) -> Result<(), Self::Error> {
@ -44,7 +44,7 @@ impl ReadStorage for FlashStorage {
} }
} }
impl Storage for FlashStorage { impl Storage for FlashStorage<'_> {
fn write(&mut self, offset: u32, mut bytes: &[u8]) -> Result<(), Self::Error> { fn write(&mut self, offset: u32, mut bytes: &[u8]) -> Result<(), Self::Error> {
self.check_bounds(offset, bytes.len())?; self.check_bounds(offset, bytes.len())?;

2
examples/ota/update/src/main.rs
View File

@ -52,7 +52,7 @@ fn main() -> ! {
esp_println::logger::init_logger_from_env(); esp_println::logger::init_logger_from_env();
let peripherals = esp_hal::init(esp_hal::Config::default()); let peripherals = esp_hal::init(esp_hal::Config::default());
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(peripherals.FLASH);
let mut buffer = [0u8; esp_bootloader_esp_idf::partitions::PARTITION_TABLE_MAX_LEN]; let mut buffer = [0u8; esp_bootloader_esp_idf::partitions::PARTITION_TABLE_MAX_LEN];
let pt = let pt =

4
examples/peripheral/flash_read_write/src/main.rs
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@ -17,9 +17,9 @@ esp_bootloader_esp_idf::esp_app_desc!();
#[main] #[main]
fn main() -> ! { fn main() -> ! {
esp_println::logger::init_logger_from_env(); esp_println::logger::init_logger_from_env();
let _ = esp_hal::init(esp_hal::Config::default()); let peripherals = esp_hal::init(esp_hal::Config::default());
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(peripherals.FLASH);
println!("Flash size = {}", flash.capacity()); println!("Flash size = {}", flash.capacity());
let mut pt_mem = [0u8; partitions::PARTITION_TABLE_MAX_LEN]; let mut pt_mem = [0u8; partitions::PARTITION_TABLE_MAX_LEN];

13
hil-test/src/bin/alloc_psram.rs
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@ -27,12 +27,19 @@ mod tests {
use embedded_storage::*; use embedded_storage::*;
use esp_alloc::{AnyMemory, ExternalMemory, InternalMemory}; use esp_alloc::{AnyMemory, ExternalMemory, InternalMemory};
use esp_bootloader_esp_idf::partitions; use esp_bootloader_esp_idf::partitions;
use esp_hal::peripherals::FLASH;
use esp_storage::FlashStorage; use esp_storage::FlashStorage;
struct Context<'a> {
flash: FLASH<'a>,
}
#[init] #[init]
fn init() { fn init() -> Context<'static> {
let p = esp_hal::init(esp_hal::Config::default()); let p = esp_hal::init(esp_hal::Config::default());
esp_alloc::psram_allocator!(p.PSRAM, esp_hal::psram); esp_alloc::psram_allocator!(p.PSRAM, esp_hal::psram);
Context { flash: p.FLASH }
} }
// alloc::vec::Vec tests // alloc::vec::Vec tests
@ -146,8 +153,8 @@ mod tests {
} }
#[test] #[test]
fn test_with_accessing_flash_storage() { fn test_with_accessing_flash_storage(ctx: Context<'static>) {
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(ctx.flash);
let mut pt_mem = [0u8; partitions::PARTITION_TABLE_MAX_LEN]; let mut pt_mem = [0u8; partitions::PARTITION_TABLE_MAX_LEN];
let pt = partitions::read_partition_table(&mut flash, &mut pt_mem).unwrap(); let pt = partitions::read_partition_table(&mut flash, &mut pt_mem).unwrap();

4
hil-test/src/bin/storage_read_app_desc.rs
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@ -18,11 +18,11 @@ mod tests {
#[test] #[test]
fn test_can_read_app_desc() { fn test_can_read_app_desc() {
let _ = esp_hal::init(esp_hal::Config::default()); let peripherals = esp_hal::init(esp_hal::Config::default());
let mut bytes = [0u8; 256]; let mut bytes = [0u8; 256];
let mut flash = FlashStorage::new(); let mut flash = FlashStorage::new(peripherals.FLASH);
// esp-idf 2nd stage bootloader would expect the app-descriptor at the start of // esp-idf 2nd stage bootloader would expect the app-descriptor at the start of
// DROM it also expects DROM segment to the the first page of the // DROM it also expects DROM segment to the the first page of the