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Fix insertion location of trap section in ram (#605)

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* Fix insertion location of trap section in ram

* Apply fixes for db and mcuboot

* Add changelog
This commit is contained in:
Scott Mabin 2023-06-23 12:00:16 +01:00 committed by GitHub
parent 5af8b6387a
commit 087bfa570b
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GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 14 additions and 14 deletions
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2
CHANGELOG.md
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@ -51,7 +51,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Fixed CI by pinning the log crate to 0.4.18 (#600)
- ESP32-S3: Fix calculation of PSRAM start address
- Fixed wrong variable access (FOSC CLK calibration for ESP32-C6 #593)
- Fixed [trap location in ram](https://github.com/esp-rs/esp-hal/pull/605#issuecomment-1604039683) (#605)
### Changed
- Improve examples documentation (#533)

2
esp32c2-hal/ld/bl-riscv-link.x
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@ -67,7 +67,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;
SECTIONS {
/**

4
esp32c2-hal/ld/db-riscv-link.x
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@ -89,10 +89,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;

2
esp32c3-hal/ld/bl-riscv-link.x
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@ -67,7 +67,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;
SECTIONS {
/**

4
esp32c3-hal/ld/db-riscv-link.x
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@ -89,10 +89,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;

2
esp32c3-hal/ld/mb-riscv-link.x
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@ -64,9 +64,9 @@ SECTIONS
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
. = ALIGN(4);
*libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);

2
esp32c6-hal/ld/bl-riscv-link.x
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@ -71,7 +71,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;
SECTIONS {
/**

4
esp32c6-hal/ld/db-riscv-link.x
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@ -94,10 +94,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;

2
esp32h2-hal/ld/bl-riscv-link.x
View File

@ -65,7 +65,7 @@ SECTIONS {
*(.trap.*);
} > RWTEXT
}
INSERT AFTER .rwtext;
INSERT BEFORE .rwtext;
SECTIONS {
/**

4
esp32h2-hal/ld/db-riscv-link.x
View File

@ -94,10 +94,10 @@ SECTIONS
_data_size = _data_end - _data_start + 8;
.rwtext ORIGIN(REGION_RWTEXT) + _data_size : AT(_text_size + _rodata_size + _data_size){
_srwtext = .;
*(.rwtext);
. = ALIGN(4);
KEEP(*(.trap));
*(.trap.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT
_rwtext_size = _erwtext - _srwtext + 8;