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Move SHA algos to metadata (#3844)

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Dániel Buga 2025-07-21 21:47:33 +02:00 committed by GitHub
parent fd66bd3dcc
commit 0c1cc17ed1
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GPG Key ID: B5690EEEBB952194
11 changed files with 136 additions and 16 deletions
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15
esp-hal/src/sha.rs
View File

@ -611,20 +611,21 @@ macro_rules! impl_sha {
// Two working modes
// – Typical SHA
// – DMA-SHA (not implemented yet)
//
// TODO: Allow/Implement SHA512_(u16)
#[cfg(sha_algo_sha_1)]
impl_sha!(Sha1, 0, 20, 64);
#[cfg(not(esp32))]
#[cfg(sha_algo_sha_224)]
impl_sha!(Sha224, 1, 28, 64);
#[cfg(sha_algo_sha_256)]
impl_sha!(Sha256, 2, 32, 64);
#[cfg(any(esp32, esp32s2, esp32s3))]
#[cfg(sha_algo_sha_384)]
impl_sha!(Sha384, 3, 48, 128);
#[cfg(any(esp32, esp32s2, esp32s3))]
#[cfg(sha_algo_sha_512)]
impl_sha!(Sha512, 4, 64, 128);
#[cfg(any(esp32s2, esp32s3))]
#[cfg(sha_algo_sha_512_224)]
impl_sha!(Sha512_224, 5, 28, 128);
#[cfg(any(esp32s2, esp32s3))]
#[cfg(sha_algo_sha_512_256)]
impl_sha!(Sha512_256, 6, 32, 128);
// TODO: Allow/Implement SHA512_(u16)
fn h_mem(sha: &crate::peripherals::SHA<'_>, index: usize) -> *mut u32 {
let sha = sha.register_block();

72
esp-metadata-generated/src/_build_script_utils.rs
View File

@ -281,6 +281,10 @@ impl Chip {
"rmt_ram_start=\"1073047552\"",
"rmt_channel_ram_size=\"64\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_256",
"sha_algo_sha_384",
"sha_algo_sha_512",
"timergroup_timg_has_timer1",
"uart_ram_size=\"128\"",
"has_dram_region",
@ -427,6 +431,10 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1073047552\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"64\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=sha_algo_sha_384",
"cargo:rustc-cfg=sha_algo_sha_512",
"cargo:rustc-cfg=timergroup_timg_has_timer1",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
"cargo:rustc-cfg=has_dram_region",
@ -537,6 +545,9 @@ impl Chip {
"i2c_master_fifo_size=\"16\"",
"interrupts_status_registers=\"2\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"timergroup_timg_has_divcnt_rst",
"uart_ram_size=\"128\"",
"has_dram_region",
@ -643,6 +654,9 @@ impl Chip {
"cargo:rustc-cfg=i2c_master_fifo_size=\"16\"",
"cargo:rustc-cfg=interrupts_status_registers=\"2\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=timergroup_timg_has_divcnt_rst",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
"cargo:rustc-cfg=has_dram_region",
@ -782,6 +796,9 @@ impl Chip {
"rmt_ram_start=\"1610703872\"",
"rmt_channel_ram_size=\"48\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"timergroup_timg_has_divcnt_rst",
"uart_ram_size=\"128\"",
"has_dram_region",
@ -917,6 +934,9 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1610703872\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"48\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=timergroup_timg_has_divcnt_rst",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
"cargo:rustc-cfg=has_dram_region",
@ -1110,6 +1130,9 @@ impl Chip {
"rmt_ram_start=\"1610638336\"",
"rmt_channel_ram_size=\"48\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"timergroup_timg_has_divcnt_rst",
"uart_ram_size=\"128\"",
"lp_uart_ram_size=\"32\"",
@ -1301,6 +1324,9 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1610638336\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"48\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=timergroup_timg_has_divcnt_rst",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
"cargo:rustc-cfg=lp_uart_ram_size=\"32\"",
@ -1472,6 +1498,9 @@ impl Chip {
"rmt_ram_start=\"1610642432\"",
"rmt_channel_ram_size=\"48\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"timergroup_timg_has_divcnt_rst",
"uart_ram_size=\"128\"",
"has_dram_region",
@ -1637,6 +1666,9 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1610642432\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"48\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=timergroup_timg_has_divcnt_rst",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
"cargo:rustc-cfg=has_dram_region",
@ -1795,6 +1827,14 @@ impl Chip {
"rmt_ram_start=\"1061250048\"",
"rmt_channel_ram_size=\"64\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"sha_algo_sha_384",
"sha_algo_sha_512",
"sha_algo_sha_512_224",
"sha_algo_sha_512_256",
"sha_algo_sha_512_t",
"spi_master_has_octal",
"timergroup_timg_has_timer1",
"uart_ram_size=\"128\"",
@ -1950,6 +1990,14 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1061250048\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"64\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=sha_algo_sha_384",
"cargo:rustc-cfg=sha_algo_sha_512",
"cargo:rustc-cfg=sha_algo_sha_512_224",
"cargo:rustc-cfg=sha_algo_sha_512_256",
"cargo:rustc-cfg=sha_algo_sha_512_t",
"cargo:rustc-cfg=spi_master_has_octal",
"cargo:rustc-cfg=timergroup_timg_has_timer1",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
@ -2127,6 +2175,14 @@ impl Chip {
"rmt_ram_start=\"1610704896\"",
"rmt_channel_ram_size=\"48\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
"sha_algo_sha_384",
"sha_algo_sha_512",
"sha_algo_sha_512_224",
"sha_algo_sha_512_256",
"sha_algo_sha_512_t",
"spi_master_has_octal",
"timergroup_timg_has_timer1",
"uart_ram_size=\"128\"",
@ -2300,6 +2356,14 @@ impl Chip {
"cargo:rustc-cfg=rmt_ram_start=\"1610704896\"",
"cargo:rustc-cfg=rmt_channel_ram_size=\"48\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
"cargo:rustc-cfg=sha_algo_sha_384",
"cargo:rustc-cfg=sha_algo_sha_512",
"cargo:rustc-cfg=sha_algo_sha_512_224",
"cargo:rustc-cfg=sha_algo_sha_512_256",
"cargo:rustc-cfg=sha_algo_sha_512_t",
"cargo:rustc-cfg=spi_master_has_octal",
"cargo:rustc-cfg=timergroup_timg_has_timer1",
"cargo:rustc-cfg=uart_ram_size=\"128\"",
@ -2444,6 +2508,10 @@ impl Config {
println!("cargo:rustc-check-cfg=cfg(gpio_has_bank_1)");
println!("cargo:rustc-check-cfg=cfg(gpio_remap_iomux_pin_registers)");
println!("cargo:rustc-check-cfg=cfg(i2c_master_separate_filter_config_registers)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_1)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_256)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_384)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_512)");
println!("cargo:rustc-check-cfg=cfg(timergroup_timg_has_timer1)");
println!("cargo:rustc-check-cfg=cfg(esp32c2)");
println!("cargo:rustc-check-cfg=cfg(riscv)");
@ -2487,6 +2555,7 @@ impl Config {
println!("cargo:rustc-check-cfg=cfg(i2c_master_has_arbitration_en)");
println!("cargo:rustc-check-cfg=cfg(i2c_master_has_tx_fifo_watermark)");
println!("cargo:rustc-check-cfg=cfg(i2c_master_bus_timeout_is_exponential)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_224)");
println!("cargo:rustc-check-cfg=cfg(timergroup_timg_has_divcnt_rst)");
println!("cargo:rustc-check-cfg=cfg(esp32c3)");
println!("cargo:rustc-check-cfg=cfg(soc_has_ds)");
@ -2576,6 +2645,9 @@ impl Config {
println!("cargo:rustc-check-cfg=cfg(riscv_coproc_supported)");
println!("cargo:rustc-check-cfg=cfg(usb_otg)");
println!("cargo:rustc-check-cfg=cfg(aes_dma_mode_gcm)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_512_224)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_512_256)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_512_t)");
println!("cargo:rustc-check-cfg=cfg(spi_master_has_octal)");
println!("cargo:rustc-check-cfg=cfg(esp32s3)");
println!("cargo:rustc-check-cfg=cfg(soc_has_interrupt_core1)");

5
esp-metadata/devices/esp32.toml
View File

@ -587,6 +587,10 @@ support_status = "partial"
ram_start = 0x3ff56800
channel_ram_size = 64
[device.sha]
support_status = "partial"
algo = ["SHA-1", "SHA-256", "SHA-384", "SHA-512"]
[device.spi_master]
support_status = "supported"
instances = [
@ -632,7 +636,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.rsa]
[device.sha]
## Interfaces
[device.i2s]

5
esp-metadata/devices/esp32c2.toml
View File

@ -244,6 +244,10 @@ bus_timeout_is_exponential = true
support_status = "partial"
status_registers = 2
[device.sha]
support_status = "partial"
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]
support_status = "supported"
instances = [
@ -278,7 +282,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
# [device.aes] Product portfolio lists AES, but TRM only has XTS_AES?
[device.ecc]
[device.sha]
## Interfaces
[device.ledc]

5
esp-metadata/devices/esp32c3.toml
View File

@ -296,6 +296,10 @@ support_status = "partial"
ram_start = 0x60016400
channel_ram_size = 48
[device.sha]
support_status = "partial"
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]
support_status = "supported"
instances = [
@ -332,7 +336,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.rsa]
[device.sha]
[device.hmac]
## Interfaces

5
esp-metadata/devices/esp32c6.toml
View File

@ -451,6 +451,10 @@ support_status = "partial"
ram_start = 0x60006400
channel_ram_size = 48
[device.sha]
support_status = "partial"
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]
support_status = "supported"
instances = [
@ -496,7 +500,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.ecc]
[device.rsa]
[device.sha]
[device.hmac]
## Interfaces

5
esp-metadata/devices/esp32h2.toml
View File

@ -368,6 +368,10 @@ support_status = "partial"
ram_start = 0x60007400
channel_ram_size = 48
[device.sha]
support_status = "partial"
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]
support_status = "supported"
instances = [
@ -405,7 +409,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.ecc]
[device.rsa]
[device.sha]
[device.hmac]
## Interfaces

14
esp-metadata/devices/esp32s2.toml
View File

@ -411,6 +411,19 @@ support_status = "partial"
ram_start = 0x3f416400
channel_ram_size = 64
[device.sha]
support_status = "partial"
algo = [
"SHA-1",
"SHA-224",
"SHA-256",
"SHA-384",
"SHA-512",
"SHA-512/224",
"SHA-512/256",
"SHA-512/t",
]
[device.spi_master]
support_status = "supported"
has_octal = true
@ -461,7 +474,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.rsa]
[device.hmac]
[device.sha]
## Interfaces
[device.i2s]

14
esp-metadata/devices/esp32s3.toml
View File

@ -586,6 +586,19 @@ support_status = "partial"
ram_start = 0x60016800
channel_ram_size = 48
[device.sha]
support_status = "partial"
algo = [
"SHA-1",
"SHA-224",
"SHA-256",
"SHA-384",
"SHA-512",
"SHA-512/224",
"SHA-512/256",
"SHA-512/t",
]
[device.spi_master]
support_status = "supported"
has_octal = true
@ -631,7 +644,6 @@ apb_cycle_wait_num = 16 # TODO
## Crypto
[device.rsa]
[device.hmac]
[device.sha]
## Interfaces
[device.i2s]

5
esp-metadata/src/cfg.rs
View File

@ -463,7 +463,10 @@ driver_configs![
ShaProperties {
driver: sha,
name: "SHA",
properties: {}
properties: {
#[serde(default)]
algo: Vec<String>,
}
},
SpiMasterProperties<SpiMasterInstanceConfig> {
driver: spi_master,

7
esp-metadata/src/lib.rs
View File

@ -413,7 +413,12 @@ impl Config {
Value::StringList(values) => Some(
values
.iter()
.map(|val| format!("{name}_{}", val.to_lowercase()))
.map(|val| {
format!(
"{name}_{}",
val.to_lowercase().replace("-", "_").replace("/", "_")
)
})
.collect(),
),
Value::Number(value) => Some(vec![format!("{name}=\"{value}\"")]),