mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-30 13:50:38 +00:00
discard interrupt symbols from lto so that lto doesn't end up rebinding them (#1327)
This commit is contained in:
Scott Mabin
GitHub
parent
0cb5e4e82d
commit
25f509ce74
@ -1,35 +1,35 @@
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PROVIDE(DefaultHandler = EspDefaultHandler);
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PROVIDE(cpu_int_1_handler = DefaultHandler);
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PROVIDE(cpu_int_2_handler = DefaultHandler);
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PROVIDE(cpu_int_3_handler = DefaultHandler);
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PROVIDE(cpu_int_4_handler = DefaultHandler);
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PROVIDE(cpu_int_5_handler = DefaultHandler);
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PROVIDE(cpu_int_6_handler = DefaultHandler);
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PROVIDE(cpu_int_7_handler = DefaultHandler);
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PROVIDE(cpu_int_8_handler = DefaultHandler);
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PROVIDE(cpu_int_9_handler = DefaultHandler);
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PROVIDE(cpu_int_10_handler = DefaultHandler);
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PROVIDE(cpu_int_11_handler = DefaultHandler);
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PROVIDE(cpu_int_12_handler = DefaultHandler);
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PROVIDE(cpu_int_13_handler = DefaultHandler);
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PROVIDE(cpu_int_14_handler = DefaultHandler);
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PROVIDE(cpu_int_15_handler = DefaultHandler);
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PROVIDE(cpu_int_16_handler = DefaultHandler);
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PROVIDE(cpu_int_17_handler = DefaultHandler);
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PROVIDE(cpu_int_18_handler = DefaultHandler);
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PROVIDE(cpu_int_19_handler = DefaultHandler);
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PROVIDE(cpu_int_20_handler = DefaultHandler);
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PROVIDE(cpu_int_21_handler = DefaultHandler);
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PROVIDE(cpu_int_22_handler = DefaultHandler);
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PROVIDE(cpu_int_23_handler = DefaultHandler);
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PROVIDE(cpu_int_24_handler = DefaultHandler);
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PROVIDE(cpu_int_25_handler = DefaultHandler);
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PROVIDE(cpu_int_26_handler = DefaultHandler);
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PROVIDE(cpu_int_27_handler = DefaultHandler);
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PROVIDE(cpu_int_28_handler = DefaultHandler);
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PROVIDE(cpu_int_29_handler = DefaultHandler);
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PROVIDE(cpu_int_30_handler = DefaultHandler);
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PROVIDE(cpu_int_31_handler = DefaultHandler);
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PROVIDE(interrupt1 = DefaultHandler);
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PROVIDE(interrupt2 = DefaultHandler);
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PROVIDE(interrupt3 = DefaultHandler);
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PROVIDE(interrupt4 = DefaultHandler);
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PROVIDE(interrupt5 = DefaultHandler);
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PROVIDE(interrupt6 = DefaultHandler);
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PROVIDE(interrupt7 = DefaultHandler);
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PROVIDE(interrupt8 = DefaultHandler);
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PROVIDE(interrupt9 = DefaultHandler);
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PROVIDE(interrupt10 = DefaultHandler);
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PROVIDE(interrupt11 = DefaultHandler);
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PROVIDE(interrupt12 = DefaultHandler);
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PROVIDE(interrupt13 = DefaultHandler);
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PROVIDE(interrupt14 = DefaultHandler);
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PROVIDE(interrupt15 = DefaultHandler);
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PROVIDE(interrupt16 = DefaultHandler);
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PROVIDE(interrupt17 = DefaultHandler);
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PROVIDE(interrupt18 = DefaultHandler);
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PROVIDE(interrupt19 = DefaultHandler);
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PROVIDE(interrupt20 = DefaultHandler);
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PROVIDE(interrupt21 = DefaultHandler);
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PROVIDE(interrupt22 = DefaultHandler);
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PROVIDE(interrupt23 = DefaultHandler);
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PROVIDE(interrupt24 = DefaultHandler);
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PROVIDE(interrupt25 = DefaultHandler);
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PROVIDE(interrupt26 = DefaultHandler);
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PROVIDE(interrupt27 = DefaultHandler);
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PROVIDE(interrupt28 = DefaultHandler);
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PROVIDE(interrupt29 = DefaultHandler);
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PROVIDE(interrupt30 = DefaultHandler);
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PROVIDE(interrupt31 = DefaultHandler);
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INCLUDE "device.x"
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@ -439,119 +439,119 @@ mod vectored {
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_1_handler(context: &mut TrapFrame) {
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unsafe fn interrupt1(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt1, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_2_handler(context: &mut TrapFrame) {
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unsafe fn interrupt2(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt2, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_3_handler(context: &mut TrapFrame) {
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unsafe fn interrupt3(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt3, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_4_handler(context: &mut TrapFrame) {
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unsafe fn interrupt4(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt4, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_5_handler(context: &mut TrapFrame) {
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unsafe fn interrupt5(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt5, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_6_handler(context: &mut TrapFrame) {
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unsafe fn interrupt6(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt6, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_7_handler(context: &mut TrapFrame) {
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unsafe fn interrupt7(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt7, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_8_handler(context: &mut TrapFrame) {
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unsafe fn interrupt8(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt8, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_9_handler(context: &mut TrapFrame) {
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unsafe fn interrupt9(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt9, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_10_handler(context: &mut TrapFrame) {
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unsafe fn interrupt10(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt10, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_11_handler(context: &mut TrapFrame) {
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unsafe fn interrupt11(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt11, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_12_handler(context: &mut TrapFrame) {
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unsafe fn interrupt12(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt12, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_13_handler(context: &mut TrapFrame) {
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unsafe fn interrupt13(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt13, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_14_handler(context: &mut TrapFrame) {
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unsafe fn interrupt14(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt14, context)
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}
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_15_handler(context: &mut TrapFrame) {
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unsafe fn interrupt15(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt15, context)
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}
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#[cfg(plic)]
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_16_handler(context: &mut TrapFrame) {
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unsafe fn interrupt16(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt16, context)
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}
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#[cfg(plic)]
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_17_handler(context: &mut TrapFrame) {
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unsafe fn interrupt17(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt17, context)
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}
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#[cfg(plic)]
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_18_handler(context: &mut TrapFrame) {
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unsafe fn interrupt18(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt18, context)
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}
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#[cfg(plic)]
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#[no_mangle]
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#[ram]
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unsafe fn cpu_int_19_handler(context: &mut TrapFrame) {
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unsafe fn interrupt19(context: &mut TrapFrame) {
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handle_interrupts(CpuInterrupt::Interrupt19, context)
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}
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}
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@ -512,157 +512,157 @@ r#"
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_start_trap1:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_1_handler
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la ra, interrupt1
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j _start_trap_direct
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_start_trap2:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_2_handler
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la ra, interrupt2
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j _start_trap_direct
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_start_trap3:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_3_handler
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la ra, interrupt3
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j _start_trap_direct
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_start_trap4:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_4_handler
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la ra, interrupt4
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j _start_trap_direct
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_start_trap5:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_5_handler
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la ra, interrupt5
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j _start_trap_direct
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_start_trap6:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_6_handler
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la ra, interrupt6
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j _start_trap_direct
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_start_trap7:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_7_handler
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la ra, interrupt7
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j _start_trap_direct
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_start_trap8:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_8_handler
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la ra, interrupt8
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j _start_trap_direct
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_start_trap9:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_9_handler
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la ra, interrupt9
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j _start_trap_direct
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_start_trap10:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_10_handler
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la ra, interrupt10
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j _start_trap_direct
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_start_trap11:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_11_handler
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la ra, interrupt11
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j _start_trap_direct
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_start_trap12:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_12_handler
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la ra, interrupt12
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j _start_trap_direct
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_start_trap13:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_13_handler
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la ra, interrupt13
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j _start_trap_direct
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_start_trap14:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_14_handler
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la ra, interrupt14
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j _start_trap_direct
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_start_trap15:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_15_handler
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la ra, interrupt15
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j _start_trap_direct
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_start_trap16:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_16_handler
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la ra, interrupt16
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j _start_trap_direct
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_start_trap17:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_17_handler
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la ra, interrupt17
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j _start_trap_direct
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_start_trap18:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_18_handler
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la ra, interrupt18
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j _start_trap_direct
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_start_trap19:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_19_handler
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la ra, interrupt19
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j _start_trap_direct
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_start_trap20:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_20_handler
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la ra, interrupt20
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j _start_trap_direct
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_start_trap21:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_21_handler
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la ra, interrupt21
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j _start_trap_direct
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_start_trap22:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_22_handler
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la ra, interrupt22
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j _start_trap_direct
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_start_trap23:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_23_handler
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la ra, interrupt23
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j _start_trap_direct
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_start_trap24:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_24_handler
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la ra, interrupt24
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j _start_trap_direct
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_start_trap25:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_25_handler
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la ra, interrupt25
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j _start_trap_direct
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_start_trap26:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_26_handler
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la ra, interrupt26
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j _start_trap_direct
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_start_trap27:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_27_handler
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la ra, interrupt27
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j _start_trap_direct
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_start_trap28:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_28_handler
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la ra, interrupt28
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j _start_trap_direct
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_start_trap29:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_29_handler
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la ra, interrupt29
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j _start_trap_direct
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_start_trap30:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_30_handler
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la ra, interrupt30
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j _start_trap_direct
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_start_trap31:
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addi sp, sp, -40*4
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sw ra, 0(sp)
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la ra, cpu_int_31_handler
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la ra, interrupt31
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j _start_trap_direct
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la ra, _start_trap_rust_hal /* this runs on exception, use regular fault handler */
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_start_trap_direct:
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@ -829,36 +829,39 @@ _vector_table:
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r#"
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#this is required for the linking step, these symbols for in-use interrupts should always be overwritten by the user.
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.section .trap, "ax"
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.weak cpu_int_1_handler
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.weak cpu_int_2_handler
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.weak cpu_int_3_handler
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.weak cpu_int_4_handler
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.weak cpu_int_5_handler
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.weak cpu_int_6_handler
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.weak cpu_int_7_handler
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.weak cpu_int_8_handler
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.weak cpu_int_9_handler
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.weak cpu_int_10_handler
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.weak cpu_int_11_handler
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.weak cpu_int_12_handler
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.weak cpu_int_13_handler
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.weak cpu_int_14_handler
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.weak cpu_int_15_handler
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.weak cpu_int_16_handler
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.weak cpu_int_17_handler
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.weak cpu_int_18_handler
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.weak cpu_int_19_handler
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.weak cpu_int_20_handler
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.weak cpu_int_21_handler
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.weak cpu_int_22_handler
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.weak cpu_int_23_handler
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.weak cpu_int_24_handler
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.weak cpu_int_25_handler
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.weak cpu_int_26_handler
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.weak cpu_int_27_handler
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.weak cpu_int_28_handler
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.weak cpu_int_29_handler
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.weak cpu_int_30_handler
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.weak cpu_int_31_handler
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// See https://github.com/esp-rs/esp-hal/issues/1326 and https://reviews.llvm.org/D98762
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// and yes, this all has to go on one line... *sigh*.
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.lto_discard interrupt1, interrupt2, interrupt3, interrupt4, interrupt5, interrupt6, interrupt7, interrupt8, interrupt9, interrupt10, interrupt11, interrupt12, interrupt13, interrupt14, interrupt15, interrupt16, interrupt17, interrupt18, interrupt19, interrupt20, interrupt21, interrupt22, interrupt23, interrupt24, interrupt25, interrupt26, interrupt27, interrupt28, interrupt29, interrupt30, interrupt31
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.weak interrupt1
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.weak interrupt2
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.weak interrupt3
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.weak interrupt4
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.weak interrupt5
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.weak interrupt6
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.weak interrupt7
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.weak interrupt8
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.weak interrupt9
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.weak interrupt10
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.weak interrupt11
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.weak interrupt12
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.weak interrupt13
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.weak interrupt14
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.weak interrupt15
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.weak interrupt16
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.weak interrupt17
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.weak interrupt18
|
||||
.weak interrupt19
|
||||
.weak interrupt20
|
||||
.weak interrupt21
|
||||
.weak interrupt22
|
||||
.weak interrupt23
|
||||
.weak interrupt24
|
||||
.weak interrupt25
|
||||
.weak interrupt26
|
||||
.weak interrupt27
|
||||
.weak interrupt28
|
||||
.weak interrupt29
|
||||
.weak interrupt30
|
||||
.weak interrupt31
|
||||
"#,
|
||||
}
|
||||
|
||||
@ -70,7 +70,13 @@ opsram-2m = ["esp-hal/opsram-2m"]
|
||||
psram-2m = ["esp-hal/psram-2m"]
|
||||
|
||||
[profile.release]
|
||||
debug = true
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = false
|
||||
incremental = false
|
||||
opt-level = 3
|
||||
lto = 'fat'
|
||||
overflow-checks = false
|
||||
|
||||
[patch.crates-io]
|
||||
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "963c280621f0b7ec26546a5eff24a5032305437f" }
|
||||
|
||||
@ -53,41 +53,25 @@ embassy-time-systick-16mhz = ["esp-hal?/embassy-time-systick-16mhz"]
|
||||
embassy-time-systick-80mhz = ["esp-hal?/embassy-time-systick-80mhz"]
|
||||
embassy-time-timg0 = ["esp-hal?/embassy-time-timg0"]
|
||||
|
||||
# cargo build/run
|
||||
# https://doc.rust-lang.org/cargo/reference/profiles.html#test
|
||||
# Test and bench profiles inherit from dev and release respectively.
|
||||
|
||||
[profile.dev]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = true # <-
|
||||
debug-assertions = true
|
||||
incremental = false
|
||||
opt-level = 'z' # <-
|
||||
overflow-checks = true # <-
|
||||
opt-level = 'z'
|
||||
overflow-checks = true
|
||||
|
||||
# cargo test
|
||||
[profile.test]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = true # <-
|
||||
incremental = false
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = true # <-
|
||||
|
||||
# cargo build/run --release
|
||||
[profile.release]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = false # <-
|
||||
debug-assertions = false
|
||||
incremental = false
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = false # <-
|
||||
|
||||
# cargo test --release
|
||||
[profile.bench]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = false # <-
|
||||
incremental = false
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = false # <-
|
||||
opt-level = 3
|
||||
lto = 'fat'
|
||||
overflow-checks = false
|
||||
|
||||
[patch.crates-io]
|
||||
semihosting = { git = "https://github.com/taiki-e/semihosting", rev = "c829c19" }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user