discard interrupt symbols from lto so that lto doesn't end up rebinding them (#1327)

esp-hal/ld/riscv/hal-defaults.x

@@ -1,35 +1,35 @@
 PROVIDE(DefaultHandler = EspDefaultHandler);
 
-PROVIDE(cpu_int_1_handler = DefaultHandler);
+PROVIDE(interrupt1 = DefaultHandler);
-PROVIDE(cpu_int_2_handler = DefaultHandler);
+PROVIDE(interrupt2 = DefaultHandler);
-PROVIDE(cpu_int_3_handler = DefaultHandler);
+PROVIDE(interrupt3 = DefaultHandler);
-PROVIDE(cpu_int_4_handler = DefaultHandler);
+PROVIDE(interrupt4 = DefaultHandler);
-PROVIDE(cpu_int_5_handler = DefaultHandler);
+PROVIDE(interrupt5 = DefaultHandler);
-PROVIDE(cpu_int_6_handler = DefaultHandler);
+PROVIDE(interrupt6 = DefaultHandler);
-PROVIDE(cpu_int_7_handler = DefaultHandler);
+PROVIDE(interrupt7 = DefaultHandler);
-PROVIDE(cpu_int_8_handler = DefaultHandler);
+PROVIDE(interrupt8 = DefaultHandler);
-PROVIDE(cpu_int_9_handler = DefaultHandler);
+PROVIDE(interrupt9 = DefaultHandler);
-PROVIDE(cpu_int_10_handler = DefaultHandler);
+PROVIDE(interrupt10 = DefaultHandler);
-PROVIDE(cpu_int_11_handler = DefaultHandler);
+PROVIDE(interrupt11 = DefaultHandler);
-PROVIDE(cpu_int_12_handler = DefaultHandler);
+PROVIDE(interrupt12 = DefaultHandler);
-PROVIDE(cpu_int_13_handler = DefaultHandler);
+PROVIDE(interrupt13 = DefaultHandler);
-PROVIDE(cpu_int_14_handler = DefaultHandler);
+PROVIDE(interrupt14 = DefaultHandler);
-PROVIDE(cpu_int_15_handler = DefaultHandler);
+PROVIDE(interrupt15 = DefaultHandler);
-PROVIDE(cpu_int_16_handler = DefaultHandler);
+PROVIDE(interrupt16 = DefaultHandler);
-PROVIDE(cpu_int_17_handler = DefaultHandler);
+PROVIDE(interrupt17 = DefaultHandler);
-PROVIDE(cpu_int_18_handler = DefaultHandler);
+PROVIDE(interrupt18 = DefaultHandler);
-PROVIDE(cpu_int_19_handler = DefaultHandler);
+PROVIDE(interrupt19 = DefaultHandler);
-PROVIDE(cpu_int_20_handler = DefaultHandler);
+PROVIDE(interrupt20 = DefaultHandler);
-PROVIDE(cpu_int_21_handler = DefaultHandler);
+PROVIDE(interrupt21 = DefaultHandler);
-PROVIDE(cpu_int_22_handler = DefaultHandler);
+PROVIDE(interrupt22 = DefaultHandler);
-PROVIDE(cpu_int_23_handler = DefaultHandler);
+PROVIDE(interrupt23 = DefaultHandler);
-PROVIDE(cpu_int_24_handler = DefaultHandler);
+PROVIDE(interrupt24 = DefaultHandler);
-PROVIDE(cpu_int_25_handler = DefaultHandler);
+PROVIDE(interrupt25 = DefaultHandler);
-PROVIDE(cpu_int_26_handler = DefaultHandler);
+PROVIDE(interrupt26 = DefaultHandler);
-PROVIDE(cpu_int_27_handler = DefaultHandler);
+PROVIDE(interrupt27 = DefaultHandler);
-PROVIDE(cpu_int_28_handler = DefaultHandler);
+PROVIDE(interrupt28 = DefaultHandler);
-PROVIDE(cpu_int_29_handler = DefaultHandler);
+PROVIDE(interrupt29 = DefaultHandler);
-PROVIDE(cpu_int_30_handler = DefaultHandler);
+PROVIDE(interrupt30 = DefaultHandler);
-PROVIDE(cpu_int_31_handler = DefaultHandler);
+PROVIDE(interrupt31 = DefaultHandler);
 
 INCLUDE "device.x"

esp-hal/src/interrupt/riscv.rs

@@ -439,119 +439,119 @@ mod vectored {
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_1_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt1(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt1, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_2_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt2(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt2, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_3_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt3(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt3, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_4_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt4(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt4, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_5_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt5(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt5, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_6_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt6(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt6, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_7_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt7(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt7, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_8_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt8(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt8, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_9_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt9(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt9, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_10_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt10(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt10, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_11_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt11(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt11, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_12_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt12(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt12, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_13_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt13(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt13, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_14_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt14(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt14, context)
     }
 
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_15_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt15(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt15, context)
     }
 
     #[cfg(plic)]
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_16_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt16(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt16, context)
     }
 
     #[cfg(plic)]
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_17_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt17(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt17, context)
     }
 
     #[cfg(plic)]
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_18_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt18(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt18, context)
     }
 
     #[cfg(plic)]
     #[no_mangle]
     #[ram]
-    unsafe fn cpu_int_19_handler(context: &mut TrapFrame) {
+    unsafe fn interrupt19(context: &mut TrapFrame) {
         handle_interrupts(CpuInterrupt::Interrupt19, context)
     }
 }

esp-riscv-rt/src/lib.rs

@@ -512,157 +512,157 @@ r#"
 _start_trap1:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_1_handler
+    la ra, interrupt1
     j _start_trap_direct
 _start_trap2:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_2_handler
+    la ra, interrupt2
     j _start_trap_direct
 _start_trap3:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_3_handler
+    la ra, interrupt3
     j _start_trap_direct
 _start_trap4:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_4_handler
+    la ra, interrupt4
     j _start_trap_direct
 _start_trap5:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_5_handler
+    la ra, interrupt5
     j _start_trap_direct
 _start_trap6:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_6_handler
+    la ra, interrupt6
     j _start_trap_direct
 _start_trap7:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_7_handler
+    la ra, interrupt7
     j _start_trap_direct
 _start_trap8:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_8_handler
+    la ra, interrupt8
     j _start_trap_direct
 _start_trap9:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_9_handler
+    la ra, interrupt9
     j _start_trap_direct
 _start_trap10:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_10_handler
+    la ra, interrupt10
     j _start_trap_direct
 _start_trap11:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_11_handler
+    la ra, interrupt11
     j _start_trap_direct
 _start_trap12:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_12_handler
+    la ra, interrupt12
     j _start_trap_direct
 _start_trap13:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_13_handler
+    la ra, interrupt13
     j _start_trap_direct
 _start_trap14:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_14_handler
+    la ra, interrupt14
     j _start_trap_direct
 _start_trap15:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_15_handler
+    la ra, interrupt15
     j _start_trap_direct
 _start_trap16:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_16_handler
+    la ra, interrupt16
     j _start_trap_direct
 _start_trap17:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_17_handler
+    la ra, interrupt17
     j _start_trap_direct
 _start_trap18:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_18_handler
+    la ra, interrupt18
     j _start_trap_direct
 _start_trap19:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_19_handler
+    la ra, interrupt19
     j _start_trap_direct
 _start_trap20:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_20_handler
+    la ra, interrupt20
     j _start_trap_direct
 _start_trap21:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_21_handler
+    la ra, interrupt21
     j _start_trap_direct
 _start_trap22:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_22_handler
+    la ra, interrupt22
     j _start_trap_direct
 _start_trap23:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_23_handler
+    la ra, interrupt23
     j _start_trap_direct
 _start_trap24:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_24_handler
+    la ra, interrupt24
     j _start_trap_direct
 _start_trap25:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_25_handler
+    la ra, interrupt25
     j _start_trap_direct
 _start_trap26:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_26_handler
+    la ra, interrupt26
     j _start_trap_direct
 _start_trap27:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_27_handler
+    la ra, interrupt27
     j _start_trap_direct
 _start_trap28:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_28_handler
+    la ra, interrupt28
     j _start_trap_direct
 _start_trap29:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_29_handler
+    la ra, interrupt29
     j _start_trap_direct
 _start_trap30:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_30_handler
+    la ra, interrupt30
     j _start_trap_direct
 _start_trap31:
     addi sp, sp, -40*4
     sw ra, 0(sp)
-    la ra, cpu_int_31_handler
+    la ra, interrupt31
     j _start_trap_direct
 la ra, _start_trap_rust_hal /* this runs on exception, use regular fault handler */
 _start_trap_direct:
@@ -829,36 +829,39 @@ _vector_table:
 r#"
 #this is required for the linking step, these symbols for in-use interrupts should always be overwritten by the user.
 .section .trap, "ax"
-.weak cpu_int_1_handler
+// See https://github.com/esp-rs/esp-hal/issues/1326 and https://reviews.llvm.org/D98762
-.weak cpu_int_2_handler
+// and yes, this all has to go on one line... *sigh*.
-.weak cpu_int_3_handler
+.lto_discard interrupt1, interrupt2, interrupt3, interrupt4, interrupt5, interrupt6, interrupt7, interrupt8, interrupt9, interrupt10, interrupt11, interrupt12, interrupt13, interrupt14, interrupt15, interrupt16, interrupt17, interrupt18, interrupt19, interrupt20, interrupt21, interrupt22, interrupt23, interrupt24, interrupt25, interrupt26, interrupt27, interrupt28, interrupt29, interrupt30, interrupt31
-.weak cpu_int_4_handler
+.weak interrupt1
-.weak cpu_int_5_handler
+.weak interrupt2
-.weak cpu_int_6_handler
+.weak interrupt3
-.weak cpu_int_7_handler
+.weak interrupt4
-.weak cpu_int_8_handler
+.weak interrupt5
-.weak cpu_int_9_handler
+.weak interrupt6
-.weak cpu_int_10_handler
+.weak interrupt7
-.weak cpu_int_11_handler
+.weak interrupt8
-.weak cpu_int_12_handler
+.weak interrupt9
-.weak cpu_int_13_handler
+.weak interrupt10
-.weak cpu_int_14_handler
+.weak interrupt11
-.weak cpu_int_15_handler
+.weak interrupt12
-.weak cpu_int_16_handler
+.weak interrupt13
-.weak cpu_int_17_handler
+.weak interrupt14
-.weak cpu_int_18_handler
+.weak interrupt15
-.weak cpu_int_19_handler
+.weak interrupt16
-.weak cpu_int_20_handler
+.weak interrupt17
-.weak cpu_int_21_handler
+.weak interrupt18
-.weak cpu_int_22_handler
+.weak interrupt19
-.weak cpu_int_23_handler
+.weak interrupt20
-.weak cpu_int_24_handler
+.weak interrupt21
-.weak cpu_int_25_handler
+.weak interrupt22
-.weak cpu_int_26_handler
+.weak interrupt23
-.weak cpu_int_27_handler
+.weak interrupt24
-.weak cpu_int_28_handler
+.weak interrupt25
-.weak cpu_int_29_handler
+.weak interrupt26
-.weak cpu_int_30_handler
+.weak interrupt27
-.weak cpu_int_31_handler
+.weak interrupt28
+.weak interrupt29
+.weak interrupt30
+.weak interrupt31
 "#,
 }

examples/Cargo.toml

@@ -70,7 +70,13 @@ opsram-2m = ["esp-hal/opsram-2m"]
 psram-2m  = ["esp-hal/psram-2m"]
 
 [profile.release]
-debug = true
+codegen-units    = 1
+debug            = 2
+debug-assertions = false
+incremental      = false
+opt-level        = 3
+lto = 'fat'
+overflow-checks  = false
 
 [patch.crates-io]
 esp32 =   { git = "https://github.com/esp-rs/esp-pacs", rev = "963c280621f0b7ec26546a5eff24a5032305437f" }

hil-test/Cargo.toml

@@ -53,41 +53,25 @@ embassy-time-systick-16mhz = ["esp-hal?/embassy-time-systick-16mhz"]
 embassy-time-systick-80mhz = ["esp-hal?/embassy-time-systick-80mhz"]
 embassy-time-timg0   = ["esp-hal?/embassy-time-timg0"]
 
-# cargo build/run
+# https://doc.rust-lang.org/cargo/reference/profiles.html#test
+# Test and bench profiles inherit from dev and release respectively.
+
 [profile.dev]
 codegen-units    = 1
 debug            = 2
-debug-assertions = true  # <-
+debug-assertions = true
 incremental      = false
-opt-level        = 'z'   # <-
+opt-level        = 'z'
-overflow-checks  = true  # <-
+overflow-checks  = true
 
-# cargo test
-[profile.test]
-codegen-units    = 1
-debug            = 2
-debug-assertions = true  # <-
-incremental      = false
-opt-level        = 3     # <-
-overflow-checks  = true  # <-
-
-# cargo build/run --release
 [profile.release]
 codegen-units    = 1
 debug            = 2
-debug-assertions = false # <-
+debug-assertions = false
 incremental      = false
-opt-level        = 3     # <-
+opt-level        = 3
-overflow-checks  = false # <-
+lto = 'fat'
-
+overflow-checks  = false
-# cargo test --release
-[profile.bench]
-codegen-units    = 1
-debug            = 2
-debug-assertions = false # <-
-incremental      = false
-opt-level        = 3     # <-
-overflow-checks  = false # <-
 
 [patch.crates-io]
 semihosting = { git = "https://github.com/taiki-e/semihosting", rev = "c829c19" }