From 285cfe4c5dbfb027e91e2e11ffbdea2c6a777d9c Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Fri, 2 Feb 2024 16:00:06 +0000 Subject: [PATCH] "Fix" clippy checks in CI, resolve a bunch of clippy warnings (#1134) * Fix a bunch of `clippy` warnings in the `esp-hal` build script * Resolve most clippy warnings for ESP32 (no features) * Do the same for ESP32-S2/S3... * Same for C2/C3... * CI check for clippy now actually works (and passes!) for Xtensa * RISC-V chips (except P4) now pass clippy in CI * Add some safety doc comments which I forgot to write * The `PwmPeripheral` trait is no longer `unsafe`, and is instead now sealed --- .github/workflows/ci.yml | 46 ++++-- esp-hal/build.rs | 38 +++-- esp-hal/src/aes/esp32.rs | 2 +- esp-hal/src/aes/mod.rs | 4 +- esp-hal/src/analog/adc/calibration/curve.rs | 12 +- esp-hal/src/analog/adc/esp32.rs | 24 +-- esp-hal/src/analog/adc/mod.rs | 4 +- esp-hal/src/analog/adc/riscv.rs | 21 +-- esp-hal/src/analog/adc/xtensa.rs | 37 +++-- esp-hal/src/clock/clocks_ll/esp32.rs | 17 +-- esp-hal/src/clock/clocks_ll/esp32c2.rs | 10 +- esp-hal/src/clock/clocks_ll/esp32c3.rs | 11 +- esp-hal/src/clock/clocks_ll/esp32c6.rs | 7 +- esp-hal/src/clock/clocks_ll/esp32h2.rs | 7 +- esp-hal/src/clock/clocks_ll/esp32s2.rs | 4 +- esp-hal/src/delay.rs | 4 +- esp-hal/src/dma/mod.rs | 6 +- esp-hal/src/ecc.rs | 28 ++-- esp-hal/src/embassy/mod.rs | 2 +- esp-hal/src/gpio.rs | 157 +++++++++++--------- esp-hal/src/i2c.rs | 2 +- esp-hal/src/i2s.rs | 121 ++++++++------- esp-hal/src/lcd_cam/lcd/i8080.rs | 2 +- esp-hal/src/ledc/channel.rs | 6 +- esp-hal/src/ledc/timer.rs | 4 +- esp-hal/src/lib.rs | 3 +- esp-hal/src/mcpwm/mod.rs | 16 +- esp-hal/src/mcpwm/operator.rs | 13 +- esp-hal/src/mcpwm/timer.rs | 4 +- esp-hal/src/parl_io.rs | 21 +-- esp-hal/src/peripheral.rs | 10 +- esp-hal/src/reg_access.rs | 13 +- esp-hal/src/rmt.rs | 28 ++-- esp-hal/src/rng.rs | 3 +- esp-hal/src/rom/md5.rs | 6 + esp-hal/src/rom/mod.rs | 4 +- esp-hal/src/rsa/esp32.rs | 16 +- esp-hal/src/rsa/esp32cX.rs | 8 +- esp-hal/src/rsa/esp32sX.rs | 8 +- esp-hal/src/rsa/mod.rs | 23 +-- esp-hal/src/rtc_cntl/mod.rs | 72 ++++----- esp-hal/src/rtc_cntl/rtc/esp32c6.rs | 31 ++-- esp-hal/src/rtc_cntl/rtc/esp32h2.rs | 10 +- esp-hal/src/rtc_cntl/sleep/esp32.rs | 10 +- esp-hal/src/rtc_cntl/sleep/esp32c3.rs | 4 +- esp-hal/src/rtc_cntl/sleep/esp32c6.rs | 14 +- esp-hal/src/rtc_cntl/sleep/esp32s3.rs | 4 +- esp-hal/src/sha.rs | 4 +- esp-hal/src/soc/esp32/cpu_control.rs | 15 +- esp-hal/src/soc/esp32c2/gpio.rs | 2 +- esp-hal/src/soc/esp32c2/mod.rs | 1 + esp-hal/src/soc/esp32c3/gpio.rs | 2 +- esp-hal/src/soc/esp32c3/mod.rs | 1 + esp-hal/src/soc/esp32c6/gpio.rs | 2 +- esp-hal/src/soc/esp32c6/lp_core.rs | 4 +- esp-hal/src/soc/esp32c6/mod.rs | 1 + esp-hal/src/soc/esp32h2/gpio.rs | 2 +- esp-hal/src/soc/esp32h2/mod.rs | 1 + esp-hal/src/soc/esp32h2/radio_clocks.rs | 5 +- esp-hal/src/soc/esp32s2/psram.rs | 2 +- esp-hal/src/soc/esp32s3/cpu_control.rs | 15 +- esp-hal/src/soc/esp32s3/gpio.rs | 2 +- esp-hal/src/soc/mod.rs | 12 +- esp-hal/src/spi/master.rs | 66 ++++---- esp-hal/src/spi/slave.rs | 10 +- esp-hal/src/systimer.rs | 18 +++ esp-hal/src/timer.rs | 25 +++- esp-hal/src/trace.rs | 3 +- esp-hal/src/twai/filter.rs | 4 +- esp-hal/src/twai/mod.rs | 2 +- esp-hal/src/uart.rs | 23 ++- esp-hal/src/usb_serial_jtag.rs | 6 +- 72 files changed, 567 insertions(+), 558 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index d3aaa1439..e60ad8f9c 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -709,11 +709,32 @@ jobs: - uses: dtolnay/rust-toolchain@v1 with: toolchain: nightly - targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf + targets: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf # ,riscv32imafc-unknown-none-elf components: clippy,rust-src - uses: Swatinem/rust-cache@v2 # Run 'cargo clippy' on all packages targeting RISC-V: + - name: clippy (esp32c2-hal) + run: | + cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=esp32c2,xtal-40mhz \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default + - name: clippy (esp32c3-hal) + run: | + cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imc-unknown-none-elf --features=esp32c3 \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default + - name: clippy (esp32c6-hal) + run: | + cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imac-unknown-none-elf --features=esp32c6 \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default + - name: clippy (esp32h2-hal) + run: | + cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imac-unknown-none-elf --features=esp32h2 \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default + # - name: clippy (esp32p4-hal) + # run: | + # cargo clippy --manifest-path=esp-hal/Cargo.toml --target=riscv32imafc-unknown-none-elf --features=esp32p4 \ + # -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity -A clippy::enum_variant_names -A clippy::field_reassign_with_default + - name: clippy (esp-lp-hal, esp32c6) run: cd esp-lp-hal && cargo clippy --features=esp32c6 -- -D warnings - name: clippy (esp-lp-hal, esp32s2) @@ -722,16 +743,6 @@ jobs: run: cd esp-lp-hal && cargo clippy --features=esp32s3 -- -D warnings - name: clippy (esp-riscv-rt) run: cd esp-riscv-rt && cargo clippy --target=riscv32imc-unknown-none-elf -- -D warnings - - name: clippy (esp32c2-hal) - run: cd esp32c2-hal && cargo clippy -- -D warnings - - name: clippy (esp32c3-hal) - run: cd esp32c3-hal && cargo clippy -- -D warnings - - name: clippy (esp32c6-hal) - run: cd esp32c6-hal && cargo clippy -- -D warnings - - name: clippy (esp32h2-hal) - run: cd esp32h2-hal && cargo clippy -- -D warnings - - name: clippy (esp32p4-hal) - run: cd esp32p4-hal && cargo clippy -- -D warnings clippy-xtensa: runs-on: ubuntu-latest @@ -740,16 +751,23 @@ jobs: - uses: actions/checkout@v4 - uses: esp-rs/xtensa-toolchain@v1.5 with: + default: true ldproxy: false - uses: Swatinem/rust-cache@v2 # Run 'cargo clippy' on all packages targeting Xtensa: - name: clippy (esp32-hal) - run: cd esp32-hal && cargo clippy -- -D warnings + run: | + cargo clippy -Zbuild-std=core --manifest-path=esp-hal/Cargo.toml --target=xtensa-esp32-none-elf --features=esp32,xtal-40mhz \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity - name: clippy (esp32s2-hal) - run: cd esp32s2-hal && cargo clippy -- -D warnings + run: | + cargo clippy -Zbuild-std=core --manifest-path=esp-hal/Cargo.toml --target=xtensa-esp32s2-none-elf --features=esp32s2 \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity - name: clippy (esp32s3-hal) - run: cd esp32s3-hal && cargo clippy -- -D warnings + run: | + cargo clippy -Zbuild-std=core --manifest-path=esp-hal/Cargo.toml --target=xtensa-esp32s3-none-elf --features=esp32s3 \ + -- -D warnings -A clippy::too_many_arguments -A clippy::type_complexity rustfmt: runs-on: ubuntu-latest diff --git a/esp-hal/build.rs b/esp-hal/build.rs index efe2932b7..f0462e852 100644 --- a/esp-hal/build.rs +++ b/esp-hal/build.rs @@ -178,8 +178,8 @@ fn main() -> Result<(), Box> { } // Don't support "interrupt-preemption" and "direct-vectoring" on Xtensa and - // RISCV-clic - if (*&device.symbols.contains(&String::from("clic")) || device.arch == Arch::Xtensa) + // RISC-V with CLIC: + if (device.symbols.contains(&String::from("clic")) || device.arch == Arch::Xtensa) && (cfg!(feature = "direct-vectoring") || cfg!(feature = "interrupt-preemption")) { panic!("The target does not support interrupt-preemption and direct-vectoring"); @@ -290,7 +290,7 @@ fn copy_dir_all( /// A naive pre-processor for linker scripts fn preprocess_file( - config: &Vec<&str>, + config: &[&str], src: impl AsRef, dst: impl AsRef, ) -> std::io::Result<()> { @@ -304,15 +304,15 @@ fn preprocess_file( let line = line?; let trimmed = line.trim(); - if trimmed.starts_with("#IF ") { - let condition = &trimmed[4..]; - let should_take = take.iter().all(|v| *v == true); + if let Some(stripped) = trimmed.strip_prefix("#IF ") { + let condition = stripped; + let should_take = take.iter().all(|v| *v); let should_take = should_take && config.contains(&condition); take.push(should_take); continue; } else if trimmed == "#ELSE" { let taken = take.pop().unwrap(); - let should_take = take.iter().all(|v| *v == true); + let should_take = take.iter().all(|v| *v); let should_take = should_take && !taken; take.push(should_take); continue; @@ -322,8 +322,8 @@ fn preprocess_file( } if *take.last().unwrap() { - out_file.write(line.as_bytes())?; - out_file.write(b"\n")?; + out_file.write_all(line.as_bytes())?; + let _ = out_file.write(b"\n")?; } } Ok(()) @@ -340,15 +340,15 @@ fn gen_efuse_table(device_name: &str, out_dir: impl AsRef) -> Result<(), B let mut line = String::with_capacity(128); while reader.read_line(&mut line)? > 0 { - if line.ends_with("\n") { + if line.ends_with('\n') { line.pop(); - if line.ends_with("\r") { + if line.ends_with('\r') { line.pop(); } } // drop comment and trim line.truncate( - if let Some((pfx, _cmt)) = line.split_once("#") { + if let Some((pfx, _cmt)) = line.split_once('#') { pfx } else { &line @@ -361,9 +361,9 @@ fn gen_efuse_table(device_name: &str, out_dir: impl AsRef) -> Result<(), B continue; } - let mut fields = line.split(","); + let mut fields = line.split(','); match ( - fields.next().map(|s| s.trim().replace(".", "_")), + fields.next().map(|s| s.trim().replace('.', "_")), fields .next() .map(|s| s.trim().replace(|c: char| !c.is_ascii_digit(), "")), @@ -404,16 +404,12 @@ fn detect_atomic_extension(ext: &str) -> bool { // handle that let target_flags = rustflags .split(0x1f as char) - .filter(|s| s.starts_with("target-feature=")) - .map(|s| s.strip_prefix("target-feature=")) - .flatten(); + .filter_map(|s| s.strip_prefix("target-feature=")); for tf in target_flags { let tf = tf - .split(",") + .split(',') .map(|s| s.trim()) - .filter(|s| s.starts_with('+')) - .map(|s| s.strip_prefix('+')) - .flatten(); + .filter_map(|s| s.strip_prefix('+')); for tf in tf { if tf == ext { return true; diff --git a/esp-hal/src/aes/esp32.rs b/esp-hal/src/aes/esp32.rs index 5da2fb350..3a0444429 100644 --- a/esp-hal/src/aes/esp32.rs +++ b/esp-hal/src/aes/esp32.rs @@ -64,7 +64,7 @@ impl<'d> Aes<'d> { pub(super) fn read_block(&self, block: &mut [u8]) { let text_len = self.aes.text_iter().count(); debug_assert_eq!(block.len(), text_len * ALIGN_SIZE); - Self::read_from_regset(block, text_len, &self.aes.text(0)); + Self::read_from_regset(block, text_len, self.aes.text(0)); } } diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs index 5bbac7ad1..cf21567e6 100644 --- a/esp-hal/src/aes/mod.rs +++ b/esp-hal/src/aes/mod.rs @@ -140,7 +140,7 @@ impl<'d> Aes<'d> { pub fn new(aes: impl Peripheral

+ 'd) -> Self { crate::into_ref!(aes); let mut ret = Self { - aes: aes, + aes, #[cfg(not(esp32))] alignment_helper: AlignmentHelper::default(), }; @@ -440,7 +440,7 @@ pub mod dma { }) } - fn start_transfer_dma<'w>( + fn start_transfer_dma( &mut self, write_buffer_ptr: *const u8, write_buffer_len: usize, diff --git a/esp-hal/src/analog/adc/calibration/curve.rs b/esp-hal/src/analog/adc/calibration/curve.rs index 30d8802dd..5bc711f1b 100644 --- a/esp-hal/src/analog/adc/calibration/curve.rs +++ b/esp-hal/src/analog/adc/calibration/curve.rs @@ -95,11 +95,11 @@ where } else { // err = coeff[0] + coeff[1] * val + coeff[2] * val^2 + ... + coeff[n] * val^n let mut var = 1i64; - let mut err = (var * self.coeff[0] as i64 / COEFF_MUL) as i32; + let mut err = (var * self.coeff[0] / COEFF_MUL) as i32; for coeff in &self.coeff[1..] { - var = var * val as i64; - err += (var * *coeff as i64 / COEFF_MUL) as i32; + var *= val as i64; + err += (var * *coeff / COEFF_MUL) as i32; } err @@ -148,7 +148,7 @@ mod impls { #[cfg(esp32c3)] CURVES_COEFFS1 [ Attenuation0dB => [ - -0.2259664705000430, + -0.225966470500043, -0.0007265418501948, 0.0000109410402681, ], @@ -158,7 +158,7 @@ mod impls { 0.0000088166562521, ], Attenuation6dB => [ - -1.0178592392364350, + -1.017859239236435, -0.0097159265299153, 0.0000149794028038, ], @@ -215,7 +215,7 @@ mod impls { 0.0000208385525314, ], Attenuation11dB => [ - -0.6444034182694780, + -0.644403418269478, -0.0644334888647536, 0.0001297891447611, -0.0000000707697180, diff --git a/esp-hal/src/analog/adc/esp32.rs b/esp-hal/src/analog/adc/esp32.rs index db33e1b0a..56d01119b 100644 --- a/esp-hal/src/analog/adc/esp32.rs +++ b/esp-hal/src/analog/adc/esp32.rs @@ -55,7 +55,7 @@ where AdcPin { pin, - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } @@ -65,7 +65,7 @@ impl Default for AdcConfig { AdcConfig { resolution: Resolution::Resolution12Bit, attenuations: [None; 10], - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } @@ -111,7 +111,7 @@ impl RegisterAccess for ADC1 { fn set_attenuation(channel: usize, attenuation: u8) { unsafe { &*SENS::ptr() }.sar_atten1().modify(|r, w| { let new_value = (r.bits() & !(0b11 << (channel * 2))) - | (((attenuation as u8 & 0b11) as u32) << (channel * 2)); + | (((attenuation & 0b11) as u32) << (channel * 2)); unsafe { w.sar1_atten().bits(new_value) } }); @@ -166,7 +166,7 @@ impl RegisterAccess for ADC1 { .sar_meas_start1() .read() .meas1_data_sar() - .bits() as u16 + .bits() } } @@ -186,7 +186,7 @@ impl RegisterAccess for ADC2 { fn set_attenuation(channel: usize, attenuation: u8) { unsafe { &*SENS::ptr() }.sar_atten2().modify(|r, w| { let new_value = (r.bits() & !(0b11 << (channel * 2))) - | (((attenuation as u8 & 0b11) as u32) << (channel * 2)); + | (((attenuation & 0b11) as u32) << (channel * 2)); unsafe { w.sar2_atten().bits(new_value) } }); @@ -241,7 +241,7 @@ impl RegisterAccess for ADC2 { .sar_meas_start2() .read() .meas2_data_sar() - .bits() as u16 + .bits() } } @@ -271,9 +271,9 @@ where // Set attenuation for pins let attenuations = config.attenuations; - for channel in 0..attenuations.len() { - if let Some(attenuation) = attenuations[channel] { - ADC1::set_attenuation(channel, attenuation as u8); + for (channel, attentuation) in attenuations.iter().enumerate() { + if let Some(attenuation) = attentuation { + ADC1::set_attenuation(channel, *attenuation as u8); } } @@ -356,7 +356,7 @@ where fn read(&mut self, _pin: &mut AdcPin) -> nb::Result { use embedded_hal::adc::Channel; - if self.attenuations[AdcPin::::channel() as usize] == None { + if self.attenuations[AdcPin::::channel() as usize].is_none() { panic!( "Channel {} is not configured reading!", AdcPin::::channel() @@ -374,7 +374,7 @@ where // If no conversions are in progress, start a new one for given channel self.active_channel = Some(AdcPin::::channel()); - ADCI::set_en_pad(AdcPin::::channel() as u8); + ADCI::set_en_pad(AdcPin::::channel()); ADCI::clear_start_sar(); ADCI::set_start_sar(); @@ -414,7 +414,7 @@ macro_rules! impl_adc_interface { } } -mod implementation { +mod adc_implementation { use crate::peripherals::{ADC1, ADC2}; impl_adc_interface! { diff --git a/esp-hal/src/analog/adc/mod.rs b/esp-hal/src/analog/adc/mod.rs index 2af7496b6..bcf143294 100644 --- a/esp-hal/src/analog/adc/mod.rs +++ b/esp-hal/src/analog/adc/mod.rs @@ -84,9 +84,7 @@ pub trait AdcCalScheme: Sized + private::Sealed { impl private::Sealed for () {} impl AdcCalScheme for () { - fn new_cal(_atten: Attenuation) -> Self { - () - } + fn new_cal(_atten: Attenuation) -> Self {} } /// A helper trait to get access to ADC calibration efuses. diff --git a/esp-hal/src/analog/adc/riscv.rs b/esp-hal/src/analog/adc/riscv.rs index 424dc0ad7..7aa260b4f 100644 --- a/esp-hal/src/analog/adc/riscv.rs +++ b/esp-hal/src/analog/adc/riscv.rs @@ -1,7 +1,10 @@ use core::marker::PhantomData; +#[cfg(not(esp32h2))] pub use self::calibration::*; -use super::{AdcCalEfuse, AdcCalScheme, AdcCalSource, AdcChannel, Attenuation}; +#[cfg(not(esp32h2))] +use super::AdcCalEfuse; +use super::{AdcCalScheme, AdcCalSource, AdcChannel, Attenuation}; #[cfg(any(esp32c6, esp32h2))] use crate::clock::clocks_ll::regi2c_write_mask; #[cfg(any(esp32c2, esp32c3, esp32c6))] @@ -149,7 +152,7 @@ where AdcPin { pin, cal_scheme: AdcCalScheme::<()>::new_cal(attenuation), - _phantom: PhantomData::default(), + _phantom: PhantomData, } } @@ -168,7 +171,7 @@ where AdcPin { pin, cal_scheme: CS::new_cal(attenuation), - _phantom: PhantomData::default(), + _phantom: PhantomData, } } @@ -221,7 +224,7 @@ impl Default for AdcConfig { AdcConfig { resolution: Resolution::Resolution12Bit, attenuations: [None; NUM_ATTENS], - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } @@ -557,7 +560,7 @@ where fn read(&mut self, pin: &mut AdcPin) -> nb::Result { use embedded_hal::adc::Channel; - if self.attenuations[AdcPin::::channel() as usize] == None { + if self.attenuations[AdcPin::::channel() as usize].is_none() { panic!( "Channel {} is not configured reading!", AdcPin::::channel() @@ -646,7 +649,7 @@ macro_rules! impl_adc_interface { } #[cfg(esp32c2)] -mod implementation { +mod adc_implementation { use crate::peripherals::ADC1; impl_adc_interface! { @@ -661,7 +664,7 @@ mod implementation { } #[cfg(esp32c3)] -mod implementation { +mod adc_implementation { use crate::peripherals::{ADC1, ADC2}; impl_adc_interface! { @@ -682,7 +685,7 @@ mod implementation { } #[cfg(esp32c6)] -mod implementation { +mod adc_implementation { use crate::peripherals::ADC1; impl_adc_interface! { @@ -699,7 +702,7 @@ mod implementation { } #[cfg(esp32h2)] -mod implementation { +mod adc_implementation { use crate::peripherals::ADC1; impl_adc_interface! { diff --git a/esp-hal/src/analog/adc/xtensa.rs b/esp-hal/src/analog/adc/xtensa.rs index e1614b74d..3d2df240d 100644 --- a/esp-hal/src/analog/adc/xtensa.rs +++ b/esp-hal/src/analog/adc/xtensa.rs @@ -1,5 +1,6 @@ use core::marker::PhantomData; +#[cfg(esp32s3)] pub use self::calibration::*; #[cfg(esp32s3)] use super::AdcCalEfuse; @@ -120,7 +121,7 @@ where AdcPin { pin, cal_scheme: AdcCalScheme::<()>::new_cal(attenuation), - _phantom: PhantomData::default(), + _phantom: PhantomData, } } @@ -139,7 +140,7 @@ where AdcPin { pin, cal_scheme: CS::new_cal(attenuation), - _phantom: PhantomData::default(), + _phantom: PhantomData, } } @@ -194,7 +195,7 @@ impl Default for AdcConfig { AdcConfig { resolution: Resolution::Resolution13Bit, attenuations: [None; 10], - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } @@ -266,7 +267,7 @@ impl RegisterAccess for crate::peripherals::ADC1 { let sensors = unsafe { &*SENS::ptr() }; sensors.sar_atten1().modify(|r, w| { let new_value = (r.bits() & !(0b11 << (channel * 2))) - | (((attenuation as u8 & 0b11) as u32) << (channel * 2)); + | (((attenuation & 0b11) as u32) << (channel * 2)); unsafe { w.sar1_atten().bits(new_value) } }); @@ -324,8 +325,11 @@ impl RegisterAccess for crate::peripherals::ADC1 { } fn read_data() -> u16 { - let sensors = unsafe { &*SENS::ptr() }; - sensors.sar_meas1_ctrl2().read().meas1_data_sar().bits() as u16 + unsafe { &*SENS::ptr() } + .sar_meas1_ctrl2() + .read() + .meas1_data_sar() + .bits() } fn set_init_code(data: u16) { @@ -397,7 +401,7 @@ impl RegisterAccess for crate::peripherals::ADC2 { let sensors = unsafe { &*SENS::ptr() }; sensors.sar_atten2().modify(|r, w| { let new_value = (r.bits() & !(0b11 << (channel * 2))) - | (((attenuation as u8 & 0b11) as u32) << (channel * 2)); + | (((attenuation & 0b11) as u32) << (channel * 2)); unsafe { w.sar2_atten().bits(new_value) } }); @@ -460,8 +464,11 @@ impl RegisterAccess for crate::peripherals::ADC2 { } fn read_data() -> u16 { - let sensors = unsafe { &*SENS::ptr() }; - sensors.sar_meas2_ctrl2().read().meas2_data_sar().bits() as u16 + unsafe { &*SENS::ptr() } + .sar_meas2_ctrl2() + .read() + .meas2_data_sar() + .bits() } fn set_init_code(data: u16) { @@ -533,9 +540,9 @@ where // Set attenuation for pins let attenuations = config.attenuations; - for channel in 0..attenuations.len() { - if let Some(attenuation) = attenuations[channel] { - ADCI::set_attenuation(channel, attenuation as u8); + for (channel, attenuation) in attenuations.iter().enumerate() { + if let Some(attenuation) = attenuation { + ADCI::set_attenuation(channel, *attenuation as u8); } } @@ -642,7 +649,7 @@ where fn read(&mut self, pin: &mut AdcPin) -> nb::Result { use embedded_hal::adc::Channel; - if self.attenuations[AdcPin::::channel() as usize] == None { + if self.attenuations[AdcPin::::channel() as usize].is_none() { panic!( "Channel {} is not configured reading!", AdcPin::::channel() @@ -663,7 +670,7 @@ where // Set ADC unit calibration according used scheme for pin ADCI::set_init_code(pin.cal_scheme.adc_cal()); - ADCI::set_en_pad(AdcPin::::channel() as u8); + ADCI::set_en_pad(AdcPin::::channel()); ADCI::clear_start_sample(); ADCI::start_sample(); @@ -708,7 +715,7 @@ macro_rules! impl_adc_interface { } } -mod implementation { +mod adc_implementation { use crate::peripherals::{ADC1, ADC2}; impl_adc_interface! { diff --git a/esp-hal/src/clock/clocks_ll/esp32.rs b/esp-hal/src/clock/clocks_ll/esp32.rs index 85b0f104a..57c83c294 100644 --- a/esp-hal/src/clock/clocks_ll/esp32.rs +++ b/esp-hal/src/clock/clocks_ll/esp32.rs @@ -53,9 +53,6 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock let lref: u32; let dcur: u32; let bw: u32; - let i2c_bbpll_lref: u32; - let i2c_bbpll_div_7_0: u32; - let i2c_bbpll_dcur: u32; if matches!(pll_freq, PllClock::Pll320MHz) { // Raise the voltage, if needed @@ -174,9 +171,9 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock ); } - i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref); - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (bw << 6) | dcur; + let i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref); + let i2c_bbpll_div_7_0 = div7_0; + let i2c_bbpll_dcur = (bw << 6) | dcur; i2c_writereg_rtc( I2C_BBPLL, I2C_BBPLL_HOSTID, @@ -280,9 +277,7 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { // switch clock source rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().xtal()); - rtc_cntl - .store5() - .modify(|_, w| w.scratch5().bits(value as u32)); + rtc_cntl.store5().modify(|_, w| w.scratch5().bits(value)); // lower the voltage rtc_cntl @@ -331,9 +326,7 @@ pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) { .reg() .modify(|_, w| w.dig_dbias_wak().variant(dbias as u8)); rtc_cntl.clk_conf().modify(|_, w| w.soc_clk_sel().pll()); - rtc_cntl - .store5() - .modify(|_, w| w.scratch5().bits(value as u32)); + rtc_cntl.store5().modify(|_, w| w.scratch5().bits(value)); esp32_update_cpu_freq(cpu_freq_mhz.mhz()); } diff --git a/esp-hal/src/clock/clocks_ll/esp32c2.rs b/esp-hal/src/clock/clocks_ll/esp32c2.rs index 1e7d698f4..4098e3617 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c2.rs @@ -49,9 +49,6 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl let dchgp: u32; let dcur: u32; let dbias: u32; - let i2c_bbpll_lref: u32; - let i2c_bbpll_div_7_0: u32; - let i2c_bbpll_dcur: u32; unsafe { let clear_reg_mask = |reg, mask: u32| { @@ -94,9 +91,10 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); - i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref; - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref; + let i2c_bbpll_div_7_0 = div7_0; + let i2c_bbpll_dcur = + (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); diff --git a/esp-hal/src/clock/clocks_ll/esp32c3.rs b/esp-hal/src/clock/clocks_ll/esp32c3.rs index 207b518e0..a943a28c5 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c3.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c3.rs @@ -53,9 +53,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo let dchgp: u32; let dcur: u32; let dbias: u32; - let i2c_bbpll_lref: u32; - let i2c_bbpll_div_7_0: u32; - let i2c_bbpll_dcur: u32; + unsafe { let clear_reg_mask = |reg, mask: u32| { (reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !mask) @@ -150,9 +148,10 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo regi2c_write!(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); } - i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref; - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + let i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | div_ref; + let i2c_bbpll_div_7_0 = div7_0; + let i2c_bbpll_dcur = + (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; regi2c_write!(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); diff --git a/esp-hal/src/clock/clocks_ll/esp32c6.rs b/esp-hal/src/clock/clocks_ll/esp32c6.rs index da2819a2b..df7846907 100644 --- a/esp-hal/src/clock/clocks_ll/esp32c6.rs +++ b/esp-hal/src/clock/clocks_ll/esp32c6.rs @@ -288,7 +288,7 @@ pub(crate) fn esp32c6_rtc_freq_to_pll_mhz_raw(cpu_clock_speed_mhz: u32) { pcr.cpu_freq_conf() .modify(|_, w| w.cpu_hs_120m_force().clear_bit()); - CpuClockSource::PLL.select(); + CpuClockSource::Pll.select(); ets_update_cpu_frequency(cpu_clock_speed_mhz); } @@ -378,7 +378,7 @@ const REGI2C_RTC_WR_CNTL_S: u8 = 24; const REGI2C_RTC_DATA_V: u8 = 0xFF; const REGI2C_RTC_DATA_S: u8 = 16; -const LP_I2C_ANA_MST_I2C0_CTRL_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x0; +const LP_I2C_ANA_MST_I2C0_CTRL_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE; const LP_I2C_ANA_MST_I2C0_BUSY: u32 = 1 << 25; const LP_I2C_ANA_MST_I2C0_DATA_REG: u32 = DR_REG_LP_I2C_ANA_MST_BASE + 0x8; @@ -463,8 +463,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l ); // Write the i2c bus register temp &= (!(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)); - temp = - ((data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32)) | temp; + temp |= (data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32); temp = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32) | ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32) | ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32) diff --git a/esp-hal/src/clock/clocks_ll/esp32h2.rs b/esp-hal/src/clock/clocks_ll/esp32h2.rs index f949183ad..d2fe6d87c 100644 --- a/esp-hal/src/clock/clocks_ll/esp32h2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32h2.rs @@ -65,7 +65,7 @@ const REGI2C_RTC_WR_CNTL_S: u8 = 24; const REGI2C_RTC_DATA_V: u8 = 0xFF; const REGI2C_RTC_DATA_S: u8 = 16; -const I2C_MST_I2C0_CTRL_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x0; +const I2C_MST_I2C0_CTRL_REG: u32 = DR_REG_I2C_ANA_MST_BASE; const REGI2C_RTC_BUSY: u32 = 1 << 25; pub(crate) fn esp32h2_rtc_bbpll_configure(_xtal_freq: XtalClock, _pll_freq: PllClock) { @@ -250,7 +250,7 @@ fn regi2c_enable_block(block: u8) { unsafe { (I2C_MST_ANA_CONF2_REG as *mut u32).write_volatile( // (1 << 18) - (I2C_MST_ANA_CONF2_REG as *mut u32).read_volatile() & !(I2C_MST_ANA_CONF2 as u32), + (I2C_MST_ANA_CONF2_REG as *mut u32).read_volatile() & !I2C_MST_ANA_CONF2, ); } @@ -339,8 +339,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l ); // Write the i2c bus register temp &= (!(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)); - temp = - ((data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32)) | temp; + temp |= (data as u32 & (!(0xFFFFFFFF << (msb as u32 - lsb as u32 + 1)))) << (lsb as u32); temp = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32) | ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32) | ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32) diff --git a/esp-hal/src/clock/clocks_ll/esp32s2.rs b/esp-hal/src/clock/clocks_ll/esp32s2.rs index 4761aeb0d..c689abeea 100644 --- a/esp-hal/src/clock/clocks_ll/esp32s2.rs +++ b/esp-hal/src/clock/clocks_ll/esp32s2.rs @@ -38,8 +38,6 @@ pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) { }); let value = (((80 * MHZ) >> 12) & UINT16_MAX) | ((((80 * MHZ) >> 12) & UINT16_MAX) << 16); - rtc_cntl - .store5() - .modify(|_, w| w.scratch5().bits(value as u32)); + rtc_cntl.store5().modify(|_, w| w.scratch5().bits(value)); } } diff --git a/esp-hal/src/delay.rs b/esp-hal/src/delay.rs index f1277c59f..ebbd7a464 100644 --- a/esp-hal/src/delay.rs +++ b/esp-hal/src/delay.rs @@ -61,7 +61,7 @@ impl embedded_hal_1::delay::DelayNs for Delay { } #[cfg(riscv)] -mod delay { +mod implementation { use super::*; use crate::{clock::Clocks, systimer::SystemTimer}; @@ -95,7 +95,7 @@ mod delay { } #[cfg(xtensa)] -mod delay { +mod implementation { use super::*; use crate::clock::Clocks; diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs index fe2cd7885..e84a4c4c7 100644 --- a/esp-hal/src/dma/mod.rs +++ b/esp-hal/src/dma/mod.rs @@ -390,6 +390,8 @@ where R::set_in_priority(priority); } + // TODO: Should this function be marked as `unsafe`, like `clippy` suggests? + #[allow(clippy::not_unsafe_ptr_arg_deref)] fn prepare_transfer_without_start( &mut self, descriptors: &mut [DmaDescriptor], @@ -500,7 +502,7 @@ where available: 0, last_seen_handled_descriptor_ptr: core::ptr::null_mut(), read_buffer_start: core::ptr::null_mut(), - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } @@ -898,7 +900,7 @@ where last_seen_handled_descriptor_ptr: core::ptr::null_mut(), buffer_start: core::ptr::null_mut(), buffer_len: 0, - _phantom: PhantomData::default(), + _phantom: PhantomData, } } } diff --git a/esp-hal/src/ecc.rs b/esp-hal/src/ecc.rs index bb1e39c35..5b8a815e9 100644 --- a/esp-hal/src/ecc.rs +++ b/esp-hal/src/ecc.rs @@ -771,21 +771,21 @@ impl<'d> Ecc<'d> { let mut tmp = [0_u8; 32]; - tmp[0..px.len()].copy_from_slice(&px); + tmp[0..px.len()].copy_from_slice(px); self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); - tmp[0..py.len()].copy_from_slice(&py); + .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8); + tmp[0..py.len()].copy_from_slice(py); self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); - tmp[0..qx.len()].copy_from_slice(&qx); + .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8); + tmp[0..qx.len()].copy_from_slice(qx); self.alignment_helper - .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), &mut tmp, 8); - tmp[0..qy.len()].copy_from_slice(&qy); + .volatile_write_regset(self.ecc.qx_mem(0).as_ptr(), &tmp, 8); + tmp[0..qy.len()].copy_from_slice(qy); self.alignment_helper - .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), &mut tmp, 8); - tmp[0..qz.len()].copy_from_slice(&qz); + .volatile_write_regset(self.ecc.qy_mem(0).as_ptr(), &tmp, 8); + tmp[0..qz.len()].copy_from_slice(qz); self.alignment_helper - .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), &mut tmp, 8); + .volatile_write_regset(self.ecc.qz_mem(0).as_ptr(), &tmp, 8); self.ecc.mult_conf().write(|w| unsafe { w.work_mode() @@ -863,12 +863,12 @@ impl<'d> Ecc<'d> { }; let mut tmp = [0_u8; 32]; - tmp[0..a.len()].copy_from_slice(&a); + tmp[0..a.len()].copy_from_slice(a); self.alignment_helper - .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &mut tmp, 8); - tmp[0..b.len()].copy_from_slice(&b); + .volatile_write_regset(self.ecc.px_mem(0).as_ptr(), &tmp, 8); + tmp[0..b.len()].copy_from_slice(b); self.alignment_helper - .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &mut tmp, 8); + .volatile_write_regset(self.ecc.py_mem(0).as_ptr(), &tmp, 8); self.ecc.mult_conf().write(|w| unsafe { w.work_mode() diff --git a/esp-hal/src/embassy/mod.rs b/esp-hal/src/embassy/mod.rs index c06635681..51018e4f7 100644 --- a/esp-hal/src/embassy/mod.rs +++ b/esp-hal/src/embassy/mod.rs @@ -130,7 +130,7 @@ pub fn init(clocks: &Clocks, td: time_driver::TimerType) { #[cfg(esp32c3)] crate::interrupt::enable(Interrupt::DMA_CH2, Priority::max()).unwrap(); - #[cfg(any(esp32))] + #[cfg(esp32)] crate::interrupt::enable(Interrupt::SPI1_DMA, Priority::max()).unwrap(); #[cfg(any(esp32, esp32s2))] crate::interrupt::enable(Interrupt::SPI2_DMA, Priority::max()).unwrap(); diff --git a/esp-hal/src/gpio.rs b/esp-hal/src/gpio.rs index a49b14487..e8e3df688 100644 --- a/esp-hal/src/gpio.rs +++ b/esp-hal/src/gpio.rs @@ -160,13 +160,16 @@ pub enum RtcFunction { pub trait RTCPin: Pin { #[cfg(xtensa)] fn rtc_number(&self) -> u8; + #[cfg(any(xtensa, esp32c6))] fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction); fn rtcio_pad_hold(&mut self, enable: bool); - // Unsafe because `level` needs to be a valid setting for the - // rtc_cntl.gpio_wakeup.gpio_pinX_int_type + /// # Safety + /// + /// The `level` argument needs to be a valid setting for the + /// `rtc_cntl.gpio_wakeup.gpio_pinX_int_type`. #[cfg(any(esp32c3, esp32c6))] unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8); } @@ -805,7 +808,7 @@ where #[cfg(not(any(esp32p4)))] unsafe { - (&*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| { + (*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| { w.int_ena() .bits(gpio_intr_enable(int_enable, nmi_enable)) .int_type() @@ -815,11 +818,11 @@ where }); } - #[cfg(any(esp32p4))] + #[cfg(esp32p4)] unsafe { // there is no NMI_ENABLE but P4 could trigger 4 interrupts // we'll only support GPIO_INT0 for now - (&*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| { + (*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| { w.int_ena() .bits(gpio_intr_enable(int_enable, nmi_enable)) .int_type() @@ -841,7 +844,7 @@ where fn unlisten(&mut self) { unsafe { - (&*GPIO::PTR) + (*GPIO::PTR) .pin(GPIONUM as usize) .modify(|_, w| w.int_ena().bits(0).int_type().bits(0).int_ena().bits(0)); } @@ -1493,11 +1496,11 @@ pub struct IO { impl IO { pub fn new(gpio: GPIO, io_mux: IO_MUX) -> Self { let pins = gpio.split(); - let io = IO { + + IO { _io_mux: io_mux, pins, - }; - io + } } } @@ -1542,16 +1545,16 @@ macro_rules! gpio { } $( - impl crate::gpio::GpioProperties for GpioPin { - type Bank = crate::gpio::[< Bank $bank GpioRegisterAccess >]; - type InterruptStatus = crate::gpio::[< InterruptStatusRegisterAccessBank $bank >]; + impl $crate::gpio::GpioProperties for GpioPin { + type Bank = $crate::gpio::[< Bank $bank GpioRegisterAccess >]; + type InterruptStatus = $crate::gpio::[< InterruptStatusRegisterAccessBank $bank >]; type Signals = [< Gpio $gpionum Signals >]; - type PinType = crate::gpio::[<$type PinType>]; + type PinType = $crate::gpio::[<$type PinType>]; } pub struct [] {} - impl crate::gpio::GpioSignal for [] { + impl $crate::gpio::GpioSignal for [] { fn output_signals() -> [Option; 6]{ #[allow(unused_mut)] let mut output_signals = [None,None,None,None,None,None]; @@ -1658,7 +1661,7 @@ macro_rules! rtc_pins { ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:ident, $rde:ident)? ) => { - impl crate::gpio::RTCPin for GpioPin + impl $crate::gpio::RTCPin for GpioPin { fn rtc_number(&self) -> u8 { $rtc_pin @@ -1666,14 +1669,15 @@ macro_rules! rtc_pins { /// Set the RTC properties of the pin. If `mux` is true then then pin is /// routed to RTC, when false it is routed to IO_MUX. - fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: crate::gpio::RtcFunction) { - use crate::peripherals::RTC_IO; + fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: $crate::gpio::RtcFunction) { + use $crate::peripherals::RTC_IO; + let rtcio = unsafe{ &*RTC_IO::ptr() }; #[cfg(esp32s3)] - unsafe { crate::peripherals::SENS::steal() }.sar_peri_clk_gate_conf().modify(|_,w| w.iomux_clk_en().set_bit()); + unsafe { $crate::peripherals::SENS::steal() }.sar_peri_clk_gate_conf().modify(|_,w| w.iomux_clk_en().set_bit()); #[cfg(esp32s2)] - unsafe { crate::peripherals::SENS::steal() }.sar_io_mux_conf().modify(|_,w| w.iomux_clk_gate_en().set_bit()); + unsafe { $crate::peripherals::SENS::steal() }.sar_io_mux_conf().modify(|_,w| w.iomux_clk_gate_en().set_bit()); // disable input paste::paste!{ @@ -1686,7 +1690,7 @@ macro_rules! rtc_pins { } fn rtcio_pad_hold(&mut self, enable: bool) { - let rtc_ctrl = unsafe { &*crate::peripherals::LPWR::PTR }; + let rtc_ctrl = unsafe { &*$crate::peripherals::LPWR::PTR }; #[cfg(esp32)] rtc_ctrl.hold_force().modify(|_, w| w.$hold().bit(enable)); @@ -1697,10 +1701,10 @@ macro_rules! rtc_pins { } $( - impl crate::gpio::RTCPinWithResistors for GpioPin + impl $crate::gpio::RTCPinWithResistors for GpioPin { fn rtcio_pullup(&mut self, enable: bool) { - let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR }; + let rtcio = unsafe { &*$crate::peripherals::RTC_IO::PTR }; paste::paste! { rtcio.$pin_reg.modify(|_, w| w.$rue().bit([< enable >])); @@ -1708,7 +1712,7 @@ macro_rules! rtc_pins { } fn rtcio_pulldown(&mut self, enable: bool) { - let rtcio = unsafe { &*crate::peripherals::RTC_IO::PTR }; + let rtcio = unsafe { &*$crate::peripherals::RTC_IO::PTR }; paste::paste! { rtcio.$pin_reg.modify(|_, w| w.$rde().bit([< enable >])); @@ -1718,14 +1722,14 @@ macro_rules! rtc_pins { #[cfg(not(esp32))] paste::paste!{ - impl crate::gpio::rtc_io::IntoLowPowerPin<$pin_num> for GpioPin { - fn into_low_power(mut self) -> crate::gpio::rtc_io::LowPowerPin { - use crate::gpio::RTCPin; + impl $crate::gpio::rtc_io::IntoLowPowerPin<$pin_num> for GpioPin { + fn into_low_power(mut self) -> $crate::gpio::rtc_io::LowPowerPin { + use $crate::gpio::RTCPin; - self.rtc_set_config(false, true, crate::gpio::RtcFunction::Rtc); + self.rtc_set_config(false, true, $crate::gpio::RtcFunction::Rtc); - crate::gpio::rtc_io::LowPowerPin { - private: core::marker::PhantomData::default(), + $crate::gpio::rtc_io::LowPowerPin { + private: core::marker::PhantomData, } } } @@ -1737,7 +1741,7 @@ macro_rules! rtc_pins { $( ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:ident, $rde:ident)? ) )+ ) => { $( - crate::gpio::rtc_pins!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue, $rde)?); + $crate::gpio::rtc_pins!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue, $rde)?); )+ }; } @@ -1749,9 +1753,9 @@ macro_rules! rtc_pins { ( $pin_num:expr ) => { - impl crate::gpio::RTCPin for GpioPin { + impl $crate::gpio::RTCPin for GpioPin { unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) { - let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() }; paste::paste! { rtc_cntl.gpio_wakeup().modify(|_, w| w.[< gpio_pin $pin_num _wakeup_enable >]().bit(wakeup)); rtc_cntl.gpio_wakeup().modify(|_, w| w.[< gpio_pin $pin_num _int_type >]().bits(level)); @@ -1759,28 +1763,28 @@ macro_rules! rtc_pins { } fn rtcio_pad_hold(&mut self, enable: bool) { - let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() }; paste::paste! { rtc_cntl.pad_hold().modify(|_, w| w.[< gpio_pin $pin_num _hold >]().bit(enable)); } } } - impl crate::gpio::RTCPinWithResistors for GpioPin { + impl $crate::gpio::RTCPinWithResistors for GpioPin { fn rtcio_pullup(&mut self, enable: bool) { - let io_mux = unsafe { &*crate::peripherals::IO_MUX::ptr() }; + let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() }; io_mux.gpio($pin_num).modify(|_, w| w.fun_wpu().bit(enable)); } fn rtcio_pulldown(&mut self, enable: bool) { - let io_mux = unsafe { &*crate::peripherals::IO_MUX::ptr() }; + let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() }; io_mux.gpio($pin_num).modify(|_, w| w.fun_wpd().bit(enable)); } } }; - ( $( $pin_num:expr )+ ) => { $( crate::gpio::rtc_pins!($pin_num); )+ }; + ( $( $pin_num:expr )+ ) => { $( $crate::gpio::rtc_pins!($pin_num); )+ }; } // Following code enables `into_analog` @@ -1810,7 +1814,8 @@ macro_rules! analog { )+ ) => { pub(crate) fn internal_into_analog(pin: u8) { - use crate::peripherals::RTC_IO; + use $crate::peripherals::RTC_IO; + let rtcio = unsafe{ &*RTC_IO::ptr() }; $crate::gpio::enable_iomux_clk_gate(); @@ -1864,8 +1869,8 @@ macro_rules! analog { $($pin_num:literal)+ ) => { pub(crate) fn internal_into_analog(pin: u8) { - use crate::peripherals::IO_MUX; - use crate::peripherals::GPIO; + use $crate::peripherals::IO_MUX; + use $crate::peripherals::GPIO; let io_mux = unsafe{ &*IO_MUX::PTR }; let gpio = unsafe{ &*GPIO::PTR }; @@ -2334,7 +2339,7 @@ pub mod rtc_io { self.pullup_enable(true); self.pulldown_enable(false); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2345,7 +2350,7 @@ pub mod rtc_io { self.pullup_enable(false); self.pulldown_enable(true); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2355,7 +2360,7 @@ pub mod rtc_io { self.pullup_enable(false); self.pulldown_enable(false); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2363,7 +2368,7 @@ pub mod rtc_io { pub fn into_push_pull_output(self) -> LowPowerPin, PIN> { self.output_enable(true); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } } @@ -2371,15 +2376,24 @@ pub mod rtc_io { #[cfg(esp32s3)] #[inline(always)] fn get_pin_reg(pin: u8) -> &'static crate::peripherals::rtc_io::TOUCH_PAD0 { - let rtc_io = unsafe { &*crate::peripherals::RTC_IO::PTR }; - unsafe { core::mem::transmute((rtc_io.touch_pad0().as_ptr()).add(pin as usize)) } + unsafe { + let rtc_io = &*crate::peripherals::RTC_IO::PTR; + let pin_ptr = (rtc_io.touch_pad0().as_ptr()).add(pin as usize); + + &*(pin_ptr + as *const esp32s3::generic::Reg) + } } #[cfg(esp32s2)] #[inline(always)] fn get_pin_reg(pin: u8) -> &'static crate::peripherals::rtc_io::TOUCH_PAD { - let rtc_io = unsafe { &*crate::peripherals::RTC_IO::PTR }; - unsafe { core::mem::transmute((rtc_io.touch_pad(0).as_ptr()).add(pin as usize)) } + unsafe { + let rtc_io = &*crate::peripherals::RTC_IO::PTR; + let pin_ptr = (rtc_io.touch_pad(0).as_ptr()).add(pin as usize); + + &*(pin_ptr as *const esp32s2::generic::Reg) + } } } @@ -2470,7 +2484,7 @@ pub mod lp_gpio { self.pullup_enable(true); self.pulldown_enable(false); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2481,7 +2495,7 @@ pub mod lp_gpio { self.pullup_enable(false); self.pulldown_enable(true); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2491,7 +2505,7 @@ pub mod lp_gpio { self.pullup_enable(false); self.pulldown_enable(false); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } @@ -2499,7 +2513,7 @@ pub mod lp_gpio { pub fn into_push_pull_output(self) -> LowPowerPin, PIN> { self.output_enable(true); LowPowerPin { - private: PhantomData::default(), + private: PhantomData, } } } @@ -2516,11 +2530,14 @@ pub mod lp_gpio { #[inline(always)] fn get_pin_reg(pin: u8) -> &'static crate::peripherals::lp_io::GPIO0 { - let lp_io = unsafe { &*crate::peripherals::LP_IO::PTR }; - // ideally we should change the SVD and make the GPIOx registers into an // array - unsafe { core::mem::transmute((lp_io.gpio0().as_ptr()).add(pin as usize)) } + unsafe { + let lp_io = &*crate::peripherals::LP_IO::PTR; + let pin_ptr = (lp_io.gpio0().as_ptr()).add(pin as usize); + + &*(pin_ptr as *const esp32c6::generic::Reg) + } } /// Configures a pin for use as a low power pin @@ -2536,18 +2553,18 @@ pub mod lp_gpio { ) => { paste::paste!{ $( - impl crate::gpio::lp_gpio::IntoLowPowerPin<$gpionum> for GpioPin { - fn into_low_power(self) -> crate::gpio::lp_gpio::LowPowerPin { - crate::gpio::lp_gpio::init_low_power_pin($gpionum); - crate::gpio::lp_gpio::LowPowerPin { - private: core::marker::PhantomData::default(), + impl $crate::gpio::lp_gpio::IntoLowPowerPin<$gpionum> for GpioPin { + fn into_low_power(self) -> $crate::gpio::lp_gpio::LowPowerPin { + $crate::gpio::lp_gpio::init_low_power_pin($gpionum); + $crate::gpio::lp_gpio::LowPowerPin { + private: core::marker::PhantomData, } } } - impl crate::gpio::RTCPin for GpioPin { + impl $crate::gpio::RTCPin for GpioPin { unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) { - let lp_io = &*crate::peripherals::LP_IO::ptr(); + let lp_io = &*$crate::peripherals::LP_IO::ptr(); lp_io.[< pin $gpionum >]().modify(|_, w| { w .[< lp_gpio $gpionum _wakeup_enable >]().bit(wakeup) @@ -2558,7 +2575,7 @@ pub mod lp_gpio { fn rtcio_pad_hold(&mut self, enable: bool) { let mask = 1 << $gpionum; unsafe { - let lp_aon = &*crate::peripherals::LP_AON::ptr(); + let lp_aon = &*$crate::peripherals::LP_AON::ptr(); lp_aon.gpio_hold0().modify(|r, w| { if enable { @@ -2572,11 +2589,11 @@ pub mod lp_gpio { /// Set the LP properties of the pin. If `mux` is true then then pin is /// routed to LP_IO, when false it is routed to IO_MUX. - fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: crate::gpio::RtcFunction) { + fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: $crate::gpio::RtcFunction) { let mask = 1 << $gpionum; unsafe { // Select LP_IO - let lp_aon = &*crate::peripherals::LP_AON::ptr(); + let lp_aon = &*$crate::peripherals::LP_AON::ptr(); lp_aon .gpio_mux() .modify(|r, w| { @@ -2588,7 +2605,7 @@ pub mod lp_gpio { }); // Configure input, function and select normal operation registers - let lp_io = &*crate::peripherals::LP_IO::ptr(); + let lp_io = &*$crate::peripherals::LP_IO::ptr(); lp_io.[< gpio $gpionum >]().modify(|_, w| { w .[< lp_gpio $gpionum _slp_sel >]().bit(false) @@ -2599,14 +2616,14 @@ pub mod lp_gpio { } } - impl crate::gpio::RTCPinWithResistors for GpioPin { + impl $crate::gpio::RTCPinWithResistors for GpioPin { fn rtcio_pullup(&mut self, enable: bool) { - let lp_io = unsafe { &*crate::peripherals::LP_IO::ptr() }; + let lp_io = unsafe { &*$crate::peripherals::LP_IO::ptr() }; lp_io.[< gpio $gpionum >]().modify(|_, w| w.[< lp_gpio $gpionum _fun_wpu >]().bit(enable)); } fn rtcio_pulldown(&mut self, enable: bool) { - let lp_io = unsafe { &*crate::peripherals::LP_IO::ptr() }; + let lp_io = unsafe { &*$crate::peripherals::LP_IO::ptr() }; lp_io.[< gpio $gpionum >]().modify(|_, w| w.[< lp_gpio $gpionum _fun_wpd >]().bit(enable)); } } @@ -2740,7 +2757,7 @@ mod asynch { handle_gpio_interrupt(); } - #[cfg(any(esp32p4))] + #[cfg(esp32p4)] #[interrupt] unsafe fn GPIO_INT0() { handle_gpio_interrupt(); diff --git a/esp-hal/src/i2c.rs b/esp-hal/src/i2c.rs index 51372d723..a34aed315 100644 --- a/esp-hal/src/i2c.rs +++ b/esp-hal/src/i2c.rs @@ -908,7 +908,6 @@ pub trait Instance { let sclk_freq: u32 = source_clk / clkm_div; let half_cycle: u32 = sclk_freq / bus_freq / 2; // SCL - let clkm_div = clkm_div; let scl_low = half_cycle; // default, scl_wait_high < scl_high // Make 80KHz as a boundary here, because when working at lower frequency, too @@ -1066,6 +1065,7 @@ pub trait Instance { else { // timeout // FIXME: Enable timout for other chips! + #[allow(clippy::useless_conversion)] self.register_block() .to() .write(|w| w.time_out_en().bit(time_out_en) diff --git a/esp-hal/src/i2s.rs b/esp-hal/src/i2s.rs index 9d439e9de..9f0b3465d 100644 --- a/esp-hal/src/i2s.rs +++ b/esp-hal/src/i2s.rs @@ -503,11 +503,11 @@ where Self { i2s_tx: TxCreator { - register_access: PhantomData::default(), + register_access: PhantomData, tx_channel: channel.tx, }, i2s_rx: RxCreator { - register_access: PhantomData::default(), + register_access: PhantomData, rx_channel: channel.rx, }, } @@ -589,7 +589,7 @@ where { fn new(tx_channel: CH::Tx<'d>) -> Self { Self { - register_access: PhantomData::default(), + register_access: PhantomData, tx_channel, } } @@ -692,7 +692,7 @@ where self.write_bytes(unsafe { core::slice::from_raw_parts( words as *const _ as *const u8, - words.len() * core::mem::size_of::(), + core::mem::size_of_val(words), ) }) } @@ -748,7 +748,7 @@ where { fn new(rx_channel: CH::Rx<'d>) -> Self { Self { - register_access: PhantomData::default(), + register_access: PhantomData, rx_channel, } } @@ -863,14 +863,14 @@ where W: AcceptedWord, { fn read(&mut self, words: &mut [W]) -> Result<(), Error> { - if words.len() * core::mem::size_of::() > 4096 || words.len() == 0 { + if core::mem::size_of_val(words) > 4096 || words.is_empty() { return Err(Error::IllegalArgument); } self.read_bytes(unsafe { core::slice::from_raw_parts_mut( words as *mut _ as *mut u8, - words.len() * core::mem::size_of::(), + core::mem::size_of_val(words), ) }) } @@ -1248,35 +1248,33 @@ mod private { clkm_div_y = 0; clkm_div_z = 0; clkm_div_yn1 = 1; - } else { - if clock_settings.numerator > clock_settings.denominator / 2 { - clkm_div_x = clock_settings - .denominator - .overflowing_div( - clock_settings - .denominator - .overflowing_sub(clock_settings.numerator) - .0, - ) - .0 - .overflowing_sub(1) - .0; - clkm_div_y = clock_settings.denominator - % (clock_settings + } else if clock_settings.numerator > clock_settings.denominator / 2 { + clkm_div_x = clock_settings + .denominator + .overflowing_div( + clock_settings .denominator .overflowing_sub(clock_settings.numerator) - .0); - clkm_div_z = clock_settings + .0, + ) + .0 + .overflowing_sub(1) + .0; + clkm_div_y = clock_settings.denominator + % (clock_settings .denominator .overflowing_sub(clock_settings.numerator) - .0; - clkm_div_yn1 = 1; - } else { - clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1; - clkm_div_y = clock_settings.denominator % clock_settings.numerator; - clkm_div_z = clock_settings.numerator; - clkm_div_yn1 = 0; - } + .0); + clkm_div_z = clock_settings + .denominator + .overflowing_sub(clock_settings.numerator) + .0; + clkm_div_yn1 = 1; + } else { + clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1; + clkm_div_y = clock_settings.denominator % clock_settings.numerator; + clkm_div_z = clock_settings.numerator; + clkm_div_yn1 = 0; } i2s.tx_clkm_div_conf().modify(|_, w| { @@ -1285,7 +1283,7 @@ mod private { .tx_clkm_div_y() .variant(clkm_div_y as u16) .tx_clkm_div_yn1() - .variant(if clkm_div_yn1 != 0 { true } else { false }) + .variant(clkm_div_yn1 != 0) .tx_clkm_div_z() .variant(clkm_div_z as u16) }); @@ -1312,7 +1310,7 @@ mod private { .rx_clkm_div_y() .variant(clkm_div_y as u16) .rx_clkm_div_yn1() - .variant(if clkm_div_yn1 != 0 { true } else { false }) + .variant(clkm_div_yn1 != 0) .rx_clkm_div_z() .variant(clkm_div_z as u16) }); @@ -1349,35 +1347,33 @@ mod private { clkm_div_y = 0; clkm_div_z = 0; clkm_div_yn1 = 1; - } else { - if clock_settings.numerator > clock_settings.denominator / 2 { - clkm_div_x = clock_settings - .denominator - .overflowing_div( - clock_settings - .denominator - .overflowing_sub(clock_settings.numerator) - .0, - ) - .0 - .overflowing_sub(1) - .0; - clkm_div_y = clock_settings.denominator - % (clock_settings + } else if clock_settings.numerator > clock_settings.denominator / 2 { + clkm_div_x = clock_settings + .denominator + .overflowing_div( + clock_settings .denominator .overflowing_sub(clock_settings.numerator) - .0); - clkm_div_z = clock_settings + .0, + ) + .0 + .overflowing_sub(1) + .0; + clkm_div_y = clock_settings.denominator + % (clock_settings .denominator .overflowing_sub(clock_settings.numerator) - .0; - clkm_div_yn1 = 1; - } else { - clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1; - clkm_div_y = clock_settings.denominator % clock_settings.numerator; - clkm_div_z = clock_settings.numerator; - clkm_div_yn1 = 0; - } + .0); + clkm_div_z = clock_settings + .denominator + .overflowing_sub(clock_settings.numerator) + .0; + clkm_div_yn1 = 1; + } else { + clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1; + clkm_div_y = clock_settings.denominator % clock_settings.numerator; + clkm_div_z = clock_settings.numerator; + clkm_div_yn1 = 0; } pcr.i2s_tx_clkm_div_conf().modify(|_, w| { @@ -1386,7 +1382,7 @@ mod private { .i2s_tx_clkm_div_y() .variant(clkm_div_y as u16) .i2s_tx_clkm_div_yn1() - .variant(if clkm_div_yn1 != 0 { true } else { false }) + .variant(clkm_div_yn1 != 0) .i2s_tx_clkm_div_z() .variant(clkm_div_z as u16) }); @@ -1417,7 +1413,7 @@ mod private { .i2s_rx_clkm_div_y() .variant(clkm_div_y as u16) .i2s_rx_clkm_div_yn1() - .variant(if clkm_div_yn1 != 0 { true } else { false }) + .variant(clkm_div_yn1 != 0) .i2s_rx_clkm_div_z() .variant(clkm_div_z as u16) }); @@ -1446,6 +1442,8 @@ mod private { fn configure(_standard: &Standard, data_format: &DataFormat) { let i2s = Self::register_block(); + + #[allow(clippy::useless_conversion)] i2s.tx_conf1().modify(|_, w| { w.tx_tdm_ws_width() .variant((data_format.channel_bits() - 1).into()) @@ -1520,6 +1518,7 @@ mod private { .clear_bit() }); + #[allow(clippy::useless_conversion)] i2s.rx_conf1().modify(|_, w| { w.rx_tdm_ws_width() .variant((data_format.channel_bits() - 1).into()) diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index 44d37838d..a9fa1e458 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -284,7 +284,7 @@ where data: &[P::Word], ) -> Result<(), DmaError> { self.setup_send(cmd.into(), dummy); - self.start_write_bytes_dma(data.as_ptr() as _, data.len() * size_of::())?; + self.start_write_bytes_dma(data.as_ptr() as _, core::mem::size_of_val(data))?; self.start_send(); let dma_int_raw = self.lcd_cam.lc_dma_int_raw(); diff --git a/esp-hal/src/ledc/channel.rs b/esp-hal/src/ledc/channel.rs index 93947b715..da5f1d31a 100644 --- a/esp-hal/src/ledc/channel.rs +++ b/esp-hal/src/ledc/channel.rs @@ -184,7 +184,7 @@ where } let duty_range = 2u32.pow(duty_exp); - let duty_value = (duty_range * duty_pct as u32) as u32 / 100; + let duty_value = (duty_range * duty_pct as u32) / 100; if duty_pct > 100u8 { // duty_pct greater than 100% @@ -238,8 +238,8 @@ where } let duty_range = (1u32 << duty_exp) - 1; - let start_duty_value = (duty_range * start_duty_pct as u32) as u32 / 100; - let end_duty_value = (duty_range * end_duty_pct as u32) as u32 / 100; + let start_duty_value = (duty_range * start_duty_pct as u32) / 100; + let end_duty_value = (duty_range * end_duty_pct as u32) / 100; // NB: since we do the multiplication first here, there's no loss of // precision from using milliseconds instead of (e.g.) nanoseconds. diff --git a/esp-hal/src/ledc/timer.rs b/esp-hal/src/ledc/timer.rs index d7cccec79..a6b613a9e 100644 --- a/esp-hal/src/ledc/timer.rs +++ b/esp-hal/src/ledc/timer.rs @@ -185,10 +185,10 @@ where // APB_CLK results in divisor which too high. Try using REF_TICK as clock // source. self.use_ref_tick = true; - divisor = ((1_000_000 as u64) << 8) / frequency as u64 / precision as u64; + divisor = (1_000_000u64 << 8) / frequency as u64 / precision as u64; } - if divisor >= LEDC_TIMER_DIV_NUM_MAX || divisor < 256 { + if !(256..LEDC_TIMER_DIV_NUM_MAX).contains(&divisor) { return Err(Error::Divisor); } diff --git a/esp-hal/src/lib.rs b/esp-hal/src/lib.rs index be424eff2..80eb5474f 100644 --- a/esp-hal/src/lib.rs +++ b/esp-hal/src/lib.rs @@ -25,6 +25,7 @@ //! [esp32s3-hal]: https://github.com/esp-rs/esp-hal/tree/main/esp32s3-hal #![no_std] +#![allow(asm_sub_register)] #![cfg_attr(xtensa, feature(asm_experimental_arch))] #![cfg_attr( feature = "async", @@ -338,7 +339,7 @@ mod critical_section_impl { const UNUSED_THREAD_ID_VALUE: usize = 0x0001; fn thread_id() -> usize { - crate::get_raw_core() as usize + crate::get_raw_core() } pub(super) static MULTICORE_LOCK: ReentrantMutex = ReentrantMutex::new(); diff --git a/esp-hal/src/mcpwm/mod.rs b/esp-hal/src/mcpwm/mod.rs index 4794fe15a..4573881bb 100644 --- a/esp-hal/src/mcpwm/mod.rs +++ b/esp-hal/src/mcpwm/mod.rs @@ -282,7 +282,7 @@ impl<'a> PeripheralClockConfig<'a> { pub struct FrequencyError; /// A MCPWM peripheral -pub unsafe trait PwmPeripheral: Deref { +pub trait PwmPeripheral: Deref + private::Sealed { /// Enable peripheral fn enable(); /// Get a pointer to the peripheral RegisterBlock @@ -292,7 +292,7 @@ pub unsafe trait PwmPeripheral: Deref { } #[cfg(mcpwm0)] -unsafe impl PwmPeripheral for crate::peripherals::MCPWM0 { +impl PwmPeripheral for crate::peripherals::MCPWM0 { fn enable() { PeripheralClockControl::enable(PeripheralEnable::Mcpwm0) } @@ -315,7 +315,7 @@ unsafe impl PwmPeripheral for crate::peripherals::MCPWM0 { } #[cfg(mcpwm1)] -unsafe impl PwmPeripheral for crate::peripherals::MCPWM1 { +impl PwmPeripheral for crate::peripherals::MCPWM1 { fn enable() { PeripheralClockControl::enable(PeripheralEnable::Mcpwm1) } @@ -336,3 +336,13 @@ unsafe impl PwmPeripheral for crate::peripherals::MCPWM1 { } } } + +mod private { + pub trait Sealed {} +} + +#[cfg(mcpwm0)] +impl private::Sealed for crate::peripherals::MCPWM0 {} + +#[cfg(mcpwm1)] +impl private::Sealed for crate::peripherals::MCPWM1 {} diff --git a/esp-hal/src/mcpwm/operator.rs b/esp-hal/src/mcpwm/operator.rs index cd981aa8c..bf7a5336d 100644 --- a/esp-hal/src/mcpwm/operator.rs +++ b/esp-hal/src/mcpwm/operator.rs @@ -34,6 +34,7 @@ pub struct DeadTimeCfg { falling_edge_delay: u16, } +#[allow(clippy::unusual_byte_groupings)] impl DeadTimeCfg { // NOTE: it's a bit difficult to make this typestate // due to the different interconnections (FED/RED vs PWMxA/PWMxB) and @@ -145,7 +146,7 @@ impl DeadTimeCfg { fn dt_cfg() -> &'static crate::peripherals::mcpwm0::DB0_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.db0_cfg(), + 0 => block.db0_cfg(), 1 => unsafe { &*(&block.db1_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.db2_cfg() as *const _ as *const _) }, _ => unreachable!(), @@ -155,7 +156,7 @@ fn dt_cfg() -> &'static crate::peripherals::mc fn dt_fed() -> &'static crate::peripherals::mcpwm0::DB0_FED_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.db0_fed_cfg(), + 0 => block.db0_fed_cfg(), 1 => unsafe { &*(&block.db1_fed_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.db2_fed_cfg() as *const _ as *const _) }, _ => unreachable!(), @@ -165,7 +166,7 @@ fn dt_fed() -> &'static crate::peripherals::mc fn dt_red() -> &'static crate::peripherals::mcpwm0::DB0_RED_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.db0_red_cfg(), + 0 => block.db0_red_cfg(), 1 => unsafe { &*(&block.db1_red_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.db2_red_cfg() as *const _ as *const _) }, _ => unreachable!(), @@ -178,7 +179,7 @@ fn dt_red() -> &'static crate::peripherals::mc fn dt_cfg() -> &'static crate::peripherals::mcpwm0::DT0_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.dt0_cfg(), + 0 => block.dt0_cfg(), 1 => unsafe { &*(&block.dt1_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.dt2_cfg() as *const _ as *const _) }, _ => unreachable!(), @@ -189,7 +190,7 @@ fn dt_cfg() -> &'static crate::peripherals::mc fn dt_fed() -> &'static crate::peripherals::mcpwm0::DT0_FED_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.dt0_fed_cfg(), + 0 => block.dt0_fed_cfg(), 1 => unsafe { &*(&block.dt1_fed_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.dt2_fed_cfg() as *const _ as *const _) }, _ => unreachable!(), @@ -199,7 +200,7 @@ fn dt_fed() -> &'static crate::peripherals::mc fn dt_red() -> &'static crate::peripherals::mcpwm0::DT0_RED_CFG { let block = unsafe { &*PWM::block() }; match OP { - 0 => &block.dt0_red_cfg(), + 0 => block.dt0_red_cfg(), 1 => unsafe { &*(&block.dt1_red_cfg() as *const _ as *const _) }, 2 => unsafe { &*(&block.dt2_red_cfg() as *const _ as *const _) }, _ => unreachable!(), diff --git a/esp-hal/src/mcpwm/timer.rs b/esp-hal/src/mcpwm/timer.rs index 3bde0a6e2..5b92c5798 100644 --- a/esp-hal/src/mcpwm/timer.rs +++ b/esp-hal/src/mcpwm/timer.rs @@ -155,7 +155,7 @@ impl Timer { // The CFG0 registers are identical for all timers so we can pretend they're // TIMER0_CFG0 match TIM { - 0 => &block.timer0_cfg0(), + 0 => block.timer0_cfg0(), 1 => unsafe { &*(&block.timer1_cfg0() as *const _ as *const _) }, 2 => unsafe { &*(&block.timer2_cfg0() as *const _ as *const _) }, _ => unreachable!(), @@ -171,7 +171,7 @@ impl Timer { // The CFG1 registers are identical for all timers so we can pretend they're // TIMER0_CFG1 match TIM { - 0 => &block.timer0_cfg1(), + 0 => block.timer0_cfg1(), 1 => unsafe { &*(&block.timer1_cfg1() as *const _ as *const _) }, 2 => unsafe { &*(&block.timer2_cfg1() as *const _ as *const _) }, _ => unreachable!(), diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs index 777eb1e4f..48271641d 100644 --- a/esp-hal/src/parl_io.rs +++ b/esp-hal/src/parl_io.rs @@ -1115,10 +1115,7 @@ where } } -fn internal_init<'d, CH>( - dma_channel: &mut Channel<'d, CH>, - frequency: HertzU32, -) -> Result<(), Error> +fn internal_init(dma_channel: &mut Channel<'_, CH>, frequency: HertzU32) -> Result<(), Error> where CH: ChannelTypes, CH::P: ParlIoPeripheral, @@ -1196,7 +1193,7 @@ where }) } - fn start_write_bytes_dma<'w>(&mut self, ptr: *const u8, len: usize) -> Result<(), Error> { + fn start_write_bytes_dma(&mut self, ptr: *const u8, len: usize) -> Result<(), Error> { let pcr = unsafe { &*crate::peripherals::PCR::PTR }; pcr.parl_clk_tx_conf() .modify(|_, w| w.parl_tx_rst_en().set_bit()); @@ -1306,10 +1303,8 @@ where { let (ptr, len) = unsafe { words.write_buffer() }; - if !Instance::is_suc_eof_generated_externally() { - if len > MAX_DMA_SIZE { - return Err(Error::MaxDmaTransferSizeExceeded); - } + if !Instance::is_suc_eof_generated_externally() && len > MAX_DMA_SIZE { + return Err(Error::MaxDmaTransferSizeExceeded); } self.start_receive_bytes_dma(ptr, len)?; @@ -1320,7 +1315,7 @@ where }) } - fn start_receive_bytes_dma<'w>(&mut self, ptr: *mut u8, len: usize) -> Result<(), Error> { + fn start_receive_bytes_dma(&mut self, ptr: *mut u8, len: usize) -> Result<(), Error> { let pcr = unsafe { &*crate::peripherals::PCR::PTR }; pcr.parl_clk_rx_conf() .modify(|_, w| w.parl_rx_rst_en().set_bit()); @@ -1383,7 +1378,7 @@ where unsafe { let buffer = core::ptr::read(&self.buffer); let payload = core::ptr::read(&self.instance); - let err = (&self).instance.rx_channel.has_error(); + let err = self.instance.rx_channel.has_error(); mem::forget(self); if err { Err((DmaError::DescriptorError, buffer, payload)) @@ -1659,7 +1654,7 @@ mod private { reg_block .tx_cfg0() - .modify(|_, w| w.tx_bytelen().variant(len as u16)); + .modify(|_, w| w.tx_bytelen().variant(len)); } pub fn is_tx_ready() -> bool { @@ -1731,7 +1726,7 @@ mod private { reg_block .rx_cfg0() - .modify(|_, w| w.rx_data_bytelen().variant(len as u16)); + .modify(|_, w| w.rx_data_bytelen().variant(len)); } pub fn set_rx_sample_mode(sample_mode: SampleMode) { diff --git a/esp-hal/src/peripheral.rs b/esp-hal/src/peripheral.rs index 53e85c385..135648af3 100644 --- a/esp-hal/src/peripheral.rs +++ b/esp-hal/src/peripheral.rs @@ -231,7 +231,7 @@ mod peripheral_macros { mod peripherals { pub use super::pac::*; $( - crate::create_peripheral!($(#[$cfg])? $name <= $from_pac); + $crate::create_peripheral!($(#[$cfg])? $name <= $from_pac); )* } @@ -318,7 +318,7 @@ mod peripheral_macros { } } - impl crate::peripheral::Peripheral for $name { + impl $crate::peripheral::Peripheral for $name { type P = $name; #[inline] @@ -327,7 +327,7 @@ mod peripheral_macros { } } - impl crate::peripheral::sealed::Sealed for $name {} + impl $crate::peripheral::sealed::Sealed for $name {} }; ($(#[$cfg:meta])? $name:ident <= $base:ident) => { $(#[$cfg])? @@ -372,7 +372,7 @@ mod peripheral_macros { } } - impl crate::peripheral::Peripheral for $name { + impl $crate::peripheral::Peripheral for $name { type P = $name; #[inline] @@ -381,7 +381,7 @@ mod peripheral_macros { } } - impl crate::peripheral::sealed::Sealed for $name {} + impl $crate::peripheral::sealed::Sealed for $name {} }; } } diff --git a/esp-hal/src/reg_access.rs b/esp-hal/src/reg_access.rs index 6c8bd08e9..0336faa41 100644 --- a/esp-hal/src/reg_access.rs +++ b/esp-hal/src/reg_access.rs @@ -161,7 +161,7 @@ impl AlignmentHelper { (nsrc.len() / U32_ALIGN_SIZE) * U32_ALIGN_SIZE, )); - if to_write.len() > 0 { + if !to_write.is_empty() { for (i, v) in to_write.chunks_exact(U32_ALIGN_SIZE).enumerate() { unsafe { dst_ptr @@ -175,17 +175,14 @@ impl AlignmentHelper { // next write Generally this applies when (src/4*4) != src let was_bounded = (offset + cursor + to_write.len() / U32_ALIGN_SIZE) == dst_bound; - if remaining.len() > 0 && remaining.len() < 4 { - for i in 0..remaining.len() { - self.buf[i] = remaining[i]; - } - + if !remaining.is_empty() && remaining.len() < 4 { + self.buf[..remaining.len()].copy_from_slice(remaining); self.buf_fill = remaining.len(); return (&[], was_bounded); } - return (remaining, was_bounded); + (remaining, was_bounded) } #[allow(dead_code)] @@ -193,7 +190,7 @@ impl AlignmentHelper { assert!(dst_bound > 0); assert!(src.len() <= dst_bound * 4); - if src.len() > 0 { + if !src.is_empty() { for (i, v) in src.chunks_exact(U32_ALIGN_SIZE).enumerate() { unsafe { dst_ptr diff --git a/esp-hal/src/rmt.rs b/esp-hal/src/rmt.rs index 6861324a2..425ad5ebe 100644 --- a/esp-hal/src/rmt.rs +++ b/esp-hal/src/rmt.rs @@ -370,7 +370,7 @@ where } } - self.index = self.index + constants::RMT_CHANNEL_RAM_SIZE / 2; + self.index += constants::RMT_CHANNEL_RAM_SIZE / 2; } else { break; } @@ -527,7 +527,7 @@ mod impl_for_chip { super::chip_specific::impl_rx_channel!(Channel, RMT_SIG_1, 3, 1); } -#[cfg(any(esp32))] +#[cfg(esp32)] mod impl_for_chip { use super::private::CreateInstance; use crate::peripheral::{Peripheral, PeripheralRef}; @@ -602,7 +602,7 @@ mod impl_for_chip { super::chip_specific::impl_rx_channel!(Channel, RMT_SIG_7, 7); } -#[cfg(any(esp32s2))] +#[cfg(esp32s2)] mod impl_for_chip { use super::private::CreateInstance; use crate::peripheral::{Peripheral, PeripheralRef}; @@ -653,7 +653,7 @@ mod impl_for_chip { super::chip_specific::impl_rx_channel!(Channel, RMT_SIG_3, 3); } -#[cfg(any(esp32s3))] +#[cfg(esp32s3)] mod impl_for_chip { use super::private::CreateInstance; use crate::peripheral::{Peripheral, PeripheralRef}; @@ -722,10 +722,7 @@ pub trait TxChannel: private::TxChannelInternal { /// This returns a [`SingleShotTxTransaction`] which can be used to wait for /// the transaction to complete and get back the channel for further /// use. - fn transmit<'a, T: Into + Copy>( - self, - data: &'a [T], - ) -> SingleShotTxTransaction<'a, Self, T> + fn transmit + Copy>(self, data: &[T]) -> SingleShotTxTransaction where Self: Sized, { @@ -741,9 +738,9 @@ pub trait TxChannel: private::TxChannelInternal { /// This returns a [`ContinuousTxTransaction`] which can be used to stop the /// ongoing transmission and get back the channel for further use. /// The length of sequence cannot exceed the size of the allocated RMT RAM. - fn transmit_continuously<'a, T: Into + Copy>( + fn transmit_continuously + Copy>( self, - data: &'a [T], + data: &[T], ) -> Result, Error> where Self: Sized, @@ -754,10 +751,10 @@ pub trait TxChannel: private::TxChannelInternal { /// Like [`Self::transmit_continuously`] but also sets a loop count. /// [`ContinuousTxTransaction`] can be used to check if the loop count is /// reached. - fn transmit_continuously_with_loopcount<'a, T: Into + Copy>( + fn transmit_continuously_with_loopcount + Copy>( self, loopcount: u16, - data: &'a [T], + data: &[T], ) -> Result, Error> where Self: Sized, @@ -817,10 +814,7 @@ pub trait RxChannel: private::RxChannelInternal { /// This returns a [RxTransaction] which can be used to wait for receive to /// complete and get back the channel for further use. /// The length of the received data cannot exceed the allocated RMT RAM. - fn receive<'a, T: From + Copy>( - self, - data: &'a mut [T], - ) -> Result, Error> + fn receive + Copy>(self, data: &mut [T]) -> Result, Error> where Self: Sized, { @@ -1107,7 +1101,7 @@ pub mod asynch { Event::Error, ); } - #[cfg(any(esp32))] + #[cfg(esp32)] 4 => { as super::private::TxChannelInternal>::unlisten_interrupt( Event::End, diff --git a/esp-hal/src/rng.rs b/esp-hal/src/rng.rs index c3d9bd9fe..2518e1311 100644 --- a/esp-hal/src/rng.rs +++ b/esp-hal/src/rng.rs @@ -135,6 +135,7 @@ impl RngCore for Rng { fn try_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), rand_core::Error> { // Similar implementation as fill_bytes, but encapsulated in a Result - Ok(self.fill_bytes(dest)) + self.fill_bytes(dest); + Ok(()) } } diff --git a/esp-hal/src/rom/md5.rs b/esp-hal/src/rom/md5.rs index e760473cc..b3d85a37e 100644 --- a/esp-hal/src/rom/md5.rs +++ b/esp-hal/src/rom/md5.rs @@ -154,6 +154,12 @@ impl Context { } } +impl Default for Context { + fn default() -> Self { + Self::new() + } +} + /// Compute a full digest from a single buffer #[inline] pub fn compute>(data: T) -> Digest { diff --git a/esp-hal/src/rom/mod.rs b/esp-hal/src/rom/mod.rs index ea486932f..8137ca028 100644 --- a/esp-hal/src/rom/mod.rs +++ b/esp-hal/src/rom/mod.rs @@ -49,7 +49,7 @@ macro_rules! regi2c_write { paste::paste! { #[allow(unused_unsafe)] unsafe { - crate::rom::rom_i2c_writeReg( + $crate::rom::rom_i2c_writeReg( $block as u32, [<$block _HOSTID>] as u32, $reg_add as u32, @@ -67,7 +67,7 @@ macro_rules! regi2c_write_mask { paste::paste! { #[allow(unused_unsafe)] unsafe { - crate::rom::rom_i2c_writeReg_Mask( + $crate::rom::rom_i2c_writeReg_Mask( $block as u32, [<$block _HOSTID>] as u32, $reg_add as u32, diff --git a/esp-hal/src/rsa/esp32.rs b/esp-hal/src/rsa/esp32.rs index f18b1d0f9..8bea889c0 100644 --- a/esp-hal/src/rsa/esp32.rs +++ b/esp-hal/src/rsa/esp32.rs @@ -26,9 +26,7 @@ impl<'d> Rsa<'d> { } pub(super) fn write_multi_mode(&mut self, mode: u32) { - self.rsa - .mult_mode() - .write(|w| unsafe { w.bits(mode as u32) }); + self.rsa.mult_mode().write(|w| unsafe { w.bits(mode) }); } pub(super) fn write_modexp_mode(&mut self, mode: u32) { @@ -54,21 +52,13 @@ impl<'d> Rsa<'d> { } unsafe fn write_multi_operand_a(&mut self, operand_a: &[u32; N]) { - copy_nonoverlapping( - operand_a.as_ptr(), - self.rsa.x_mem(0).as_ptr() as *mut u32, - N, - ); + copy_nonoverlapping(operand_a.as_ptr(), self.rsa.x_mem(0).as_ptr(), N); write_bytes(self.rsa.x_mem(0).as_ptr().add(N), 0, N); } unsafe fn write_multi_operand_b(&mut self, operand_b: &[u32; N]) { write_bytes(self.rsa.z_mem(0).as_ptr(), 0, N); - copy_nonoverlapping( - operand_b.as_ptr(), - self.rsa.z_mem(0).as_ptr().add(N) as *mut u32, - N, - ); + copy_nonoverlapping(operand_b.as_ptr(), self.rsa.z_mem(0).as_ptr().add(N), N); } } diff --git a/esp-hal/src/rsa/esp32cX.rs b/esp-hal/src/rsa/esp32cX.rs index fcbd2d829..5b2a216f5 100644 --- a/esp-hal/src/rsa/esp32cX.rs +++ b/esp-hal/src/rsa/esp32cX.rs @@ -31,7 +31,7 @@ impl<'d> Rsa<'d> { } fn write_mode(&mut self, mode: u32) { - self.rsa.mode().write(|w| unsafe { w.bits(mode as u32) }); + self.rsa.mode().write(|w| unsafe { w.bits(mode) }); } /// Enables/disables search acceleration, when enabled it would increases @@ -106,11 +106,7 @@ impl<'d> Rsa<'d> { } unsafe fn write_multi_operand_b(&mut self, operand_b: &[u32; N]) { - copy_nonoverlapping( - operand_b.as_ptr(), - self.rsa.z_mem(0).as_ptr().add(N) as *mut u32, - N, - ); + copy_nonoverlapping(operand_b.as_ptr(), self.rsa.z_mem(0).as_ptr().add(N), N); } } diff --git a/esp-hal/src/rsa/esp32sX.rs b/esp-hal/src/rsa/esp32sX.rs index d1797983b..b3269c0e7 100644 --- a/esp-hal/src/rsa/esp32sX.rs +++ b/esp-hal/src/rsa/esp32sX.rs @@ -37,7 +37,7 @@ impl<'d> Rsa<'d> { } fn write_mode(&mut self, mode: u32) { - self.rsa.mode().write(|w| unsafe { w.bits(mode as u32) }); + self.rsa.mode().write(|w| unsafe { w.bits(mode) }); } /// Enables/disables search acceleration, when enabled it would increases @@ -112,11 +112,7 @@ impl<'d> Rsa<'d> { } unsafe fn write_multi_operand_b(&mut self, operand_b: &[u32; N]) { - copy_nonoverlapping( - operand_b.as_ptr(), - self.rsa.z_mem(0).as_ptr().add(N) as *mut u32, - N, - ); + copy_nonoverlapping(operand_b.as_ptr(), self.rsa.z_mem(0).as_ptr().add(N), N); } } diff --git a/esp-hal/src/rsa/mod.rs b/esp-hal/src/rsa/mod.rs index da353a0fc..f8f3981a3 100644 --- a/esp-hal/src/rsa/mod.rs +++ b/esp-hal/src/rsa/mod.rs @@ -95,15 +95,11 @@ impl<'d> Rsa<'d> { } unsafe fn write_operand_b(&mut self, operand_b: &[u32; N]) { - copy_nonoverlapping( - operand_b.as_ptr(), - self.rsa.y_mem(0).as_ptr() as *mut u32, - N, - ); + copy_nonoverlapping(operand_b.as_ptr(), self.rsa.y_mem(0).as_ptr(), N); } unsafe fn write_modulus(&mut self, modulus: &[u32; N]) { - copy_nonoverlapping(modulus.as_ptr(), self.rsa.m_mem(0).as_ptr() as *mut u32, N); + copy_nonoverlapping(modulus.as_ptr(), self.rsa.m_mem(0).as_ptr(), N); } fn write_mprime(&mut self, m_prime: u32) { @@ -111,15 +107,11 @@ impl<'d> Rsa<'d> { } unsafe fn write_operand_a(&mut self, operand_a: &[u32; N]) { - copy_nonoverlapping( - operand_a.as_ptr(), - self.rsa.x_mem(0).as_ptr() as *mut u32, - N, - ); + copy_nonoverlapping(operand_a.as_ptr(), self.rsa.x_mem(0).as_ptr(), N); } unsafe fn write_r(&mut self, r: &[u32; N]) { - copy_nonoverlapping(r.as_ptr(), self.rsa.z_mem(0).as_ptr() as *mut u32, N); + copy_nonoverlapping(r.as_ptr(), self.rsa.z_mem(0).as_ptr(), N); } unsafe fn read_out(&mut self, outbuf: &mut [u32; N]) { @@ -140,10 +132,9 @@ mod sealed { } } -pub(self) use sealed::*; +use sealed::*; macro_rules! implement_op { - (($x:literal, multi)) => { paste! {pub struct [];} paste! { @@ -170,7 +161,7 @@ macro_rules! implement_op { }; } -pub(self) use implement_op; +use implement_op; /// Support for RSA peripheral's modular exponentiation feature that could be /// used to find the `(base ^ exponent) mod modulus`. @@ -259,7 +250,7 @@ where /// This is a non blocking function that returns without an error if /// operation is completed successfully. `start_multiplication` must be /// called before calling this function. - pub fn read_results<'b, const O: usize>(&mut self, outbuf: &mut T::OutputType) + pub fn read_results(&mut self, outbuf: &mut T::OutputType) where T: Multi, { diff --git a/esp-hal/src/rtc_cntl/mod.rs b/esp-hal/src/rtc_cntl/mod.rs index d2411b01d..105a7636d 100644 --- a/esp-hal/src/rtc_cntl/mod.rs +++ b/esp-hal/src/rtc_cntl/mod.rs @@ -272,11 +272,7 @@ impl<'d> Rtc<'d> { /// enter deep sleep and wake with the provided `wake_sources` #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] - pub fn sleep_deep<'a>( - &mut self, - wake_sources: &[&'a dyn WakeSource], - delay: &mut crate::Delay, - ) -> ! { + pub fn sleep_deep(&mut self, wake_sources: &[&dyn WakeSource], delay: &mut crate::Delay) -> ! { let config = RtcSleepConfig::deep(); self.sleep(&config, wake_sources, delay); unreachable!(); @@ -284,11 +280,7 @@ impl<'d> Rtc<'d> { /// enter light sleep and wake with the provided `wake_sources` #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] - pub fn sleep_light<'a>( - &mut self, - wake_sources: &[&'a dyn WakeSource], - delay: &mut crate::Delay, - ) { + pub fn sleep_light(&mut self, wake_sources: &[&dyn WakeSource], delay: &mut crate::Delay) { let config = RtcSleepConfig::default(); self.sleep(&config, wake_sources, delay); } @@ -296,13 +288,13 @@ impl<'d> Rtc<'d> { /// enter sleep with the provided `config` and wake with the provided /// `wake_sources` #[cfg(any(esp32, esp32s3, esp32c3, esp32c6))] - pub fn sleep<'a>( + pub fn sleep( &mut self, config: &RtcSleepConfig, - wake_sources: &[&'a dyn WakeSource], + wake_sources: &[&dyn WakeSource], delay: &mut crate::Delay, ) { - let mut config = config.clone(); + let mut config = *config; let mut wakeup_triggers = WakeTriggers::default(); for wake_source in wake_sources { wake_source.apply(self, &mut wakeup_triggers, &mut config) @@ -422,17 +414,11 @@ impl RtcClock { // Or maybe this clock should be connected to digital when // XTAL 32k clock is enabled instead? .dig_xtal32k_en() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock32kXtal => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal)) // The clk_8m_d256 will be closed when rtc_state in SLEEP, // so if the slow_clk is 8md256, clk_8m must be force power on .ck8m_force_pu() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock8mD256 => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock8mD256)) }); ets_delay_us(300u32); @@ -674,11 +660,11 @@ impl RtcClock { #[allow(unused)] #[derive(Debug, Clone, Copy)] enum RwdtStageAction { - RwdtStageActionOff = 0, - RwdtStageActionInterrupt = 1, - RwdtStageActionResetCpu = 2, - RwdtStageActionResetSystem = 3, - RwdtStageActionResetRtc = 4, + Off = 0, + Interrupt = 1, + ResetCpu = 2, + ResetSystem = 3, + ResetRtc = 4, } /// RTC Watchdog Timer @@ -692,10 +678,10 @@ pub struct Rwdt { impl Default for Rwdt { fn default() -> Self { Self { - stg0_action: RwdtStageAction::RwdtStageActionResetRtc, - stg1_action: RwdtStageAction::RwdtStageActionOff, - stg2_action: RwdtStageAction::RwdtStageActionOff, - stg3_action: RwdtStageAction::RwdtStageActionOff, + stg0_action: RwdtStageAction::ResetRtc, + stg1_action: RwdtStageAction::Off, + stg2_action: RwdtStageAction::Off, + stg3_action: RwdtStageAction::Off, } } } @@ -718,7 +704,7 @@ impl Rwdt { #[cfg(any(esp32c6, esp32h2))] let rtc_cntl = unsafe { &*LP_WDT::PTR }; - self.stg0_action = RwdtStageAction::RwdtStageActionInterrupt; + self.stg0_action = RwdtStageAction::Interrupt; self.set_write_protection(false); @@ -743,7 +729,7 @@ impl Rwdt { #[cfg(any(esp32c6, esp32h2))] let rtc_cntl = unsafe { &*LP_WDT::PTR }; - self.stg0_action = RwdtStageAction::RwdtStageActionResetRtc; + self.stg0_action = RwdtStageAction::ResetRtc; self.set_write_protection(false); @@ -952,6 +938,13 @@ impl Swd { } } +#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] +impl Default for Swd { + fn default() -> Self { + Self::new() + } +} + #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] impl WatchdogDisable for Swd { fn disable(&mut self) { @@ -961,9 +954,8 @@ impl WatchdogDisable for Swd { pub fn get_reset_reason(cpu: Cpu) -> Option { let reason = unsafe { rtc_get_reset_reason(cpu as u32) }; - let reason = SocResetReason::from_repr(reason as usize); - reason + SocResetReason::from_repr(reason as usize) } pub fn get_wakeup_cause() -> SleepSource { @@ -973,7 +965,7 @@ pub fn get_wakeup_cause() -> SleepSource { #[cfg(any(esp32c6, esp32h2))] let wakeup_cause = WakeupReason::from_bits_retain(unsafe { - (&*crate::peripherals::PMU::PTR) + (*crate::peripherals::PMU::PTR) .slp_wakeup_status0() .read() .wakeup_cause() @@ -981,15 +973,11 @@ pub fn get_wakeup_cause() -> SleepSource { }); #[cfg(not(any(esp32, esp32c6, esp32h2)))] let wakeup_cause = WakeupReason::from_bits_retain(unsafe { - (&*LPWR::PTR) - .slp_wakeup_cause() - .read() - .wakeup_cause() - .bits() + (*LPWR::PTR).slp_wakeup_cause().read().wakeup_cause().bits() }); #[cfg(esp32)] let wakeup_cause = WakeupReason::from_bits_retain(unsafe { - (&*LPWR::PTR).wakeup_state().read().wakeup_cause().bits() as u32 + (*LPWR::PTR).wakeup_state().read().wakeup_cause().bits() as u32 }); if wakeup_cause.contains(WakeupReason::TimerTrigEn) { @@ -1038,5 +1026,5 @@ pub fn get_wakeup_cause() -> SleepSource { return SleepSource::CocpuTrapTrig; } - return SleepSource::Undefined; + SleepSource::Undefined } diff --git a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs index 5b6355d52..be4ee295c 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32c6.rs @@ -1470,17 +1470,12 @@ impl RtcClock { lp_clkrst() .lp_clk_conf() .modify(|_, w| w.slow_clk_sel().bits(slow_freq as u8)); + lp_clkrst().clk_to_hp().modify(|_, w| { w.icg_hp_xtal32k() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock32kXtal => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal)) .icg_hp_xtal32k() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock32kXtal => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal)) }); } } @@ -1792,10 +1787,8 @@ impl RtcClock { // The Fosc CLK of calibration circuit is divided by 32 for ECO1. // So we need to divide the calibrate cycles of the FOSC for ECO1 and above // chips by 32 to avoid excessive calibration time. - if Efuse::chip_revision() > 0 { - if cal_clk == RtcCalSel::RtcCalRcFast { - slowclk_cycles >>= 5; - } + if Efuse::chip_revision() > 0 && cal_clk == RtcCalSel::RtcCalRcFast { + slowclk_cycles >>= 5; } let xtal_cycles = RtcClock::calibrate_internal(cal_clk, slowclk_cycles) as u64; @@ -1845,7 +1838,7 @@ pub(crate) struct UnsupportedClockSource; #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub(crate) enum CpuClockSource { Xtal, - PLL, + Pll, RcFast, } @@ -1853,7 +1846,7 @@ impl CpuClockSource { pub(crate) fn current() -> Result { let source = match unsafe { pcr().sysclk_conf().read().soc_clk_sel().bits() } { 0 => CpuClockSource::Xtal, - 1 => CpuClockSource::PLL, + 1 => CpuClockSource::Pll, 2 => CpuClockSource::RcFast, _ => return Err(UnsupportedClockSource), }; @@ -1866,7 +1859,7 @@ impl CpuClockSource { pcr().sysclk_conf().modify(|_, w| { w.soc_clk_sel().bits(match self { CpuClockSource::Xtal => 0, - CpuClockSource::PLL => 1, + CpuClockSource::Pll => 1, CpuClockSource::RcFast => 2, }) }); @@ -1897,7 +1890,7 @@ impl SavedClockConfig { div = esp32c6_cpu_get_ls_divider(); source_freq_mhz = RtcClock::get_xtal_freq_mhz(); } - CpuClockSource::PLL => { + CpuClockSource::Pll => { div = esp32c6_cpu_get_hs_divider(); source_freq_mhz = esp32c6_bbpll_get_freq_mhz(); } @@ -1925,8 +1918,8 @@ impl SavedClockConfig { match self.source { CpuClockSource::Xtal => esp32c6_rtc_update_to_xtal_raw(self.freq_mhz(), self.div), CpuClockSource::RcFast => esp32c6_rtc_update_to_8m(), - CpuClockSource::PLL => { - if old_source != CpuClockSource::PLL { + CpuClockSource::Pll => { + if old_source != CpuClockSource::Pll { rtc_clk_bbpll_enable(); esp32c6_rtc_bbpll_configure_raw( RtcClock::get_xtal_freq_mhz(), @@ -1937,7 +1930,7 @@ impl SavedClockConfig { } } - if old_source == CpuClockSource::PLL && self.source != CpuClockSource::PLL + if old_source == CpuClockSource::Pll && self.source != CpuClockSource::Pll // && !s_bbpll_digi_consumers_ref_count { // We don't turn off the bbpll if some consumers depend on bbpll diff --git a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs index 8cee82c1a..592a20921 100644 --- a/esp-hal/src/rtc_cntl/rtc/esp32h2.rs +++ b/esp-hal/src/rtc_cntl/rtc/esp32h2.rs @@ -326,15 +326,9 @@ impl RtcClock { .modify(|_, w| w.slow_clk_sel().bits(slow_freq as u8)); lp_clkrst.clk_to_hp().modify(|_, w| { w.icg_hp_xtal32k() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock32kXtal => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal)) .icg_hp_xtal32k() - .bit(match slow_freq { - RtcSlowClock::RtcSlowClock32kXtal => true, - _ => false, - }) + .bit(matches!(slow_freq, RtcSlowClock::RtcSlowClock32kXtal)) }); } } diff --git a/esp-hal/src/rtc_cntl/sleep/esp32.rs b/esp-hal/src/rtc_cntl/sleep/esp32.rs index 2855aa825..3e0aba66f 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32.rs @@ -383,19 +383,19 @@ impl RtcSleepConfig { // esp-idf also clears these: - (&*esp32::DPORT::ptr()) + (*esp32::DPORT::ptr()) .mem_pd_mask() .modify(|_, w| w.lslp_mem_pd_mask().clear_bit()); - (&*esp32::I2S0::ptr()) + (*esp32::I2S0::ptr()) .pd_conf() .modify(|_, w| w.plc_mem_force_pu().clear_bit().fifo_force_pu().clear_bit()); - (&*esp32::BB::ptr()) + (*esp32::BB::ptr()) .bbpd_ctrl() .modify(|_, w| w.fft_force_pu().clear_bit().dc_est_force_pu().clear_bit()); - (&*esp32::NRX::ptr()).nrxpd_ctrl().modify(|_, w| { + (*esp32::NRX::ptr()).nrxpd_ctrl().modify(|_, w| { w.rx_rot_force_pu() .clear_bit() .vit_force_pu() @@ -537,7 +537,7 @@ impl RtcSleepConfig { // set bits for what can wake us up rtc_cntl .wakeup_state() - .modify(|_, w| w.wakeup_ena().bits(wakeup_triggers.0.into())); + .modify(|_, w| w.wakeup_ena().bits(wakeup_triggers.0)); rtc_cntl .state0() diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index 9a298f829..20293df67 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -585,10 +585,10 @@ impl RtcSleepConfig { .modify(|_, w| w.icache_tag_mem_force_on().clear_bit()); // clear register clock force on // clear register clock force on - (&*esp32c3::SPI0::ptr()) + (*esp32c3::SPI0::ptr()) .clock_gate() .modify(|_, w| w.clk_en().clear_bit()); - (&*esp32c3::SPI1::ptr()) + (*esp32c3::SPI1::ptr()) .clock_gate() .modify(|_, w| w.clk_en().clear_bit()); } diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c6.rs b/esp-hal/src/rtc_cntl/sleep/esp32c6.rs index 17964593d..a899b7a40 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c6.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c6.rs @@ -190,7 +190,7 @@ impl AnalogSleepConfig { // HP SLEEP (hp_sleep_*) pmu().hp_sleep_bias().modify(|_, w| { w.hp_sleep_dbg_atten() // pmu_ll_hp_set_dbg_atten - .bits(self.hp_sys.bias.dbg_atten() as u8) + .bits(self.hp_sys.bias.dbg_atten()) .hp_sleep_pd_cur() // pmu_ll_hp_set_current_power_off .bit(self.hp_sys.bias.pd_cur()) .sleep() // pmu_ll_hp_set_bias_sleep_enable @@ -200,7 +200,7 @@ impl AnalogSleepConfig { w.hp_sleep_hp_regulator_xpd() // pmu_ll_hp_set_regulator_xpd .bit(self.hp_sys.regulator0.xpd()) .hp_sleep_hp_regulator_dbias() // pmu_ll_hp_set_regulator_dbias - .bits(self.hp_sys.regulator0.dbias() as u8) + .bits(self.hp_sys.regulator0.dbias()) }); pmu().hp_sleep_hp_regulator1().modify(|_, w| { w.hp_sleep_hp_regulator_drv_b() // pmu_ll_hp_set_regulator_driver_bar @@ -210,7 +210,7 @@ impl AnalogSleepConfig { // LP SLEEP (lp_sleep_*) pmu().lp_sleep_bias().modify(|_, w| { w.lp_sleep_dbg_atten() // pmu_ll_lp_set_dbg_atten - .bits(self.lp_sys_sleep.bias.dbg_atten() as u8) + .bits(self.lp_sys_sleep.bias.dbg_atten()) .lp_sleep_pd_cur() // pmu_ll_lp_set_current_power_off .bit(self.lp_sys_sleep.bias.pd_cur()) .sleep() // pmu_ll_lp_set_bias_sleep_enable @@ -223,14 +223,14 @@ impl AnalogSleepConfig { .lp_sleep_lp_regulator_xpd() // pmu_ll_lp_set_regulator_xpd .bit(self.lp_sys_sleep.regulator0.xpd()) .lp_sleep_lp_regulator_slp_dbias() // pmu_ll_lp_set_regulator_sleep_dbias - .bits(self.lp_sys_sleep.regulator0.slp_dbias() as u8) + .bits(self.lp_sys_sleep.regulator0.slp_dbias()) .lp_sleep_lp_regulator_dbias() // pmu_ll_lp_set_regulator_dbias - .bits(self.lp_sys_sleep.regulator0.dbias() as u8) + .bits(self.lp_sys_sleep.regulator0.dbias()) }); pmu().lp_sleep_lp_regulator1().modify(|_, w| { w.lp_sleep_lp_regulator_drv_b() // pmu_ll_lp_set_regulator_driver_bar - .bits(self.lp_sys_sleep.regulator1.drv_b() as u8) + .bits(self.lp_sys_sleep.regulator1.drv_b()) }); } } @@ -537,7 +537,7 @@ impl SleepTimeConfig { // So we need to divide the calibrate cycles of the FOSC for ECO1 and above // chips by 32 to avoid excessive calibration time. if Efuse::chip_revision() >= 1 { - slowclk_cycles = slowclk_cycles / 32; + slowclk_cycles /= 32; } let xtal_cycles = diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index 5304f618a..7643be77a 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -536,10 +536,10 @@ impl RtcSleepConfig { .modify(|_, w| w.icache_tag_mem_force_on().clear_bit()); // clear register clock force on - (&*esp32s3::SPI0::ptr()) + (*esp32s3::SPI0::ptr()) .clock_gate() .modify(|_, w| w.clk_en().clear_bit()); - (&*esp32s3::SPI1::ptr()) + (*esp32s3::SPI1::ptr()) .clock_gate() .modify(|_, w| w.clk_en().clear_bit()); diff --git a/esp-hal/src/sha.rs b/esp-hal/src/sha.rs index 3a47ce7b5..d1b2fd69a 100644 --- a/esp-hal/src/sha.rs +++ b/esp-hal/src/sha.rs @@ -206,13 +206,13 @@ impl<'d> Sha<'d> { } fn chunk_length(&self) -> usize { - return match self.mode { + match self.mode { ShaMode::SHA1 | ShaMode::SHA256 => 64, #[cfg(not(esp32))] ShaMode::SHA224 => 64, #[cfg(not(any(esp32c2, esp32c3, esp32c6, esp32h2)))] _ => 128, - }; + } } #[cfg(esp32)] diff --git a/esp-hal/src/soc/esp32/cpu_control.rs b/esp-hal/src/soc/esp32/cpu_control.rs index f48d5063c..73a88e98c 100644 --- a/esp-hal/src/soc/esp32/cpu_control.rs +++ b/esp-hal/src/soc/esp32/cpu_control.rs @@ -76,13 +76,11 @@ pub struct Stack { pub mem: MaybeUninit<[u8; SIZE]>, } +#[allow(clippy::len_without_is_empty)] impl Stack { - const _ALIGNED: () = ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. - /// Construct a stack of length SIZE, uninitialized - #[allow(path_statements)] pub const fn new() -> Stack { - Self::_ALIGNED; + ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. Stack { mem: MaybeUninit::uninit(), @@ -165,6 +163,11 @@ impl CpuControl { } /// Park the given core + /// + /// # Safety + /// + /// The user must ensure that the core being parked is not the core which is + /// currently executing their code. pub unsafe fn park_core(&mut self, core: Cpu) { internal_park_core(core); } @@ -278,7 +281,7 @@ impl CpuControl { unsafe { // move vec table - let base = &_init_start as *const u32; + let base = core::ptr::addr_of!(_init_start); core::arch::asm!("wsr.vecbase {0}", in(reg) base, options(nostack)); } @@ -363,7 +366,7 @@ impl CpuControl { self.unpark_core(Cpu::AppCpu); Ok(AppCoreGuard { - phantom: PhantomData::default(), + phantom: PhantomData, }) } } diff --git a/esp-hal/src/soc/esp32c2/gpio.rs b/esp-hal/src/soc/esp32c2/gpio.rs index 3f22d788d..7ad652f9a 100644 --- a/esp-hal/src/soc/esp32c2/gpio.rs +++ b/esp-hal/src/soc/esp32c2/gpio.rs @@ -64,7 +64,7 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { - unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } + unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal/src/soc/esp32c2/mod.rs b/esp-hal/src/soc/esp32c2/mod.rs index da9c81e74..d923fb397 100644 --- a/esp-hal/src/soc/esp32c2/mod.rs +++ b/esp-hal/src/soc/esp32c2/mod.rs @@ -13,6 +13,7 @@ pub mod gpio; pub mod peripherals; pub mod radio_clocks; +#[allow(unused)] pub(crate) mod registers { pub const INTERRUPT_MAP_BASE: u32 = 0x600c2000; } diff --git a/esp-hal/src/soc/esp32c3/gpio.rs b/esp-hal/src/soc/esp32c3/gpio.rs index 4c9976217..401e0aba6 100644 --- a/esp-hal/src/soc/esp32c3/gpio.rs +++ b/esp-hal/src/soc/esp32c3/gpio.rs @@ -65,7 +65,7 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { - unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } + unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal/src/soc/esp32c3/mod.rs b/esp-hal/src/soc/esp32c3/mod.rs index a84c0c94b..8f5de57dc 100644 --- a/esp-hal/src/soc/esp32c3/mod.rs +++ b/esp-hal/src/soc/esp32c3/mod.rs @@ -17,6 +17,7 @@ pub mod gpio; pub mod peripherals; pub mod radio_clocks; +#[allow(unused)] pub(crate) mod registers { pub const INTERRUPT_MAP_BASE: u32 = 0x600c2000; } diff --git a/esp-hal/src/soc/esp32c6/gpio.rs b/esp-hal/src/soc/esp32c6/gpio.rs index c5f44ae93..995ade47e 100644 --- a/esp-hal/src/soc/esp32c6/gpio.rs +++ b/esp-hal/src/soc/esp32c6/gpio.rs @@ -65,7 +65,7 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { - unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } + unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal/src/soc/esp32c6/lp_core.rs b/esp-hal/src/soc/esp32c6/lp_core.rs index f896b55d5..13ebfe763 100644 --- a/esp-hal/src/soc/esp32c6/lp_core.rs +++ b/esp-hal/src/soc/esp32c6/lp_core.rs @@ -98,12 +98,12 @@ impl<'d> LpCore<'d> { match clk_src { LpCoreClockSource::RcFastClk => unsafe { - (&*crate::soc::peripherals::LP_CLKRST::PTR) + (*crate::soc::peripherals::LP_CLKRST::PTR) .lp_clk_conf() .modify(|_, w| w.fast_clk_sel().clear_bit()) }, LpCoreClockSource::XtalD2Clk => unsafe { - (&*crate::soc::peripherals::LP_CLKRST::PTR) + (*crate::soc::peripherals::LP_CLKRST::PTR) .lp_clk_conf() .modify(|_, w| w.fast_clk_sel().set_bit()) }, diff --git a/esp-hal/src/soc/esp32c6/mod.rs b/esp-hal/src/soc/esp32c6/mod.rs index 28a757cea..eae8003c8 100644 --- a/esp-hal/src/soc/esp32c6/mod.rs +++ b/esp-hal/src/soc/esp32c6/mod.rs @@ -19,6 +19,7 @@ pub mod lp_core; pub mod peripherals; pub mod radio_clocks; +#[allow(unused)] pub(crate) mod registers { pub const INTERRUPT_MAP_BASE: u32 = 0x60010000; } diff --git a/esp-hal/src/soc/esp32h2/gpio.rs b/esp-hal/src/soc/esp32h2/gpio.rs index 626f7e737..60f56fdad 100644 --- a/esp-hal/src/soc/esp32h2/gpio.rs +++ b/esp-hal/src/soc/esp32h2/gpio.rs @@ -66,7 +66,7 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { - unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } + unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal/src/soc/esp32h2/mod.rs b/esp-hal/src/soc/esp32h2/mod.rs index b367042d6..6622d6d94 100644 --- a/esp-hal/src/soc/esp32h2/mod.rs +++ b/esp-hal/src/soc/esp32h2/mod.rs @@ -18,6 +18,7 @@ pub mod gpio; pub mod peripherals; pub mod radio_clocks; +#[allow(unused)] pub(crate) mod registers { pub const INTERRUPT_MAP_BASE: u32 = 0x60010000; } diff --git a/esp-hal/src/soc/esp32h2/radio_clocks.rs b/esp-hal/src/soc/esp32h2/radio_clocks.rs index fb44e2505..4e19b9d74 100644 --- a/esp-hal/src/soc/esp32h2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32h2/radio_clocks.rs @@ -58,7 +58,6 @@ fn disable_phy() { } fn ble_ieee802154_clock_enable() { - let modem_lpcon = unsafe { &*esp32h2::MODEM_LPCON::PTR }; let modem_syscon = unsafe { &*esp32h2::MODEM_SYSCON::PTR }; modem_syscon @@ -82,7 +81,7 @@ fn ble_ieee802154_clock_enable() { .set_bit() }); - modem_lpcon + unsafe { &*esp32h2::MODEM_LPCON::PTR } .clk_conf() .modify(|_, w| w.clk_coex_en().set_bit()); } @@ -138,7 +137,7 @@ fn init_clocks() { .as_ptr() .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28); - (&*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| { + (*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| { w.clk_i2c_mst_en() .set_bit() .clk_coex_en() diff --git a/esp-hal/src/soc/esp32s2/psram.rs b/esp-hal/src/soc/esp32s2/psram.rs index 33201e972..0dd575e4e 100644 --- a/esp-hal/src/soc/esp32s2/psram.rs +++ b/esp-hal/src/soc/esp32s2/psram.rs @@ -18,7 +18,7 @@ const PSRAM_VADDR: u32 = 0x3f500000; pub fn psram_vaddr_start() -> usize { - PSRAM_VADDR_START as usize + PSRAM_VADDR_START } cfg_if::cfg_if! { diff --git a/esp-hal/src/soc/esp32s3/cpu_control.rs b/esp-hal/src/soc/esp32s3/cpu_control.rs index 12ef92237..a1bad8d08 100644 --- a/esp-hal/src/soc/esp32s3/cpu_control.rs +++ b/esp-hal/src/soc/esp32s3/cpu_control.rs @@ -76,13 +76,11 @@ pub struct Stack { pub mem: MaybeUninit<[u8; SIZE]>, } +#[allow(clippy::len_without_is_empty)] impl Stack { - const _ALIGNED: () = ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. - /// Construct a stack of length SIZE, uninitialized - #[allow(path_statements)] pub const fn new() -> Stack { - Self::_ALIGNED; + ::core::assert!(SIZE % 16 == 0); // Make sure stack top is aligned, too. Stack { mem: MaybeUninit::uninit(), @@ -165,6 +163,11 @@ impl CpuControl { } /// Park the given core + /// + /// # Safety + /// + /// The user must ensure that the core being parked is not the core which is + /// currently executing their code. pub unsafe fn park_core(&mut self, core: Cpu) { internal_park_core(core); } @@ -214,7 +217,7 @@ impl CpuControl { unsafe { // move vec table - let base = &_init_start as *const u32; + let base = core::ptr::addr_of!(_init_start); core::arch::asm!("wsr.vecbase {0}", in(reg) base, options(nostack)); } @@ -300,7 +303,7 @@ impl CpuControl { self.unpark_core(Cpu::AppCpu); Ok(AppCoreGuard { - phantom: PhantomData::default(), + phantom: PhantomData, }) } } diff --git a/esp-hal/src/soc/esp32s3/gpio.rs b/esp-hal/src/soc/esp32s3/gpio.rs index 90adf5b38..55fa6e6bf 100644 --- a/esp-hal/src/soc/esp32s3/gpio.rs +++ b/esp-hal/src/soc/esp32s3/gpio.rs @@ -66,7 +66,7 @@ pub const ZERO_INPUT: u8 = 0x3c; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { - unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } + unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal/src/soc/mod.rs b/esp-hal/src/soc/mod.rs index 4adf9373a..76c52530e 100644 --- a/esp-hal/src/soc/mod.rs +++ b/esp-hal/src/soc/mod.rs @@ -1,6 +1,6 @@ use portable_atomic::{AtomicU8, Ordering}; -pub use self::soc::*; +pub use self::implementation::*; #[cfg_attr(esp32, path = "esp32/mod.rs")] #[cfg_attr(esp32c2, path = "esp32c2/mod.rs")] @@ -10,7 +10,7 @@ pub use self::soc::*; #[cfg_attr(esp32p4, path = "esp32p4/mod.rs")] #[cfg_attr(esp32s2, path = "esp32s2/mod.rs")] #[cfg_attr(esp32s3, path = "esp32s3/mod.rs")] -mod soc; +mod implementation; mod efuse_field; @@ -30,7 +30,7 @@ pub enum SetMacError { AlreadySet, } -impl soc::efuse::Efuse { +impl self::efuse::Efuse { /// Set the base mac address /// /// The new value will be returned by `read_mac_address` instead of the one @@ -69,9 +69,5 @@ impl soc::efuse::Efuse { } pub fn is_valid_ram_address(address: u32) -> bool { - if (soc::constants::SOC_DRAM_LOW..=soc::constants::SOC_DRAM_HIGH).contains(&address) { - true - } else { - false - } + (self::constants::SOC_DRAM_LOW..=self::constants::SOC_DRAM_HIGH).contains(&address) } diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index adf15f7dd..f26fdb8c4 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -184,10 +184,7 @@ impl Command { } fn is_none(&self) -> bool { - match self { - Command::None => true, - _ => false, - } + matches!(self, Command::None) } } @@ -308,10 +305,7 @@ impl Address { } fn is_none(&self) -> bool { - match self { - Address::None => true, - _ => false, - } + matches!(self, Address::None) } fn mode(&self) -> SpiDataMode { @@ -482,7 +476,7 @@ where let mut spi = Spi { spi, - _mode: PhantomData::default(), + _mode: PhantomData, }; spi.spi.setup(frequency, clocks); spi.spi.init(); @@ -659,7 +653,7 @@ where let mut spi = Spi { spi, - _mode: PhantomData::default(), + _mode: PhantomData, }; spi.spi.setup(frequency, clocks); spi.spi.init(); @@ -692,7 +686,7 @@ where return Err(Error::FifoSizeExeeded); } - if buffer.len() == 0 { + if buffer.is_empty() { return Err(Error::Unsupported); } @@ -822,7 +816,7 @@ pub mod dma { SpiDma { spi: self.spi, channel, - _mode: PhantomData::default(), + _mode: PhantomData, } } } @@ -1322,16 +1316,16 @@ pub mod dma { type Error = T::Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { - Ok( - if !crate::soc::is_valid_ram_address(&words[0] as *const _ as u32) { - for chunk in words.chunks(SIZE) { - self.buffer[..chunk.len()].copy_from_slice(chunk); - self.inner.write(&self.buffer[..chunk.len()])?; - } - } else { - self.inner.write(words)?; - }, - ) + if !crate::soc::is_valid_ram_address(&words[0] as *const _ as u32) { + for chunk in words.chunks(SIZE) { + self.buffer[..chunk.len()].copy_from_slice(chunk); + self.inner.write(&self.buffer[..chunk.len()])?; + } + } else { + self.inner.write(words)?; + }; + + Ok(()) } } @@ -1787,7 +1781,7 @@ where Ok(read_buffer) } - fn start_transfer_dma<'w>( + fn start_transfer_dma( &mut self, write_buffer_ptr: *const u8, write_buffer_len: usize, @@ -1845,7 +1839,7 @@ where Ok(words) } - fn start_write_bytes_dma<'w>( + fn start_write_bytes_dma( &mut self, ptr: *const u8, len: usize, @@ -1875,7 +1869,7 @@ where Ok(()) } - fn start_read_bytes_dma<'w>( + fn start_read_bytes_dma( &mut self, ptr: *mut u8, len: usize, @@ -2094,7 +2088,7 @@ pub trait Instance { unsafe { // use default clock source PLL_F80M_CLK (ESP32-C6) and // PLL_F48M_CLK (ESP32-H2) - (&*crate::peripherals::PCR::PTR) + (*crate::peripherals::PCR::PTR) .spi2_clkm_conf() .modify(|_, w| w.spi2_clkm_sel().bits(1)); } @@ -2380,18 +2374,18 @@ pub trait Instance { pre = 16; } - errval = (apb_clk_freq.raw() as i32 / (pre as i32 * n as i32) + errval = (apb_clk_freq.raw() as i32 / (pre * n) - frequency.raw() as i32) .abs(); if bestn == -1 || errval <= besterr { besterr = errval; - bestn = n as i32; - bestpre = pre as i32; + bestn = n; + bestpre = pre; } } let n: i32 = bestn; - pre = bestpre as i32; + pre = bestpre; let l: i32 = n; /* Effectively, this does: @@ -2731,7 +2725,7 @@ pub trait Instance { !address.is_none(), false, dummy != 0, - buffer.len() == 0, + buffer.is_empty(), ); // set cmd, address, dummy cycles @@ -2771,7 +2765,7 @@ pub trait Instance { .modify(|_, w| w.usr_dummy_cyclelen().variant(dummy - 1)); } - if buffer.len() > 0 { + if !buffer.is_empty() { // re-using the full-duplex write here self.write_bytes(buffer)?; } else { @@ -2794,7 +2788,7 @@ pub trait Instance { !address.is_none(), false, dummy != 0, - buffer.len() == 0, + buffer.is_empty(), ); // set cmd, address, dummy cycles @@ -2950,7 +2944,7 @@ impl ExtendedInstance for crate::peripherals::SPI2 { } } -#[cfg(any(esp32))] +#[cfg(esp32)] impl Instance for crate::peripherals::SPI2 { #[inline(always)] fn register_block(&self) -> &RegisterBlock { @@ -2988,7 +2982,7 @@ impl Instance for crate::peripherals::SPI2 { } } -#[cfg(any(esp32))] +#[cfg(esp32)] impl ExtendedInstance for crate::peripherals::SPI2 { fn sio0_input_signal(&self) -> InputSignal { InputSignal::HSPID @@ -3015,7 +3009,7 @@ impl ExtendedInstance for crate::peripherals::SPI2 { } } -#[cfg(any(esp32))] +#[cfg(esp32)] impl Instance for crate::peripherals::SPI3 { #[inline(always)] fn register_block(&self) -> &RegisterBlock { diff --git a/esp-hal/src/spi/slave.rs b/esp-hal/src/spi/slave.rs index 4b44dd50d..8990cdddf 100644 --- a/esp-hal/src/spi/slave.rs +++ b/esp-hal/src/spi/slave.rs @@ -127,7 +127,7 @@ where let mut spi = Spi { spi, data_mode: mode, - _mode: PhantomData::default(), + _mode: PhantomData, }; spi.spi.init(); spi.spi.set_data_mode(mode); @@ -327,8 +327,8 @@ pub mod dma { unsafe { let buffer = core::ptr::read(&self.buffer); let payload = core::ptr::read(&self.spi_dma); - let err = (&self).spi_dma.channel.rx.has_error() - || (&self).spi_dma.channel.tx.has_error(); + let err = + self.spi_dma.channel.rx.has_error() || self.spi_dma.channel.tx.has_error(); mem::forget(self); if err { Err((DmaError::DescriptorError, buffer, payload)) @@ -1000,7 +1000,7 @@ impl Instance for crate::peripherals::SPI2 { } } -#[cfg(any(esp32))] +#[cfg(esp32)] impl Instance for crate::peripherals::SPI2 { #[inline(always)] fn register_block(&self) -> &RegisterBlock { @@ -1038,7 +1038,7 @@ impl Instance for crate::peripherals::SPI2 { } } -#[cfg(any(esp32))] +#[cfg(esp32)] impl Instance for crate::peripherals::SPI3 { #[inline(always)] fn register_block(&self) -> &RegisterBlock { diff --git a/esp-hal/src/systimer.rs b/esp-hal/src/systimer.rs index e4456828a..4a9373b63 100644 --- a/esp-hal/src/systimer.rs +++ b/esp-hal/src/systimer.rs @@ -257,18 +257,36 @@ impl Alarm { } impl Alarm { + /// Conjure an alarm out of thin air. + /// + /// # Safety + /// + /// Users must take care to ensure that only one reference to the timer is + /// in scope at any given time. pub const unsafe fn conjure() -> Self { Self { _pd: PhantomData } } } impl Alarm { + /// Conjure an alarm out of thin air. + /// + /// # Safety + /// + /// Users must take care to ensure that only one reference to the timer is + /// in scope at any given time. pub const unsafe fn conjure() -> Self { Self { _pd: PhantomData } } } impl Alarm { + /// Conjure an alarm out of thin air. + /// + /// # Safety + /// + /// Users must take care to ensure that only one reference to the timer is + /// in scope at any given time. pub const unsafe fn conjure() -> Self { Self { _pd: PhantomData } } diff --git a/esp-hal/src/timer.rs b/esp-hal/src/timer.rs index e46250019..5aa5dbff4 100644 --- a/esp-hal/src/timer.rs +++ b/esp-hal/src/timer.rs @@ -189,7 +189,7 @@ where // ESP32-H2 is using PLL_48M_CLK source instead of APB_CLK let timer0 = Timer::new( Timer0 { - phantom: PhantomData::default(), + phantom: PhantomData, }, #[cfg(not(esp32h2))] clocks.apb_clock, @@ -200,7 +200,7 @@ where #[cfg(not(any(esp32c2, esp32c3, esp32c6, esp32h2)))] let timer1 = Timer::new( Timer1 { - phantom: PhantomData::default(), + phantom: PhantomData, }, clocks.apb_clock, ); @@ -425,7 +425,7 @@ where let value_lo = reg_block.t0lo().read().bits() as u64; let value_hi = (reg_block.t0hi().read().bits() as u64) << 32; - (value_lo | value_hi) as u64 + value_lo | value_hi } fn divider(&self) -> u32 { @@ -595,7 +595,7 @@ where let value_lo = reg_block.t1lo().read().bits() as u64; let value_hi = (reg_block.t1hi().read().bits() as u64) << 32; - (value_lo | value_hi) as u64 + value_lo | value_hi } fn divider(&self) -> u32 { @@ -730,7 +730,7 @@ where TG::configure_wdt_src_clk(); Self { - phantom: PhantomData::default(), + phantom: PhantomData, } } @@ -749,6 +749,12 @@ where } /// Forcibly enable or disable the watchdog timer + /// + /// # Safety + /// + /// This bypasses the usual ownership rules for the peripheral, so users + /// must take care to ensure that no driver instance is active for the + /// timer. pub unsafe fn set_wdt_enabled(enabled: bool) { let reg_block = unsafe { &*TG::register_block() }; @@ -827,6 +833,15 @@ where } } +impl Default for Wdt +where + TG: TimerGroupInstance, +{ + fn default() -> Self { + Self::new() + } +} + impl WatchdogDisable for Wdt where TG: TimerGroupInstance, diff --git a/esp-hal/src/trace.rs b/esp-hal/src/trace.rs index 1d45dd821..7cd6fcb53 100644 --- a/esp-hal/src/trace.rs +++ b/esp-hal/src/trace.rs @@ -161,7 +161,8 @@ impl<'d> Trace<'d> { let mut i = 0; loop { let b = unsafe { - (buffer.as_ptr() as *const _ as *const u8) + buffer + .as_ptr() .add((i + idx as usize) % buffer.len()) .read_volatile() }; diff --git a/esp-hal/src/twai/filter.rs b/esp-hal/src/twai/filter.rs index 38ab8f0da..8aa559181 100644 --- a/esp-hal/src/twai/filter.rs +++ b/esp-hal/src/twai/filter.rs @@ -255,8 +255,8 @@ impl SingleExtendedFilter { let mut acceptance_mask: u32 = 0; // Pack the id into the full layout. - acceptance_code |= (id_code.as_raw() as u32) << 3; - acceptance_mask |= (id_mask.as_raw() as u32) << 3; + acceptance_code |= id_code.as_raw() << 3; + acceptance_mask |= id_mask.as_raw() << 3; // Pack the rtr bit into the full layout. acceptance_code |= (rtr_code as u32) << 2; diff --git a/esp-hal/src/twai/mod.rs b/esp-hal/src/twai/mod.rs index f673b2d43..07efe330c 100644 --- a/esp-hal/src/twai/mod.rs +++ b/esp-hal/src/twai/mod.rs @@ -120,7 +120,7 @@ impl EspTwaiFrame { Self { id: id.into(), data, - dlc: dlc, + dlc, is_remote: false, } } diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 2fa605a6c..9f57e1273 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -508,6 +508,7 @@ where } /// Configures the AT-CMD detection settings. + #[allow(clippy::useless_conversion)] pub fn set_at_cmd(&mut self, config: config::AtCmdConfig) { #[cfg(not(any(esp32, esp32s2)))] T::register_block() @@ -518,7 +519,7 @@ where w.at_cmd_char() .bits(config.cmd_char) .char_num() - .bits(config.char_num.or(Some(1)).unwrap()) + .bits(config.char_num.unwrap_or(1)) }); if let Some(pre_idle_count) = config.pre_idle_count { @@ -978,6 +979,7 @@ pub trait Instance { }); } + #[allow(clippy::useless_conversion)] fn get_tx_fifo_count() -> u16 { Self::register_block() .status() @@ -987,6 +989,7 @@ pub trait Instance { .into() } + #[allow(clippy::useless_conversion)] fn get_rx_fifo_count() -> u16 { let fifo_cnt: u16 = Self::register_block() .status() @@ -1000,29 +1003,25 @@ pub trait Instance { // section 3.17 #[cfg(esp32)] { - let rd_addr: u16 = Self::register_block() + let rd_addr = Self::register_block() .mem_rx_status() .read() .mem_rx_rd_addr() - .bits() - .into(); - let wr_addr: u16 = Self::register_block() + .bits(); + let wr_addr = Self::register_block() .mem_rx_status() .read() .mem_rx_wr_addr() - .bits() - .into(); + .bits(); if wr_addr > rd_addr { wr_addr - rd_addr } else if wr_addr < rd_addr { (wr_addr + UART_FIFO_SIZE) - rd_addr + } else if fifo_cnt > 0 { + UART_FIFO_SIZE } else { - if fifo_cnt > 0 { - UART_FIFO_SIZE - } else { - 0 - } + 0 } } diff --git a/esp-hal/src/usb_serial_jtag.rs b/esp-hal/src/usb_serial_jtag.rs index 7a28269f0..e0df0b1de 100644 --- a/esp-hal/src/usb_serial_jtag.rs +++ b/esp-hal/src/usb_serial_jtag.rs @@ -88,7 +88,7 @@ impl<'d> UsbSerialJtagTx<'d> { { // the FIFO is not full unsafe { - reg_block.ep1().write(|w| w.rdwr_byte().bits(word.into())); + reg_block.ep1().write(|w| w.rdwr_byte().bits(word)); } Ok(()) @@ -201,9 +201,7 @@ impl<'d> UsbSerialJtagRx<'d> { impl<'d> UsbSerialJtag<'d> { /// Create a new USB serial/JTAG instance with defaults - pub fn new(usb_device: impl Peripheral

+ 'd) -> Self { - crate::into_ref!(usb_device); - + pub fn new(_usb_device: impl Peripheral

+ 'd) -> Self { PeripheralClockControl::enable(crate::system::Peripheral::UsbDevice); USB_DEVICE::disable_tx_interrupts();