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Remove FullDuplexMode and HalfDuplexMode type params (#2373)

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* Remove duplex type param

* Rename dma_ functions
This commit is contained in:
Dániel Buga 2024-10-24 09:22:21 +02:00 committed by GitHub
parent f03527f6fc
commit 2ac47868f7
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GPG Key ID: B5690EEEBB952194
20 changed files with 511 additions and 823 deletions
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7
esp-hal/CHANGELOG.md
View File

@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Added `AnyTwai`. (#2359) - Added `AnyTwai`. (#2359)
- `Pins::steal()` to unsafely obtain GPIO. (#2335) - `Pins::steal()` to unsafely obtain GPIO. (#2335)
- `I2c::with_timeout` (#2361) - `I2c::with_timeout` (#2361)
- `Spi::half_duplex_read` and `Spi::half_duplex_write` (#2373)
### Changed ### Changed
@ -25,6 +26,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Peripheral type erasure for I2S (#2367) - Peripheral type erasure for I2S (#2367)
- Peripheral type erasure for I2C (#2361) - Peripheral type erasure for I2C (#2361)
- Peripheral type erasure for TWAI (#2359) - Peripheral type erasure for TWAI (#2359)
- The SPI driver has been rewritten to allow using half-duplex and full-duplex functionality on the same bus. See the migration guide for details. (#2373)
- Renamed `SpiDma` functions: `dma_transfer` to `transfer`, `dma_write` to `write`, `dma_read` to `read`. (#2373)
### Fixed ### Fixed
@ -36,6 +39,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- The `i2s::{I2sWrite, I2sWriteDma, I2sRead, I2sReadDma, I2sWriteDmaAsync, I2sReadDmaAsync}` traits have been removed. (#2316) - The `i2s::{I2sWrite, I2sWriteDma, I2sRead, I2sReadDma, I2sWriteDmaAsync, I2sReadDmaAsync}` traits have been removed. (#2316)
- The `ledc::ChannelHW` trait is no longer generic. (#2387) - The `ledc::ChannelHW` trait is no longer generic. (#2387)
- The `I2c::new_with_timeout` constructors have been removed (#2361) - The `I2c::new_with_timeout` constructors have been removed (#2361)
- The `spi::master::HalfDuplexReadWrite` trait has been removed. (#2373)
- The `Spi::with_pins` methods have been removed. (#2373)
- The `Spi::new_half_duplex` constructor have been removed. (#2373)
- The `HalfDuplexMode` and `FullDuplexMode` parameters have been removed from `Spi`. (#2373)
## [0.21.1] ## [0.21.1]

57
esp-hal/MIGRATING-0.21.md
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@ -60,3 +60,60 @@ The `with_timeout` constructors have been removed in favour of `set_timeout` or
-let i2c = I2c::new_with_timeout(peripherals.I2C0, io.pins.gpio4, io.pins.gpio5, 100.kHz(), timeout); -let i2c = I2c::new_with_timeout(peripherals.I2C0, io.pins.gpio4, io.pins.gpio5, 100.kHz(), timeout);
+let i2c = I2c::new(peripherals.I2C0, io.pins.gpio4, io.pins.gpio5, 100.kHz()).with_timeout(timeout); +let i2c = I2c::new(peripherals.I2C0, io.pins.gpio4, io.pins.gpio5, 100.kHz()).with_timeout(timeout);
``` ```
## Changes to half-duplex SPI
The `HalfDuplexMode` and `FullDuplexMode` type parameters have been removed from SPI master and slave
drivers. It is now possible to execute half-duplex and full-duplex operations on the same SPI bus.
### Driver construction
- The `Spi::new_half_duplex` constructor has been removed. Use `new` (or `new_typed`) instead.
- The `with_pins` methods have been removed. Use the individual `with_*` functions instead.
- The `with_mosi` and `with_miso` functions now take input-output peripheral signals to support half-duplex mode.
> TODO(danielb): this means they are currently only usable with GPIO pins, but upcoming GPIO changes should allow using any output signal.
```diff
- let mut spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
- .with_pins(sck, mosi, miso, sio2, sio3, cs);
+ let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
+ .with_sck(sck)
+ .with_cs(cs)
+ .with_mosi(mosi)
+ .with_miso(miso)
+ .with_sio2(sio2)
+ .with_sio3(sio3);
```
### Transfer functions
The `Spi<'_, SPI, HalfDuplexMode>::read` and `Spi<'_, SPI, HalfDuplexMode>::write` functions have been replaced by
`half_duplex_read` and `half_duplex_write`.
```diff
let mut data = [0u8; 2];
let transfer = spi
- .read(
+ .half_duplex_read(
SpiDataMode::Single,
Command::Command8(0x90, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single),
0,
&mut data,
)
.unwrap();
let transfer = spi
- .write(
+ .half_duplex_write(
SpiDataMode::Quad,
Command::Command8(write as u16, command_data_mode),
Address::Address24(
write as u32 | (write as u32) << 8 | (write as u32) << 16,
SpiDataMode::Quad,
),
0,
dma_tx_buf,
)
.unwrap();
```

5
esp-hal/src/dma/mod.rs
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@ -35,7 +35,10 @@
//! 100.kHz(), //! 100.kHz(),
//! SpiMode::Mode0, //! SpiMode::Mode0,
//! ) //! )
//! .with_pins(sclk, mosi, miso, cs) //! .with_sck(sclk)
//! .with_mosi(mosi)
//! .with_miso(miso)
//! .with_cs(cs)
//! .with_dma(dma_channel.configure( //! .with_dma(dma_channel.configure(
//! false, //! false,
//! DmaPriority::Priority0, //! DmaPriority::Priority0,

982
esp-hal/src/spi/master.rs
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File diff suppressed because it is too large Load Diff

13
esp-hal/src/spi/mod.rs
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@ -76,9 +76,6 @@ pub enum SpiBitOrder {
LSBFirst, LSBFirst,
} }
/// Trait marker for defining SPI duplex modes.
pub trait DuplexMode: crate::private::Sealed {}
/// SPI data mode /// SPI data mode
#[derive(Debug, Clone, Copy, PartialEq, Eq)] #[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))] #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -91,16 +88,6 @@ pub enum SpiDataMode {
Quad, Quad,
} }
/// Full-duplex operation
pub struct FullDuplexMode {}
impl DuplexMode for FullDuplexMode {}
impl crate::private::Sealed for FullDuplexMode {}
/// Half-duplex operation
pub struct HalfDuplexMode {}
impl DuplexMode for HalfDuplexMode {}
impl crate::private::Sealed for HalfDuplexMode {}
crate::any_peripheral! { crate::any_peripheral! {
/// Any SPI peripheral. /// Any SPI peripheral.
pub peripheral AnySpi { pub peripheral AnySpi {

27
esp-hal/src/spi/slave.rs
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@ -48,7 +48,7 @@
//! let mut send = tx_buffer; //! let mut send = tx_buffer;
//! //!
//! let transfer = spi //! let transfer = spi
//! .dma_transfer(&mut receive, &mut send) //! .transfer(&mut receive, &mut send)
//! .unwrap(); //! .unwrap();
//! //!
//! transfer.wait().unwrap(); //! transfer.wait().unwrap();
@ -69,9 +69,8 @@
//! `is_done()`. //! `is_done()`.
//! //!
//! See [tracking issue](https://github.com/esp-rs/esp-hal/issues/469) for more information. //! See [tracking issue](https://github.com/esp-rs/esp-hal/issues/469) for more information.
use core::marker::PhantomData;
use super::{Error, FullDuplexMode, SpiMode}; use super::{Error, SpiMode};
use crate::{ use crate::{
dma::{DescriptorChain, DmaChannelConvert, DmaEligible, PeripheralMarker, Rx, Tx}, dma::{DescriptorChain, DmaChannelConvert, DmaEligible, PeripheralMarker, Rx, Tx},
gpio::{InputSignal, OutputSignal, PeripheralInput, PeripheralOutput}, gpio::{InputSignal, OutputSignal, PeripheralInput, PeripheralOutput},
@ -87,14 +86,13 @@ const MAX_DMA_SIZE: usize = 32768 - 32;
/// SPI peripheral driver. /// SPI peripheral driver.
/// ///
/// See the [module-level documentation][self] for more details. /// See the [module-level documentation][self] for more details.
pub struct Spi<'d, M, T = AnySpi> { pub struct Spi<'d, T = AnySpi> {
spi: PeripheralRef<'d, T>, spi: PeripheralRef<'d, T>,
#[allow(dead_code)] #[allow(dead_code)]
data_mode: SpiMode, data_mode: SpiMode,
_mode: PhantomData<M>,
} }
impl<'d> Spi<'d, FullDuplexMode> { impl<'d> Spi<'d> {
/// Constructs an SPI instance in 8bit dataframe mode. /// Constructs an SPI instance in 8bit dataframe mode.
pub fn new< pub fn new<
SCK: PeripheralInput, SCK: PeripheralInput,
@ -108,12 +106,12 @@ impl<'d> Spi<'d, FullDuplexMode> {
miso: impl Peripheral<P = MISO> + 'd, miso: impl Peripheral<P = MISO> + 'd,
cs: impl Peripheral<P = CS> + 'd, cs: impl Peripheral<P = CS> + 'd,
mode: SpiMode, mode: SpiMode,
) -> Spi<'d, FullDuplexMode> { ) -> Spi<'d> {
Self::new_typed(spi, sclk, mosi, miso, cs, mode) Self::new_typed(spi, sclk, mosi, miso, cs, mode)
} }
} }
impl<'d, T> Spi<'d, FullDuplexMode, T> impl<'d, T> Spi<'d, T>
where where
T: Instance, T: Instance,
{ {
@ -130,7 +128,7 @@ where
miso: impl Peripheral<P = MISO> + 'd, miso: impl Peripheral<P = MISO> + 'd,
cs: impl Peripheral<P = CS> + 'd, cs: impl Peripheral<P = CS> + 'd,
mode: SpiMode, mode: SpiMode,
) -> Spi<'d, FullDuplexMode, T> { ) -> Spi<'d, T> {
crate::into_ref!(sclk, mosi, miso, cs); crate::into_ref!(sclk, mosi, miso, cs);
let this = Self::new_internal(spi, mode); let this = Self::new_internal(spi, mode);
@ -154,13 +152,12 @@ where
pub(crate) fn new_internal( pub(crate) fn new_internal(
spi: impl Peripheral<P = impl Into<T> + 'd> + 'd, spi: impl Peripheral<P = impl Into<T> + 'd> + 'd,
mode: SpiMode, mode: SpiMode,
) -> Spi<'d, FullDuplexMode, T> { ) -> Spi<'d, T> {
crate::into_ref!(spi); crate::into_ref!(spi);
let mut spi = Spi { let mut spi = Spi {
spi: spi.map_into(), spi: spi.map_into(),
data_mode: mode, data_mode: mode,
_mode: PhantomData,
}; };
spi.spi.reset_peripheral(); spi.spi.reset_peripheral();
spi.spi.enable_peripheral(); spi.spi.enable_peripheral();
@ -193,7 +190,7 @@ pub mod dma {
Mode, Mode,
}; };
impl<'d, T> Spi<'d, FullDuplexMode, T> impl<'d, T> Spi<'d, T>
where where
T: InstanceDma, T: InstanceDma,
{ {
@ -316,7 +313,7 @@ pub mod dma {
/// sent is 32736 bytes. /// sent is 32736 bytes.
/// ///
/// The write is driven by the SPI master's sclk signal and cs line. /// The write is driven by the SPI master's sclk signal and cs line.
pub fn dma_write<'t, TXBUF>( pub fn write<'t, TXBUF>(
&'t mut self, &'t mut self,
words: &'t TXBUF, words: &'t TXBUF,
) -> Result<DmaTransferTx<'t, Self>, Error> ) -> Result<DmaTransferTx<'t, Self>, Error>
@ -351,7 +348,7 @@ pub mod dma {
/// received is 32736 bytes. /// received is 32736 bytes.
/// ///
/// The read is driven by the SPI master's sclk signal and cs line. /// The read is driven by the SPI master's sclk signal and cs line.
pub fn dma_read<'t, RXBUF>( pub fn read<'t, RXBUF>(
&'t mut self, &'t mut self,
words: &'t mut RXBUF, words: &'t mut RXBUF,
) -> Result<DmaTransferRx<'t, Self>, Error> ) -> Result<DmaTransferRx<'t, Self>, Error>
@ -387,7 +384,7 @@ pub mod dma {
/// ///
/// The data transfer is driven by the SPI master's sclk signal and cs /// The data transfer is driven by the SPI master's sclk signal and cs
/// line. /// line.
pub fn dma_transfer<'t, RXBUF, TXBUF>( pub fn transfer<'t, RXBUF, TXBUF>(
&'t mut self, &'t mut self,
read_buffer: &'t mut RXBUF, read_buffer: &'t mut RXBUF,
words: &'t TXBUF, words: &'t TXBUF,

5
examples/src/bin/embassy_spi.rs
View File

@ -59,7 +59,10 @@ async fn main(_spawner: Spawner) {
let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap(); let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(sclk, mosi, miso, cs) .with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_cs(cs)
.with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0)) .with_dma(dma_channel.configure_for_async(false, DmaPriority::Priority0))
.with_buffers(dma_rx_buf, dma_tx_buf); .with_buffers(dma_rx_buf, dma_tx_buf);

19
examples/src/bin/qspi_flash.rs
View File

@ -79,8 +79,13 @@ fn main() -> ! {
let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap(); let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap(); let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
let mut spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(sclk, mosi, miso, sio2, sio3, cs) .with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_sio2(sio2)
.with_sio3(sio3)
.with_cs(cs)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
let delay = Delay::new(); let delay = Delay::new();
@ -88,7 +93,7 @@ fn main() -> ! {
// write enable // write enable
dma_tx_buf.set_length(0); dma_tx_buf.set_length(0);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::Command8(0x06, SpiDataMode::Single), Command::Command8(0x06, SpiDataMode::Single),
Address::None, Address::None,
@ -102,7 +107,7 @@ fn main() -> ! {
// erase sector // erase sector
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::Command8(0x20, SpiDataMode::Single), Command::Command8(0x20, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single), Address::Address24(0x000000, SpiDataMode::Single),
@ -116,7 +121,7 @@ fn main() -> ! {
// write enable // write enable
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::Command8(0x06, SpiDataMode::Single), Command::Command8(0x06, SpiDataMode::Single),
Address::None, Address::None,
@ -133,7 +138,7 @@ fn main() -> ! {
dma_tx_buf.as_mut_slice().fill(b'!'); dma_tx_buf.as_mut_slice().fill(b'!');
dma_tx_buf.as_mut_slice()[0..][..5].copy_from_slice(&b"Hello"[..]); dma_tx_buf.as_mut_slice()[0..][..5].copy_from_slice(&b"Hello"[..]);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Quad, SpiDataMode::Quad,
Command::Command8(0x32, SpiDataMode::Single), Command::Command8(0x32, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single), Address::Address24(0x000000, SpiDataMode::Single),
@ -148,7 +153,7 @@ fn main() -> ! {
loop { loop {
// quad fast read // quad fast read
let transfer = spi let transfer = spi
.read( .half_duplex_read(
SpiDataMode::Quad, SpiDataMode::Quad,
Command::Command8(0xeb, SpiDataMode::Single), Command::Command8(0xeb, SpiDataMode::Single),
Address::Address32(0x000000 << 8, SpiDataMode::Quad), Address::Address32(0x000000 << 8, SpiDataMode::Quad),

17
examples/src/bin/spi_halfduplex_read_manufacturer_id.rs
View File

@ -33,7 +33,7 @@ use esp_hal::{
gpio::Io, gpio::Io,
prelude::*, prelude::*,
spi::{ spi::{
master::{Address, Command, HalfDuplexReadWrite, Spi}, master::{Address, Command, Spi},
SpiDataMode, SpiDataMode,
SpiMode, SpiMode,
}, },
@ -63,15 +63,20 @@ fn main() -> ! {
} }
} }
let mut spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(sclk, mosi, miso, sio2, sio3, cs); .with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_sio2(sio2)
.with_sio3(sio3)
.with_cs(cs);
let delay = Delay::new(); let delay = Delay::new();
loop { loop {
// READ MANUFACTURER ID FROM FLASH CHIP // READ MANUFACTURER ID FROM FLASH CHIP
let mut data = [0u8; 2]; let mut data = [0u8; 2];
spi.read( spi.half_duplex_read(
SpiDataMode::Single, SpiDataMode::Single,
Command::Command8(0x90, SpiDataMode::Single), Command::Command8(0x90, SpiDataMode::Single),
Address::Address24(0x000000, SpiDataMode::Single), Address::Address24(0x000000, SpiDataMode::Single),
@ -84,7 +89,7 @@ fn main() -> ! {
// READ MANUFACTURER ID FROM FLASH CHIP // READ MANUFACTURER ID FROM FLASH CHIP
let mut data = [0u8; 2]; let mut data = [0u8; 2];
spi.read( spi.half_duplex_read(
SpiDataMode::Dual, SpiDataMode::Dual,
Command::Command8(0x92, SpiDataMode::Single), Command::Command8(0x92, SpiDataMode::Single),
Address::Address32(0x000000_00, SpiDataMode::Dual), Address::Address32(0x000000_00, SpiDataMode::Dual),
@ -97,7 +102,7 @@ fn main() -> ! {
// READ MANUFACTURER ID FROM FLASH CHIP // READ MANUFACTURER ID FROM FLASH CHIP
let mut data = [0u8; 2]; let mut data = [0u8; 2];
spi.read( spi.half_duplex_read(
SpiDataMode::Quad, SpiDataMode::Quad,
Command::Command8(0x94, SpiDataMode::Single), Command::Command8(0x94, SpiDataMode::Single),
Address::Address32(0x000000_00, SpiDataMode::Quad), Address::Address32(0x000000_00, SpiDataMode::Quad),

11
examples/src/bin/spi_loopback.rs
View File

@ -19,6 +19,7 @@ use esp_backtrace as _;
use esp_hal::{ use esp_hal::{
delay::Delay, delay::Delay,
gpio::Io, gpio::Io,
peripheral::Peripheral,
prelude::*, prelude::*,
spi::{master::Spi, SpiMode}, spi::{master::Spi, SpiMode},
}; };
@ -33,11 +34,13 @@ fn main() -> ! {
let miso_mosi = io.pins.gpio2; let miso_mosi = io.pins.gpio2;
let cs = io.pins.gpio5; let cs = io.pins.gpio5;
let miso = miso_mosi.peripheral_input(); let miso = unsafe { miso_mosi.clone_unchecked() };
let mosi = miso_mosi.into_peripheral_output();
let mut spi = let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0).with_pins(sclk, mosi, miso, cs); .with_sck(sclk)
.with_mosi(miso_mosi)
.with_miso(miso)
.with_cs(cs);
let delay = Delay::new(); let delay = Delay::new();

7
examples/src/bin/spi_loopback_dma.rs
View File

@ -54,7 +54,10 @@ fn main() -> ! {
let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap(); let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(sclk, mosi, miso, cs) .with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_cs(cs)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
let delay = Delay::new(); let delay = Delay::new();
@ -71,7 +74,7 @@ fn main() -> ! {
i = i.wrapping_add(1); i = i.wrapping_add(1);
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
// here we could do something else while DMA transfer is in progress // here we could do something else while DMA transfer is in progress

14
examples/src/bin/spi_loopback_dma_psram.rs
View File

@ -2,7 +2,7 @@
//! //!
//! The following wiring is assumed: //! The following wiring is assumed:
//! - SCLK => GPIO42 //! - SCLK => GPIO42
//! - MISO => (loopback to MOSI via peripheral_input()) //! - MISO => (looped back to MOSI via the GPIO MUX)
//! - MOSI => GPIO48 //! - MOSI => GPIO48
//! - CS => GPIO38 //! - CS => GPIO38
//! //!
@ -27,6 +27,7 @@ use esp_hal::{
delay::Delay, delay::Delay,
dma::{Dma, DmaBufBlkSize, DmaPriority, DmaRxBuf, DmaTxBuf}, dma::{Dma, DmaBufBlkSize, DmaPriority, DmaRxBuf, DmaTxBuf},
gpio::Io, gpio::Io,
peripheral::Peripheral,
prelude::*, prelude::*,
spi::{master::Spi, SpiMode}, spi::{master::Spi, SpiMode},
}; };
@ -62,7 +63,7 @@ fn main() -> ! {
let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
let sclk = io.pins.gpio42; let sclk = io.pins.gpio42;
let mosi = io.pins.gpio48; let mosi = io.pins.gpio48;
let miso = mosi.peripheral_input(); let miso = unsafe { mosi.clone_unchecked() };
let cs = io.pins.gpio38; let cs = io.pins.gpio38;
let dma = Dma::new(peripherals.DMA); let dma = Dma::new(peripherals.DMA);
@ -87,8 +88,13 @@ fn main() -> ! {
rx_descriptors.len() rx_descriptors.len()
); );
let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap(); let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
// Need to set miso first so that mosi can overwrite the
// output connection (because we are using the same pin to loop back)
let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let mut spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_pins(sclk, mosi, miso, cs) .with_sck(sclk)
.with_miso(miso)
.with_mosi(mosi)
.with_cs(cs)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
delay.delay_millis(100); // delay to let the above messages display delay.delay_millis(100); // delay to let the above messages display
@ -105,7 +111,7 @@ fn main() -> ! {
i = i.wrapping_add(1); i = i.wrapping_add(1);
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();

14
examples/src/bin/spi_slave_dma.rs
View File

@ -107,11 +107,9 @@ fn main() -> ! {
println!("Iteration {i}"); println!("Iteration {i}");
println!("Do `dma_transfer`"); println!("Do `transfer`");
let transfer = spi let transfer = spi.transfer(&mut slave_receive, &mut slave_send).unwrap();
.dma_transfer(&mut slave_receive, &mut slave_send)
.unwrap();
bitbang_master( bitbang_master(
master_send, master_send,
@ -133,9 +131,9 @@ fn main() -> ! {
delay.delay_millis(250); delay.delay_millis(250);
println!("Do `dma_read`"); println!("Do `read`");
slave_receive.fill(0xff); slave_receive.fill(0xff);
let transfer = spi.dma_read(&mut slave_receive).unwrap(); let transfer = spi.read(&mut slave_receive).unwrap();
bitbang_master( bitbang_master(
master_send, master_send,
@ -155,8 +153,8 @@ fn main() -> ! {
delay.delay_millis(250); delay.delay_millis(250);
println!("Do `dma_write`"); println!("Do `write`");
let transfer = spi.dma_write(&mut slave_send).unwrap(); let transfer = spi.write(&mut slave_send).unwrap();
master_receive.fill(0); master_receive.fill(0);

3
hil-test/tests/embassy_interrupt_spi_dma.rs
View File

@ -15,7 +15,6 @@ use esp_hal::{
prelude::*, prelude::*,
spi::{ spi::{
master::{Spi, SpiDma}, master::{Spi, SpiDma},
FullDuplexMode,
SpiMode, SpiMode,
}, },
timer::{timg::TimerGroup, AnyTimer}, timer::{timg::TimerGroup, AnyTimer},
@ -34,7 +33,7 @@ macro_rules! mk_static {
} }
#[embassy_executor::task] #[embassy_executor::task]
async fn interrupt_driven_task(spi: SpiDma<'static, FullDuplexMode, Async>) { async fn interrupt_driven_task(spi: SpiDma<'static, Async>) {
let mut ticker = Ticker::every(Duration::from_millis(1)); let mut ticker = Ticker::every(Duration::from_millis(1));
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(128); let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(128);

60
hil-test/tests/qspi.rs
View File

@ -10,11 +10,10 @@ use esp_hal::pcnt::{channel::EdgeMode, unit::Unit, Pcnt};
use esp_hal::{ use esp_hal::{
dma::{Channel, Dma, DmaPriority, DmaRxBuf, DmaTxBuf}, dma::{Channel, Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
dma_buffers, dma_buffers,
gpio::{AnyPin, Input, Io, Level, NoPin, Output, Pull}, gpio::{AnyPin, Input, Io, Level, Output, Pull},
prelude::*, prelude::*,
spi::{ spi::{
master::{Address, Command, Spi, SpiDma}, master::{Address, Command, Spi, SpiDma},
HalfDuplexMode,
SpiDataMode, SpiDataMode,
SpiMode, SpiMode,
}, },
@ -38,7 +37,7 @@ cfg_if::cfg_if! {
} }
} }
type SpiUnderTest = SpiDma<'static, HalfDuplexMode, Blocking>; type SpiUnderTest = SpiDma<'static, Blocking>;
struct Context { struct Context {
spi: esp_hal::peripherals::SPI2, spi: esp_hal::peripherals::SPI2,
@ -54,7 +53,7 @@ fn transfer_read(
command: Command, command: Command,
) -> (SpiUnderTest, DmaRxBuf) { ) -> (SpiUnderTest, DmaRxBuf) {
let transfer = spi let transfer = spi
.read(SpiDataMode::Quad, command, Address::None, 0, dma_rx_buf) .half_duplex_read(SpiDataMode::Quad, command, Address::None, 0, dma_rx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
transfer.wait() transfer.wait()
@ -67,7 +66,7 @@ fn transfer_write(
command_data_mode: SpiDataMode, command_data_mode: SpiDataMode,
) -> (SpiUnderTest, DmaTxBuf) { ) -> (SpiUnderTest, DmaTxBuf) {
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Quad, SpiDataMode::Quad,
Command::Command8(write as u16, command_data_mode), Command::Command8(write as u16, command_data_mode),
Address::Address24( Address::Address24(
@ -226,8 +225,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, pin, NoPin, NoPin, NoPin, NoPin) .with_mosi(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_read(spi, pin_mirror, 0b0001_0001); super::execute_read(spi, pin_mirror, 0b0001_0001);
@ -239,8 +238,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, pin, NoPin, NoPin, NoPin) .with_miso(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_read(spi, pin_mirror, 0b0010_0010); super::execute_read(spi, pin_mirror, 0b0010_0010);
@ -252,8 +251,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, NoPin, pin, NoPin, NoPin) .with_sio2(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_read(spi, pin_mirror, 0b0100_0100); super::execute_read(spi, pin_mirror, 0b0100_0100);
@ -265,8 +264,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, NoPin, NoPin, pin, NoPin) .with_sio3(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_read(spi, pin_mirror, 0b1000_1000); super::execute_read(spi, pin_mirror, 0b1000_1000);
@ -278,8 +277,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, pin, NoPin, NoPin, NoPin, NoPin) .with_mosi(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write_read(spi, pin_mirror, 0b0001_0001); super::execute_write_read(spi, pin_mirror, 0b0001_0001);
@ -291,8 +290,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, pin, NoPin, NoPin, NoPin) .with_miso(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write_read(spi, pin_mirror, 0b0010_0010); super::execute_write_read(spi, pin_mirror, 0b0010_0010);
@ -304,8 +303,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, NoPin, pin, NoPin, NoPin) .with_sio2(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write_read(spi, pin_mirror, 0b0100_0100); super::execute_write_read(spi, pin_mirror, 0b0100_0100);
@ -317,8 +316,8 @@ mod tests {
let [pin, pin_mirror, _] = ctx.gpios; let [pin, pin_mirror, _] = ctx.gpios;
let pin_mirror = Output::new(pin_mirror, Level::High); let pin_mirror = Output::new(pin_mirror, Level::High);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, NoPin, NoPin, NoPin, pin, NoPin) .with_sio3(pin)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write_read(spi, pin_mirror, 0b1000_1000); super::execute_write_read(spi, pin_mirror, 0b1000_1000);
@ -341,8 +340,8 @@ mod tests {
.channel0 .channel0
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment); .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, mosi, NoPin, NoPin, NoPin, NoPin) .with_mosi(mosi)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write(unit0, unit1, spi, 0b0000_0001, false); super::execute_write(unit0, unit1, spi, 0b0000_0001, false);
@ -370,8 +369,9 @@ mod tests {
.channel0 .channel0
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment); .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, mosi, gpio, NoPin, NoPin, NoPin) .with_mosi(mosi)
.with_miso(gpio)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write(unit0, unit1, spi, 0b0000_0010, true); super::execute_write(unit0, unit1, spi, 0b0000_0010, true);
@ -399,8 +399,9 @@ mod tests {
.channel0 .channel0
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment); .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, mosi, NoPin, gpio, NoPin, NoPin) .with_mosi(mosi)
.with_sio2(gpio)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write(unit0, unit1, spi, 0b0000_0100, true); super::execute_write(unit0, unit1, spi, 0b0000_0100, true);
@ -428,8 +429,9 @@ mod tests {
.channel0 .channel0
.set_input_mode(EdgeMode::Hold, EdgeMode::Increment); .set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
let spi = Spi::new_half_duplex(ctx.spi, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(ctx.spi, 100.kHz(), SpiMode::Mode0)
.with_pins(NoPin, mosi, NoPin, NoPin, gpio, NoPin) .with_mosi(mosi)
.with_sio3(gpio)
.with_dma(ctx.dma_channel); .with_dma(ctx.dma_channel);
super::execute_write(unit0, unit1, spi, 0b0000_1000, true); super::execute_write(unit0, unit1, spi, 0b0000_1000, true);

42
hil-test/tests/spi_full_duplex.rs
View File

@ -15,8 +15,9 @@ use esp_hal::{
dma::{Dma, DmaDescriptor, DmaPriority, DmaRxBuf, DmaTxBuf}, dma::{Dma, DmaDescriptor, DmaPriority, DmaRxBuf, DmaTxBuf},
dma_buffers, dma_buffers,
gpio::{Io, Level, NoPin}, gpio::{Io, Level, NoPin},
peripheral::Peripheral,
prelude::*, prelude::*,
spi::{master::Spi, FullDuplexMode, SpiMode}, spi::{master::Spi, SpiMode},
}; };
#[cfg(pcnt)] #[cfg(pcnt)]
use esp_hal::{ use esp_hal::{
@ -34,7 +35,7 @@ cfg_if::cfg_if! {
} }
struct Context { struct Context {
spi: Spi<'static, FullDuplexMode>, spi: Spi<'static>,
dma_channel: DmaChannelCreator, dma_channel: DmaChannelCreator,
// Reuse the really large buffer so we don't run out of DRAM with many tests // Reuse the really large buffer so we don't run out of DRAM with many tests
rx_buffer: &'static mut [u8], rx_buffer: &'static mut [u8],
@ -72,11 +73,12 @@ mod tests {
#[cfg(pcnt)] #[cfg(pcnt)]
let mosi_loopback_pcnt = mosi.peripheral_input(); let mosi_loopback_pcnt = mosi.peripheral_input();
let mosi_loopback = mosi.peripheral_input(); // Need to set miso first so that mosi can overwrite the
// output connection (because we are using the same pin to loop back)
let spi = Spi::new(peripherals.SPI2, 10000.kHz(), SpiMode::Mode0) let spi = Spi::new(peripherals.SPI2, 10000.kHz(), SpiMode::Mode0)
.with_sck(sclk) .with_sck(sclk)
.with_mosi(mosi) .with_miso(unsafe { mosi.clone_unchecked() })
.with_miso(mosi_loopback); .with_mosi(mosi);
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000); let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
@ -209,11 +211,11 @@ mod tests {
for i in 1..4 { for i in 1..4 {
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]); dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
(spi, dma_rx_buf) = transfer.wait(); (spi, dma_rx_buf) = transfer.wait();
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]); assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
(spi, dma_tx_buf) = transfer.wait(); (spi, dma_tx_buf) = transfer.wait();
assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _); assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
} }
@ -242,12 +244,12 @@ mod tests {
for i in 1..4 { for i in 1..4 {
dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]); dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
(spi, dma_rx_buf) = transfer.wait(); (spi, dma_rx_buf) = transfer.wait();
assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]); assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait(); (spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@ -274,7 +276,7 @@ mod tests {
dma_tx_buf.as_mut_slice()[0] = i as u8; dma_tx_buf.as_mut_slice()[0] = i as u8;
*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8; *dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
@ -300,7 +302,7 @@ mod tests {
.spi .spi
.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait(); let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
@ -311,7 +313,7 @@ mod tests {
dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]); dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait(); let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@ -469,18 +471,18 @@ mod tests {
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]); dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
let (spi, dma_tx_buf) = transfer.wait(); let (spi, dma_tx_buf) = transfer.wait();
dma_rx_buf.as_mut_slice().fill(0); dma_rx_buf.as_mut_slice().fill(0);
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let (spi, mut dma_rx_buf) = transfer.wait(); let (spi, mut dma_rx_buf) = transfer.wait();
let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
let (spi, _dma_tx_buf) = transfer.wait(); let (spi, _dma_tx_buf) = transfer.wait();
dma_rx_buf.as_mut_slice().fill(0); dma_rx_buf.as_mut_slice().fill(0);
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap(); let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
let (_, dma_rx_buf) = transfer.wait(); let (_, dma_rx_buf) = transfer.wait();
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice()); assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
@ -503,7 +505,7 @@ mod tests {
.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
let mut transfer = spi let mut transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
@ -526,7 +528,7 @@ mod tests {
.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
let mut transfer = spi let mut transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
@ -536,7 +538,7 @@ mod tests {
spi.change_bus_frequency(10000.kHz()); spi.change_bus_frequency(10000.kHz());
let transfer = spi let transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();
@ -561,7 +563,7 @@ mod tests {
); );
let mut transfer = spi let mut transfer = spi
.dma_transfer(dma_rx_buf, dma_tx_buf) .transfer(dma_rx_buf, dma_tx_buf)
.map_err(|e| e.0) .map_err(|e| e.0)
.unwrap(); .unwrap();

15
hil-test/tests/spi_half_duplex_read.rs
View File

@ -11,8 +11,7 @@ use esp_hal::{
gpio::{Io, Level, Output}, gpio::{Io, Level, Output},
prelude::*, prelude::*,
spi::{ spi::{
master::{Address, Command, HalfDuplexReadWrite, Spi, SpiDma}, master::{Address, Command, Spi, SpiDma},
HalfDuplexMode,
SpiDataMode, SpiDataMode,
SpiMode, SpiMode,
}, },
@ -21,7 +20,7 @@ use esp_hal::{
use hil_test as _; use hil_test as _;
struct Context { struct Context {
spi: SpiDma<'static, HalfDuplexMode, Blocking>, spi: SpiDma<'static, Blocking>,
miso_mirror: Output<'static>, miso_mirror: Output<'static>,
} }
@ -50,7 +49,7 @@ mod tests {
} }
} }
let spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_sck(sclk) .with_sck(sclk)
.with_miso(miso) .with_miso(miso)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
@ -72,7 +71,7 @@ mod tests {
let mut spi = ctx.spi; let mut spi = ctx.spi;
let transfer = spi let transfer = spi
.read( .half_duplex_read(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -89,7 +88,7 @@ mod tests {
ctx.miso_mirror.set_high(); ctx.miso_mirror.set_high();
let transfer = spi let transfer = spi
.read( .half_duplex_read(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -120,7 +119,7 @@ mod tests {
ctx.miso_mirror.set_low(); ctx.miso_mirror.set_low();
let mut buffer = [0xAA; DMA_BUFFER_SIZE]; let mut buffer = [0xAA; DMA_BUFFER_SIZE];
spi.read( spi.half_duplex_read(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -134,7 +133,7 @@ mod tests {
// SPI should read '1's from the MISO pin // SPI should read '1's from the MISO pin
ctx.miso_mirror.set_high(); ctx.miso_mirror.set_high();
spi.read( spi.half_duplex_read(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,

15
hil-test/tests/spi_half_duplex_write.rs
View File

@ -12,8 +12,7 @@ use esp_hal::{
pcnt::{channel::EdgeMode, unit::Unit, Pcnt}, pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
prelude::*, prelude::*,
spi::{ spi::{
master::{Address, Command, HalfDuplexReadWrite, Spi, SpiDma}, master::{Address, Command, Spi, SpiDma},
HalfDuplexMode,
SpiDataMode, SpiDataMode,
SpiMode, SpiMode,
}, },
@ -22,7 +21,7 @@ use esp_hal::{
use hil_test as _; use hil_test as _;
struct Context { struct Context {
spi: SpiDma<'static, HalfDuplexMode, Blocking>, spi: SpiDma<'static, Blocking>,
pcnt_unit: Unit<'static, 0>, pcnt_unit: Unit<'static, 0>,
pcnt_source: InputSignal, pcnt_source: InputSignal,
} }
@ -53,7 +52,7 @@ mod tests {
let mosi_loopback = mosi.peripheral_input(); let mosi_loopback = mosi.peripheral_input();
let spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_sck(sclk) .with_sck(sclk)
.with_mosi(mosi) .with_mosi(mosi)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
@ -84,7 +83,7 @@ mod tests {
dma_tx_buf.fill(&[0b0110_1010; DMA_BUFFER_SIZE]); dma_tx_buf.fill(&[0b0110_1010; DMA_BUFFER_SIZE]);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -98,7 +97,7 @@ mod tests {
assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _); assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -130,7 +129,7 @@ mod tests {
let buffer = [0b0110_1010; DMA_BUFFER_SIZE]; let buffer = [0b0110_1010; DMA_BUFFER_SIZE];
// Write the buffer where each byte has 3 pos edges. // Write the buffer where each byte has 3 pos edges.
spi.write( spi.half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -141,7 +140,7 @@ mod tests {
assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _); assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _);
spi.write( spi.half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,

15
hil-test/tests/spi_half_duplex_write_psram.rs
View File

@ -14,8 +14,7 @@ use esp_hal::{
pcnt::{channel::EdgeMode, unit::Unit, Pcnt}, pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
prelude::*, prelude::*,
spi::{ spi::{
master::{Address, Command, HalfDuplexReadWrite, Spi, SpiDma}, master::{Address, Command, Spi, SpiDma},
HalfDuplexMode,
SpiDataMode, SpiDataMode,
SpiMode, SpiMode,
}, },
@ -39,7 +38,7 @@ macro_rules! dma_alloc_buffer {
} }
struct Context { struct Context {
spi: SpiDma<'static, HalfDuplexMode, Blocking>, spi: SpiDma<'static, Blocking>,
pcnt_unit: Unit<'static, 0>, pcnt_unit: Unit<'static, 0>,
pcnt_source: InputSignal, pcnt_source: InputSignal,
} }
@ -65,7 +64,7 @@ mod tests {
let mosi_loopback = mosi.peripheral_input(); let mosi_loopback = mosi.peripheral_input();
let spi = Spi::new_half_duplex(peripherals.SPI2, 100.kHz(), SpiMode::Mode0) let spi = Spi::new(peripherals.SPI2, 100.kHz(), SpiMode::Mode0)
.with_sck(sclk) .with_sck(sclk)
.with_mosi(mosi) .with_mosi(mosi)
.with_dma(dma_channel.configure(false, DmaPriority::Priority0)); .with_dma(dma_channel.configure(false, DmaPriority::Priority0));
@ -99,7 +98,7 @@ mod tests {
// Fill the buffer where each byte has 3 pos edges. // Fill the buffer where each byte has 3 pos edges.
dma_tx_buf.fill(&[0b0110_1010; DMA_BUFFER_SIZE]); dma_tx_buf.fill(&[0b0110_1010; DMA_BUFFER_SIZE]);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -113,7 +112,7 @@ mod tests {
assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _); assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _);
let transfer = spi let transfer = spi
.write( .half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -151,7 +150,7 @@ mod tests {
let buffer = [0b0110_1010; DMA_BUFFER_SIZE]; let buffer = [0b0110_1010; DMA_BUFFER_SIZE];
// Write the buffer where each byte has 3 pos edges. // Write the buffer where each byte has 3 pos edges.
spi.write( spi.half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,
@ -162,7 +161,7 @@ mod tests {
assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _); assert_eq!(unit.get_value(), (3 * DMA_BUFFER_SIZE) as _);
spi.write( spi.half_duplex_write(
SpiDataMode::Single, SpiDataMode::Single,
Command::None, Command::None,
Address::None, Address::None,

6
hil-test/tests/spi_slave.rs
View File

@ -12,7 +12,7 @@ use esp_hal::{
dma::{Dma, DmaPriority}, dma::{Dma, DmaPriority},
dma_buffers, dma_buffers,
gpio::{interconnect::InputSignal, Io, Level, Output, PeripheralInput}, gpio::{interconnect::InputSignal, Io, Level, Output, PeripheralInput},
spi::{slave::Spi, FullDuplexMode, SpiMode}, spi::{slave::Spi, SpiMode},
}; };
use hil_test as _; use hil_test as _;
@ -25,7 +25,7 @@ cfg_if::cfg_if! {
} }
struct Context { struct Context {
spi: Spi<'static, FullDuplexMode>, spi: Spi<'static>,
dma_channel: DmaChannelCreator, dma_channel: DmaChannelCreator,
bitbang_spi: BitbangSpi, bitbang_spi: BitbangSpi,
} }
@ -170,7 +170,7 @@ mod tests {
} }
slave_receive.fill(0xFF); slave_receive.fill(0xFF);
let transfer = spi.dma_transfer(slave_receive, &slave_send).unwrap(); let transfer = spi.transfer(slave_receive, &slave_send).unwrap();
ctx.bitbang_spi.transfer_buf(master_receive, master_send); ctx.bitbang_spi.transfer_buf(master_receive, master_send);