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Minor, exploratory SHA cleanup (#3931)

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* Add sha_dma metadata

* Move SHA interrupt to metadata

* Minor SHA cleanups
This commit is contained in:
Dániel Buga 2025-08-13 16:23:09 +02:00 committed by GitHub
parent 3a85c6efe4
commit 2f1a5cc101
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
16 changed files with 208 additions and 150 deletions
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52
esp-hal/src/sha.rs
View File

@ -62,14 +62,18 @@ use core::{borrow::Borrow, convert::Infallible, marker::PhantomData, mem::size_o
/// Re-export digest for convenience
pub use digest::Digest;
#[cfg(not(esp32))]
use crate::peripherals::Interrupt;
use crate::{
peripherals::SHA,
reg_access::{AlignmentHelper, SocDependentEndianess},
system::GenericPeripheralGuard,
};
// ESP32 quirks:
// - Big endian text register (what about hash?)
// - Text and hash is in the same register -> needs an additional load operation to place the hash
// in the text registers
// - Each algorithm has its own register cluster
/// The SHA Accelerator driver instance
pub struct Sha<'d> {
sha: SHA<'d>,
@ -104,25 +108,21 @@ impl<'d> Sha<'d> {
impl crate::private::Sealed for Sha<'_> {}
#[cfg(not(esp32))]
#[cfg(sha_dma)]
#[instability::unstable]
impl crate::interrupt::InterruptConfigurable for Sha<'_> {
fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) {
for core in crate::system::Cpu::other() {
crate::interrupt::disable(core, Interrupt::SHA);
}
unsafe { crate::interrupt::bind_interrupt(Interrupt::SHA, handler.handler()) };
unwrap!(crate::interrupt::enable(Interrupt::SHA, handler.priority()));
self.sha.disable_peri_interrupt();
self.sha.bind_peri_interrupt(handler.handler());
self.sha.enable_peri_interrupt(handler.priority());
}
}
// A few notes on this implementation with regards to 'memcpy',
// - The registers are *not* cleared after processing, so padding needs to be written out
// - This component uses core::intrinsics::volatile_* which is unstable, but is the only way to
// efficiently copy memory with volatile
// - For this particular registers (and probably others), a full u32 needs to be written partial
// register writes (i.e. in u8 mode) does not work
// - This means that we need to buffer bytes coming in up to 4 u8's in order to create a full u32
// - Registers need to be written one u32 at a time, no u8 access
// - This means that we need to buffer bytes coming in up to 4 u8's in order to create a full u32
/// An active digest
///
@ -220,6 +220,8 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> ShaDigest<'d, A, S> {
let length = (self.cursor as u64 * 8).to_be_bytes();
nb::block!(self.update(&[0x80]))?; // Append "1" bit
let chunk_len = A::CHUNK_LENGTH;
// Flush partial data, ensures aligned cursor
{
while self.is_busy() {}
@ -231,22 +233,22 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> ShaDigest<'d, A, S> {
let flushed = self.alignment_helper.flush_to(
m_mem(&self.sha.borrow().sha, 0),
(self.cursor % A::CHUNK_LENGTH) / self.alignment_helper.align_size(),
(self.cursor % chunk_len) / self.alignment_helper.align_size(),
);
self.cursor = self.cursor.wrapping_add(flushed);
if flushed > 0 && self.cursor.is_multiple_of(A::CHUNK_LENGTH) {
if flushed > 0 && self.cursor.is_multiple_of(chunk_len) {
self.process_buffer();
while self.is_busy() {}
}
}
debug_assert!(self.cursor.is_multiple_of(4));
let mod_cursor = self.cursor % A::CHUNK_LENGTH;
if (A::CHUNK_LENGTH - mod_cursor) < A::CHUNK_LENGTH / 8 {
let mut mod_cursor = self.cursor % chunk_len;
if (chunk_len - mod_cursor) < chunk_len / 8 {
// Zero out remaining data if buffer is almost full (>=448/896), and process
// buffer
let pad_len = A::CHUNK_LENGTH - mod_cursor;
let pad_len = chunk_len - mod_cursor;
self.alignment_helper.volatile_write(
m_mem(&self.sha.borrow().sha, 0),
0_u8,
@ -256,14 +258,14 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> ShaDigest<'d, A, S> {
self.process_buffer();
self.cursor = self.cursor.wrapping_add(pad_len);
debug_assert_eq!(self.cursor % A::CHUNK_LENGTH, 0);
debug_assert_eq!(self.cursor % chunk_len, 0);
mod_cursor = 0;
// Spin-wait for finish
while self.is_busy() {}
}
let mod_cursor = self.cursor % A::CHUNK_LENGTH; // Should be zero if branched above
let pad_len = A::CHUNK_LENGTH - mod_cursor - size_of::<u64>();
let pad_len = chunk_len - mod_cursor - size_of::<u64>();
self.alignment_helper.volatile_write(
m_mem(&self.sha.borrow().sha, 0),
@ -275,8 +277,8 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> ShaDigest<'d, A, S> {
self.alignment_helper.aligned_volatile_copy(
m_mem(&self.sha.borrow().sha, 0),
&length,
A::CHUNK_LENGTH / self.alignment_helper.align_size(),
(A::CHUNK_LENGTH - size_of::<u64>()) / self.alignment_helper.align_size(),
chunk_len / self.alignment_helper.align_size(),
(chunk_len - size_of::<u64>()) / self.alignment_helper.align_size(),
);
self.process_buffer();
@ -386,8 +388,8 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> ShaDigest<'d, A, S> {
}
}
let mod_cursor = self.cursor % A::CHUNK_LENGTH;
let chunk_len = A::CHUNK_LENGTH;
let mod_cursor = self.cursor % chunk_len;
let (remaining, bound_reached) = self.alignment_helper.aligned_volatile_copy(
m_mem(&self.sha.borrow().sha, 0),
@ -539,7 +541,7 @@ impl<'d, A: ShaAlgorithm, S: Borrow<Sha<'d>>> digest::FixedOutput for ShaDigest<
/// This macro implements the Sha<'a, Dm> trait for a specified Sha algorithm
/// and a set of parameters
macro_rules! impl_sha {
($name: ident, $mode_bits: tt, $digest_length: tt, $chunk_length: tt) => {
($name: ident, $mode_bits: literal, $digest_length: literal, $chunk_length: literal) => {
/// A SHA implementation struct.
///
/// This struct is generated by the macro and represents a specific SHA hashing

13
esp-metadata-generated/src/_build_script_utils.rs
View File

@ -562,6 +562,7 @@ impl Chip {
"i2c_master_fifo_size=\"16\"",
"interrupts_status_registers=\"2\"",
"rng_apb_cycle_wait_num=\"16\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -678,6 +679,7 @@ impl Chip {
"cargo:rustc-cfg=i2c_master_fifo_size=\"16\"",
"cargo:rustc-cfg=interrupts_status_registers=\"2\"",
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -828,6 +830,7 @@ impl Chip {
"rng_apb_cycle_wait_num=\"16\"",
"rsa_size_increment=\"32\"",
"rsa_memory_size_bytes=\"384\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -974,6 +977,7 @@ impl Chip {
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=rsa_size_increment=\"32\"",
"cargo:rustc-cfg=rsa_memory_size_bytes=\"384\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -1178,6 +1182,7 @@ impl Chip {
"rng_apb_cycle_wait_num=\"16\"",
"rsa_size_increment=\"32\"",
"rsa_memory_size_bytes=\"384\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -1380,6 +1385,7 @@ impl Chip {
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=rsa_size_increment=\"32\"",
"cargo:rustc-cfg=rsa_memory_size_bytes=\"384\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -1562,6 +1568,7 @@ impl Chip {
"rng_apb_cycle_wait_num=\"16\"",
"rsa_size_increment=\"32\"",
"rsa_memory_size_bytes=\"384\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -1738,6 +1745,7 @@ impl Chip {
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=rsa_size_increment=\"32\"",
"cargo:rustc-cfg=rsa_memory_size_bytes=\"384\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -1910,6 +1918,7 @@ impl Chip {
"rng_apb_cycle_wait_num=\"16\"",
"rsa_size_increment=\"32\"",
"rsa_memory_size_bytes=\"512\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -2082,6 +2091,7 @@ impl Chip {
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=rsa_size_increment=\"32\"",
"cargo:rustc-cfg=rsa_memory_size_bytes=\"512\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -2274,6 +2284,7 @@ impl Chip {
"rng_apb_cycle_wait_num=\"16\"",
"rsa_size_increment=\"32\"",
"rsa_memory_size_bytes=\"512\"",
"sha_dma",
"sha_algo_sha_1",
"sha_algo_sha_224",
"sha_algo_sha_256",
@ -2462,6 +2473,7 @@ impl Chip {
"cargo:rustc-cfg=rng_apb_cycle_wait_num=\"16\"",
"cargo:rustc-cfg=rsa_size_increment=\"32\"",
"cargo:rustc-cfg=rsa_memory_size_bytes=\"512\"",
"cargo:rustc-cfg=sha_dma",
"cargo:rustc-cfg=sha_algo_sha_1",
"cargo:rustc-cfg=sha_algo_sha_224",
"cargo:rustc-cfg=sha_algo_sha_256",
@ -2666,6 +2678,7 @@ impl Config {
println!("cargo:rustc-check-cfg=cfg(i2c_master_has_arbitration_en)");
println!("cargo:rustc-check-cfg=cfg(i2c_master_has_tx_fifo_watermark)");
println!("cargo:rustc-check-cfg=cfg(i2c_master_bus_timeout_is_exponential)");
println!("cargo:rustc-check-cfg=cfg(sha_dma)");
println!("cargo:rustc-check-cfg=cfg(sha_algo_sha_224)");
println!("cargo:rustc-check-cfg=cfg(timergroup_timg_has_divcnt_rst)");
println!("cargo:rustc-check-cfg=cfg(timergroup_default_clock_source_is_set)");

3
esp-metadata-generated/src/_generated_esp32.rs
View File

@ -195,6 +195,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(512)
};
("sha.dma") => {
false
};
("spi_master.has_octal") => {
false
};

13
esp-metadata-generated/src/_generated_esp32c2.rs
View File

@ -156,6 +156,9 @@ macro_rules! property {
("rng.apb_cycle_wait_num", str) => {
stringify!(16)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
false
};
@ -333,9 +336,10 @@ macro_rules! for_each_peripheral {
LEDC() (unstable))); _for_each_inner!((RNG <= RNG() (unstable)));
_for_each_inner!((LPWR <= RTC_CNTL() (unstable))); _for_each_inner!((MODEM_CLKRST
<= MODEM_CLKRST() (unstable))); _for_each_inner!((SENSITIVE <= SENSITIVE()
(unstable))); _for_each_inner!((SHA <= SHA() (unstable))); _for_each_inner!((SPI0
<= SPI0() (unstable))); _for_each_inner!((SPI1 <= SPI1() (unstable)));
_for_each_inner!((SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
(unstable))); _for_each_inner!((SHA <= SHA(SHA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
_for_each_inner!((SPI0 <= SPI0() (unstable))); _for_each_inner!((SPI1 <= SPI1()
(unstable))); _for_each_inner!((SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((SYSTEM <=
SYSTEM() (unstable))); _for_each_inner!((SYSTIMER <= SYSTIMER() (unstable)));
_for_each_inner!((TIMG0 <= TIMG0() (unstable))); _for_each_inner!((UART0 <=
@ -367,7 +371,8 @@ macro_rules! for_each_peripheral {
INTERRUPT_CORE0() (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LEDC <= LEDC()
(unstable)), (RNG <= RNG() (unstable)), (LPWR <= RTC_CNTL() (unstable)),
(MODEM_CLKRST <= MODEM_CLKRST() (unstable)), (SENSITIVE <= SENSITIVE()
(unstable)), (SHA <= SHA() (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
(unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM <= SYSTEM()
(unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0() (unstable)),

64
esp-metadata-generated/src/_generated_esp32c3.rs
View File

@ -189,6 +189,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(384)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
false
};
@ -461,34 +464,36 @@ macro_rules! for_each_peripheral {
<= RNG() (unstable))); _for_each_inner!((RSA <= RSA(RSA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
_for_each_inner!((LPWR <= RTC_CNTL() (unstable))); _for_each_inner!((SENSITIVE <=
SENSITIVE() (unstable))); _for_each_inner!((SHA <= SHA() (unstable)));
_for_each_inner!((SPI0 <= SPI0() (unstable))); _for_each_inner!((SPI1 <= SPI1()
(unstable))); _for_each_inner!((SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((SYSTEM <=
SYSTEM() (unstable))); _for_each_inner!((SYSTIMER <= SYSTIMER() (unstable)));
_for_each_inner!((TIMG0 <= TIMG0() (unstable))); _for_each_inner!((TIMG1 <=
TIMG1() (unstable))); _for_each_inner!((TWAI0 <= TWAI0() (unstable)));
_for_each_inner!((UART0 <= UART0(UART0 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((UART1 <=
UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }))); _for_each_inner!((UHCI0 <= UHCI0() (unstable)));
_for_each_inner!((UHCI1 <= UHCI1() (unstable))); _for_each_inner!((USB_DEVICE <=
USB_DEVICE(USB_DEVICE : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable))); _for_each_inner!((XTS_AES <= XTS_AES()
(unstable))); _for_each_inner!((DMA_CH0 <= virtual() (unstable)));
_for_each_inner!((DMA_CH1 <= virtual() (unstable))); _for_each_inner!((DMA_CH2 <=
virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <=
virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable)));
_for_each_inner!((TSENS <= virtual() (unstable))); _for_each_inner!((WIFI <=
virtual() (unstable))); _for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <=
virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()),
(GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <=
virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()),
(GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <=
virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()),
(GPIO19 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <= virtual()), (AES <=
AES(AES : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
SENSITIVE() (unstable))); _for_each_inner!((SHA <= SHA(SHA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable))); _for_each_inner!((SPI0 <= SPI0() (unstable)));
_for_each_inner!((SPI1 <= SPI1() (unstable))); _for_each_inner!((SPI2 <=
SPI2(SPI2 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
}))); _for_each_inner!((SYSTEM <= SYSTEM() (unstable)));
_for_each_inner!((SYSTIMER <= SYSTIMER() (unstable))); _for_each_inner!((TIMG0 <=
TIMG0() (unstable))); _for_each_inner!((TIMG1 <= TIMG1() (unstable)));
_for_each_inner!((TWAI0 <= TWAI0() (unstable))); _for_each_inner!((UART0 <=
UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }))); _for_each_inner!((UART1 <= UART1(UART1 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })));
_for_each_inner!((UHCI0 <= UHCI0() (unstable))); _for_each_inner!((UHCI1 <=
UHCI1() (unstable))); _for_each_inner!((USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable))); _for_each_inner!((XTS_AES <= XTS_AES() (unstable)));
_for_each_inner!((DMA_CH0 <= virtual() (unstable))); _for_each_inner!((DMA_CH1 <=
virtual() (unstable))); _for_each_inner!((DMA_CH2 <= virtual() (unstable)));
_for_each_inner!((ADC1 <= virtual() (unstable))); _for_each_inner!((ADC2 <=
virtual() (unstable))); _for_each_inner!((BT <= virtual() (unstable)));
_for_each_inner!((SW_INTERRUPT <= virtual() (unstable))); _for_each_inner!((TSENS
<= virtual() (unstable))); _for_each_inner!((WIFI <= virtual() (unstable)));
_for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
(GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
(GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
(GPIO20 <= virtual()), (GPIO21 <= virtual()), (AES <= AES(AES : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <= APB_SARADC()
(unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (BB <= BB()
(unstable)), (DMA <= DMA() (unstable)), (DS <= DS() (unstable)), (EFUSE <=
@ -503,7 +508,8 @@ macro_rules! for_each_peripheral {
(RMT <= RMT() (unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (LPWR <= RTC_CNTL() (unstable)), (SENSITIVE <= SENSITIVE()
(unstable)), (SHA <= SHA() (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
(unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM <= SYSTEM()
(unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0() (unstable)),

9
esp-metadata-generated/src/_generated_esp32c6.rs
View File

@ -195,6 +195,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(384)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
false
};
@ -498,7 +501,8 @@ macro_rules! for_each_peripheral {
PMU() (unstable))); _for_each_inner!((RMT <= RMT() (unstable)));
_for_each_inner!((RNG <= RNG() (unstable))); _for_each_inner!((RSA <= RSA(RSA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable))); _for_each_inner!((SHA <= SHA() (unstable)));
(unstable))); _for_each_inner!((SHA <= SHA(SHA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
_for_each_inner!((SLCHOST <= SLCHOST() (unstable))); _for_each_inner!((ETM <=
SOC_ETM() (unstable))); _for_each_inner!((SPI0 <= SPI0() (unstable)));
_for_each_inner!((SPI1 <= SPI1() (unstable))); _for_each_inner!((SPI2 <=
@ -564,7 +568,8 @@ macro_rules! for_each_peripheral {
(unstable)), (PCNT <= PCNT() (unstable)), (PCR <= PCR() (unstable)), (PLIC_MX <=
PLIC_MX() (unstable)), (PMU <= PMU() (unstable)), (RMT <= RMT() (unstable)), (RNG
<= RNG() (unstable)), (RSA <= RSA(RSA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SHA <= SHA()
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SHA <= SHA(SHA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (SLCHOST <= SLCHOST() (unstable)), (ETM <= SOC_ETM() (unstable)),
(SPI0 <= SPI0() (unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM

9
esp-metadata-generated/src/_generated_esp32h2.rs
View File

@ -189,6 +189,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(384)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
false
};
@ -477,7 +480,8 @@ macro_rules! for_each_peripheral {
_for_each_inner!((RMT <= RMT() (unstable))); _for_each_inner!((RNG <= RNG()
(unstable))); _for_each_inner!((RSA <= RSA(RSA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
_for_each_inner!((SHA <= SHA() (unstable))); _for_each_inner!((ETM <= SOC_ETM()
_for_each_inner!((SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable))); _for_each_inner!((ETM <= SOC_ETM()
(unstable))); _for_each_inner!((SPI0 <= SPI0() (unstable)));
_for_each_inner!((SPI1 <= SPI1() (unstable))); _for_each_inner!((SPI2 <=
SPI2(SPI2 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
@ -536,7 +540,8 @@ macro_rules! for_each_peripheral {
<= PAU() (unstable)), (PCNT <= PCNT() (unstable)), (PCR <= PCR() (unstable)),
(PLIC_MX <= PLIC_MX() (unstable)), (PMU <= PMU() (unstable)), (RMT <= RMT()
(unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SHA <= SHA()
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SHA <= SHA(SHA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (ETM <= SOC_ETM() (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM <= PCR() (unstable)),

9
esp-metadata-generated/src/_generated_esp32s2.rs
View File

@ -195,6 +195,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(512)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
true
};
@ -504,7 +507,8 @@ macro_rules! for_each_peripheral {
}) (unstable))); _for_each_inner!((LPWR <= RTC_CNTL() (unstable)));
_for_each_inner!((RTC_I2C <= RTC_I2C() (unstable))); _for_each_inner!((RTC_IO <=
RTC_IO() (unstable))); _for_each_inner!((SENS <= SENS() (unstable)));
_for_each_inner!((SHA <= SHA() (unstable))); _for_each_inner!((SPI0 <= SPI0()
_for_each_inner!((SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable))); _for_each_inner!((SPI0 <= SPI0()
(unstable))); _for_each_inner!((SPI1 <= SPI1() (unstable)));
_for_each_inner!((SPI2 <= SPI2(SPI2_DMA : { bind_dma_interrupt,
enable_dma_interrupt, disable_dma_interrupt }, SPI2 : { bind_peri_interrupt,
@ -559,7 +563,8 @@ macro_rules! for_each_peripheral {
(unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (LPWR <= RTC_CNTL()
(unstable)), (RTC_I2C <= RTC_I2C() (unstable)), (RTC_IO <= RTC_IO() (unstable)),
(SENS <= SENS() (unstable)), (SHA <= SHA() (unstable)), (SPI0 <= SPI0()
(SENS <= SENS() (unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0()
(unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <= SPI2(SPI2_DMA : {
bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }, SPI2 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SPI3 <=

166
esp-metadata-generated/src/_generated_esp32s3.rs
View File

@ -189,6 +189,9 @@ macro_rules! property {
("rsa.memory_size_bytes", str) => {
stringify!(512)
};
("sha.dma") => {
true
};
("spi_master.has_octal") => {
true
};
@ -506,89 +509,92 @@ macro_rules! for_each_peripheral {
_for_each_inner!((RTC_I2C <= RTC_I2C() (unstable))); _for_each_inner!((RTC_IO <=
RTC_IO() (unstable))); _for_each_inner!((SDHOST <= SDHOST() (unstable)));
_for_each_inner!((SENS <= SENS() (unstable))); _for_each_inner!((SENSITIVE <=
SENSITIVE() (unstable))); _for_each_inner!((SHA <= SHA() (unstable)));
_for_each_inner!((SPI0 <= SPI0() (unstable))); _for_each_inner!((SPI1 <= SPI1()
(unstable))); _for_each_inner!((SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((SPI3 <=
SPI3(SPI3 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
}))); _for_each_inner!((SYSTEM <= SYSTEM() (unstable)));
_for_each_inner!((SYSTIMER <= SYSTIMER() (unstable))); _for_each_inner!((TIMG0 <=
TIMG0() (unstable))); _for_each_inner!((TIMG1 <= TIMG1() (unstable)));
_for_each_inner!((TWAI0 <= TWAI0() (unstable))); _for_each_inner!((UART0 <=
UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }))); _for_each_inner!((UART1 <= UART1(UART1 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })));
_for_each_inner!((UART2 <= UART2(UART2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((UHCI0 <=
UHCI0() (unstable))); _for_each_inner!((UHCI1 <= UHCI1() (unstable)));
_for_each_inner!((USB0 <= USB0() (unstable))); _for_each_inner!((USB_DEVICE <=
USB_DEVICE(USB_DEVICE : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable))); _for_each_inner!((USB_WRAP <= USB_WRAP()
(unstable))); _for_each_inner!((WCL <= WCL() (unstable)));
_for_each_inner!((XTS_AES <= XTS_AES() (unstable))); _for_each_inner!((DMA_CH0 <=
virtual() (unstable))); _for_each_inner!((DMA_CH1 <= virtual() (unstable)));
_for_each_inner!((DMA_CH2 <= virtual() (unstable))); _for_each_inner!((DMA_CH3 <=
virtual() (unstable))); _for_each_inner!((DMA_CH4 <= virtual() (unstable)));
_for_each_inner!((ADC1 <= virtual() (unstable))); _for_each_inner!((ADC2 <=
virtual() (unstable))); _for_each_inner!((BT <= virtual() (unstable)));
_for_each_inner!((CPU_CTRL <= virtual() (unstable))); _for_each_inner!((PSRAM <=
virtual() (unstable))); _for_each_inner!((SW_INTERRUPT <= virtual() (unstable)));
_for_each_inner!((ULP_RISCV_CORE <= virtual() (unstable)));
_for_each_inner!((WIFI <= virtual() (unstable))); _for_each_inner!((all(GPIO0 <=
virtual()), (GPIO1 <= virtual()), (GPIO2 <= virtual()), (GPIO3 <= virtual()),
(GPIO4 <= virtual()), (GPIO5 <= virtual()), (GPIO6 <= virtual()), (GPIO7 <=
virtual()), (GPIO8 <= virtual()), (GPIO9 <= virtual()), (GPIO10 <= virtual()),
(GPIO11 <= virtual()), (GPIO12 <= virtual()), (GPIO13 <= virtual()), (GPIO14 <=
virtual()), (GPIO15 <= virtual()), (GPIO16 <= virtual()), (GPIO17 <= virtual()),
(GPIO18 <= virtual()), (GPIO19 <= virtual()), (GPIO20 <= virtual()), (GPIO21 <=
virtual()), (GPIO26 <= virtual()), (GPIO27 <= virtual()), (GPIO28 <= virtual()),
(GPIO29 <= virtual()), (GPIO30 <= virtual()), (GPIO31 <= virtual()), (GPIO32 <=
virtual()), (GPIO33 <= virtual()), (GPIO34 <= virtual()), (GPIO35 <= virtual()),
(GPIO36 <= virtual()), (GPIO37 <= virtual()), (GPIO38 <= virtual()), (GPIO39 <=
virtual()), (GPIO40 <= virtual()), (GPIO41 <= virtual()), (GPIO42 <= virtual()),
(GPIO43 <= virtual()), (GPIO44 <= virtual()), (GPIO45 <= virtual()), (GPIO46 <=
virtual()), (GPIO47 <= virtual()), (GPIO48 <= virtual()), (AES <= AES(AES : {
SENSITIVE() (unstable))); _for_each_inner!((SHA <= SHA(SHA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (APB_CTRL <= APB_CTRL() (unstable)), (APB_SARADC <= APB_SARADC()
(unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (DMA <= DMA()
(unstable)), (DS <= DS() (unstable)), (EFUSE <= EFUSE() (unstable)), (EXTMEM <=
EXTMEM() (unstable)), (GPIO <= GPIO() (unstable)), (GPIO_SD <= GPIO_SD()
(unstable)), (HMAC <= HMAC() (unstable)), (I2C0 <= I2C0(I2C_EXT0 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (I2C1 <=
I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (I2S1 <= I2S1(I2S1
: { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (INTERRUPT_CORE1
<= INTERRUPT_CORE1() (unstable)), (IO_MUX <= IO_MUX() (unstable)), (LCD_CAM <=
LCD_CAM() (unstable)), (LEDC <= LEDC() (unstable)), (LPWR <= RTC_CNTL()
(unstable)), (MCPWM0 <= MCPWM0() (unstable)), (MCPWM1 <= MCPWM1() (unstable)),
(PCNT <= PCNT() (unstable)), (PERI_BACKUP <= PERI_BACKUP() (unstable)), (RMT <=
RMT() (unstable)), (RNG <= RNG() (unstable)), (RSA <= RSA(RSA : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (RTC_CNTL <= RTC_CNTL() (unstable)), (RTC_I2C <= RTC_I2C()
(unstable)), (RTC_IO <= RTC_IO() (unstable)), (SDHOST <= SDHOST() (unstable)),
(SENS <= SENS() (unstable)), (SENSITIVE <= SENSITIVE() (unstable)), (SHA <= SHA()
(unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <= SPI1() (unstable)), (SPI2 <=
(unstable))); _for_each_inner!((SPI0 <= SPI0() (unstable)));
_for_each_inner!((SPI1 <= SPI1() (unstable))); _for_each_inner!((SPI2 <=
SPI2(SPI2 : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
})), (SPI3 <= SPI3(SPI3 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (SYSTEM <= SYSTEM() (unstable)), (SYSTIMER <=
SYSTIMER() (unstable)), (TIMG0 <= TIMG0() (unstable)), (TIMG1 <= TIMG1()
(unstable)), (TWAI0 <= TWAI0() (unstable)), (UART0 <= UART0(UART0 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UART1 <=
}))); _for_each_inner!((SPI3 <= SPI3(SPI3 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((SYSTEM <=
SYSTEM() (unstable))); _for_each_inner!((SYSTIMER <= SYSTIMER() (unstable)));
_for_each_inner!((TIMG0 <= TIMG0() (unstable))); _for_each_inner!((TIMG1 <=
TIMG1() (unstable))); _for_each_inner!((TWAI0 <= TWAI0() (unstable)));
_for_each_inner!((UART0 <= UART0(UART0 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }))); _for_each_inner!((UART1 <=
UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (UART2 <= UART2(UART2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (UHCI0 <= UHCI0() (unstable)),
(UHCI1 <= UHCI1() (unstable)), (USB0 <= USB0() (unstable)), (USB_DEVICE <=
USB_DEVICE(USB_DEVICE : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (USB_WRAP <= USB_WRAP() (unstable)), (WCL
<= WCL() (unstable)), (XTS_AES <= XTS_AES() (unstable)), (DMA_CH0 <= virtual()
(unstable)), (DMA_CH1 <= virtual() (unstable)), (DMA_CH2 <= virtual()
(unstable)), (DMA_CH3 <= virtual() (unstable)), (DMA_CH4 <= virtual()
(unstable)), (ADC1 <= virtual() (unstable)), (ADC2 <= virtual() (unstable)), (BT
<= virtual() (unstable)), (CPU_CTRL <= virtual() (unstable)), (PSRAM <= virtual()
(unstable)), (SW_INTERRUPT <= virtual() (unstable)), (ULP_RISCV_CORE <= virtual()
(unstable)), (WIFI <= virtual() (unstable))));
disable_peri_interrupt }))); _for_each_inner!((UART2 <= UART2(UART2 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })));
_for_each_inner!((UHCI0 <= UHCI0() (unstable))); _for_each_inner!((UHCI1 <=
UHCI1() (unstable))); _for_each_inner!((USB0 <= USB0() (unstable)));
_for_each_inner!((USB_DEVICE <= USB_DEVICE(USB_DEVICE : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
_for_each_inner!((USB_WRAP <= USB_WRAP() (unstable))); _for_each_inner!((WCL <=
WCL() (unstable))); _for_each_inner!((XTS_AES <= XTS_AES() (unstable)));
_for_each_inner!((DMA_CH0 <= virtual() (unstable))); _for_each_inner!((DMA_CH1 <=
virtual() (unstable))); _for_each_inner!((DMA_CH2 <= virtual() (unstable)));
_for_each_inner!((DMA_CH3 <= virtual() (unstable))); _for_each_inner!((DMA_CH4 <=
virtual() (unstable))); _for_each_inner!((ADC1 <= virtual() (unstable)));
_for_each_inner!((ADC2 <= virtual() (unstable))); _for_each_inner!((BT <=
virtual() (unstable))); _for_each_inner!((CPU_CTRL <= virtual() (unstable)));
_for_each_inner!((PSRAM <= virtual() (unstable))); _for_each_inner!((SW_INTERRUPT
<= virtual() (unstable))); _for_each_inner!((ULP_RISCV_CORE <= virtual()
(unstable))); _for_each_inner!((WIFI <= virtual() (unstable)));
_for_each_inner!((all(GPIO0 <= virtual()), (GPIO1 <= virtual()), (GPIO2 <=
virtual()), (GPIO3 <= virtual()), (GPIO4 <= virtual()), (GPIO5 <= virtual()),
(GPIO6 <= virtual()), (GPIO7 <= virtual()), (GPIO8 <= virtual()), (GPIO9 <=
virtual()), (GPIO10 <= virtual()), (GPIO11 <= virtual()), (GPIO12 <= virtual()),
(GPIO13 <= virtual()), (GPIO14 <= virtual()), (GPIO15 <= virtual()), (GPIO16 <=
virtual()), (GPIO17 <= virtual()), (GPIO18 <= virtual()), (GPIO19 <= virtual()),
(GPIO20 <= virtual()), (GPIO21 <= virtual()), (GPIO26 <= virtual()), (GPIO27 <=
virtual()), (GPIO28 <= virtual()), (GPIO29 <= virtual()), (GPIO30 <= virtual()),
(GPIO31 <= virtual()), (GPIO32 <= virtual()), (GPIO33 <= virtual()), (GPIO34 <=
virtual()), (GPIO35 <= virtual()), (GPIO36 <= virtual()), (GPIO37 <= virtual()),
(GPIO38 <= virtual()), (GPIO39 <= virtual()), (GPIO40 <= virtual()), (GPIO41 <=
virtual()), (GPIO42 <= virtual()), (GPIO43 <= virtual()), (GPIO44 <= virtual()),
(GPIO45 <= virtual()), (GPIO46 <= virtual()), (GPIO47 <= virtual()), (GPIO48 <=
virtual()), (AES <= AES(AES : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (APB_CTRL <= APB_CTRL() (unstable)),
(APB_SARADC <= APB_SARADC() (unstable)), (ASSIST_DEBUG <= ASSIST_DEBUG()
(unstable)), (DMA <= DMA() (unstable)), (DS <= DS() (unstable)), (EFUSE <=
EFUSE() (unstable)), (EXTMEM <= EXTMEM() (unstable)), (GPIO <= GPIO()
(unstable)), (GPIO_SD <= GPIO_SD() (unstable)), (HMAC <= HMAC() (unstable)),
(I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (I2S0 <= I2S0(I2S0 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
(unstable)), (I2S1 <= I2S1(I2S1 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (INTERRUPT_CORE0 <= INTERRUPT_CORE0()
(unstable)), (INTERRUPT_CORE1 <= INTERRUPT_CORE1() (unstable)), (IO_MUX <=
IO_MUX() (unstable)), (LCD_CAM <= LCD_CAM() (unstable)), (LEDC <= LEDC()
(unstable)), (LPWR <= RTC_CNTL() (unstable)), (MCPWM0 <= MCPWM0() (unstable)),
(MCPWM1 <= MCPWM1() (unstable)), (PCNT <= PCNT() (unstable)), (PERI_BACKUP <=
PERI_BACKUP() (unstable)), (RMT <= RMT() (unstable)), (RNG <= RNG() (unstable)),
(RSA <= RSA(RSA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (RTC_CNTL <= RTC_CNTL() (unstable)),
(RTC_I2C <= RTC_I2C() (unstable)), (RTC_IO <= RTC_IO() (unstable)), (SDHOST <=
SDHOST() (unstable)), (SENS <= SENS() (unstable)), (SENSITIVE <= SENSITIVE()
(unstable)), (SHA <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt }) (unstable)), (SPI0 <= SPI0() (unstable)), (SPI1 <=
SPI1() (unstable)), (SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (SPI3 <= SPI3(SPI3 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (SYSTEM
<= SYSTEM() (unstable)), (SYSTIMER <= SYSTIMER() (unstable)), (TIMG0 <= TIMG0()
(unstable)), (TIMG1 <= TIMG1() (unstable)), (TWAI0 <= TWAI0() (unstable)), (UART0
<= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
disable_peri_interrupt })), (UART1 <= UART1(UART1 : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt })), (UART2 <= UART2(UART2 : {
bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (UHCI0 <=
UHCI0() (unstable)), (UHCI1 <= UHCI1() (unstable)), (USB0 <= USB0() (unstable)),
(USB_DEVICE <= USB_DEVICE(USB_DEVICE : { bind_peri_interrupt,
enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (USB_WRAP <=
USB_WRAP() (unstable)), (WCL <= WCL() (unstable)), (XTS_AES <= XTS_AES()
(unstable)), (DMA_CH0 <= virtual() (unstable)), (DMA_CH1 <= virtual()
(unstable)), (DMA_CH2 <= virtual() (unstable)), (DMA_CH3 <= virtual()
(unstable)), (DMA_CH4 <= virtual() (unstable)), (ADC1 <= virtual() (unstable)),
(ADC2 <= virtual() (unstable)), (BT <= virtual() (unstable)), (CPU_CTRL <=
virtual() (unstable)), (PSRAM <= virtual() (unstable)), (SW_INTERRUPT <=
virtual() (unstable)), (ULP_RISCV_CORE <= virtual() (unstable)), (WIFI <=
virtual() (unstable))));
};
}
/// This macro can be used to generate code for each `GPIOn` instance.

3
esp-metadata/devices/esp32c2.toml
View File

@ -31,7 +31,7 @@ peripherals = [
{ name = "LPWR", pac = "RTC_CNTL" },
{ name = "MODEM_CLKRST" },
{ name = "SENSITIVE" },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "SPI0" },
{ name = "SPI1" },
{ name = "SPI2", interrupts = { peri = "SPI2" } },
@ -250,6 +250,7 @@ status_registers = 2
[device.sha]
support_status = "partial"
dma = true
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]

3
esp-metadata/devices/esp32c3.toml
View File

@ -39,7 +39,7 @@ peripherals = [
{ name = "RSA", interrupts = { peri = "RSA" } },
{ name = "LPWR", pac = "RTC_CNTL" },
{ name = "SENSITIVE" },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "SPI0" },
{ name = "SPI1" },
{ name = "SPI2", interrupts = { peri = "SPI2" } },
@ -312,6 +312,7 @@ memory_size_bytes = 384
[device.sha]
support_status = "partial"
dma = true
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]

3
esp-metadata/devices/esp32c6.toml
View File

@ -64,7 +64,7 @@ peripherals = [
{ name = "RMT" },
{ name = "RNG" },
{ name = "RSA", interrupts = { peri = "RSA" } },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "SLCHOST" },
{ name = "ETM", pac = "SOC_ETM" },
{ name = "SPI0" },
@ -467,6 +467,7 @@ memory_size_bytes = 384
[device.sha]
support_status = "partial"
dma = true
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]

3
esp-metadata/devices/esp32h2.toml
View File

@ -57,7 +57,7 @@ peripherals = [
{ name = "RMT" },
{ name = "RNG" },
{ name = "RSA", interrupts = { peri = "RSA" } },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "ETM", pac = "SOC_ETM" },
{ name = "SPI0" },
{ name = "SPI1" },
@ -384,6 +384,7 @@ memory_size_bytes = 384
[device.sha]
support_status = "partial"
dma = true
algo = ["SHA-1", "SHA-224", "SHA-256"]
[device.spi_master]

3
esp-metadata/devices/esp32s2.toml
View File

@ -41,7 +41,7 @@ peripherals = [
{ name = "RTC_I2C" },
{ name = "RTC_IO" },
{ name = "SENS" },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "SPI0" },
{ name = "SPI1" },
{ name = "SPI2", interrupts = { peri = "SPI2", dma = "SPI2_DMA" } },
@ -428,6 +428,7 @@ memory_size_bytes = 512
[device.sha]
support_status = "partial"
dma = true
algo = [
"SHA-1",
"SHA-224",

3
esp-metadata/devices/esp32s3.toml
View File

@ -47,7 +47,7 @@ peripherals = [
{ name = "SDHOST" },
{ name = "SENS" },
{ name = "SENSITIVE" },
{ name = "SHA" },
{ name = "SHA", interrupts = { peri = "SHA" } },
{ name = "SPI0" },
{ name = "SPI1" },
{ name = "SPI2", interrupts = { peri = "SPI2" } },
@ -604,6 +604,7 @@ memory_size_bytes = 512
[device.sha]
support_status = "partial"
dma = true
algo = [
"SHA-1",
"SHA-224",

2
esp-metadata/src/cfg.rs
View File

@ -498,6 +498,8 @@ driver_configs![
driver: sha,
name: "SHA",
properties: {
#[serde(default)]
dma: bool,
#[serde(default)]
algo: Vec<String>,
}