cleans up some timg fixmes, allows for use of timers without eh02 (#1367)

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Scott Mabin 2024-04-01 13:43:18 +01:00 committed by GitHub
parent b8b041b51a
commit 32587d7569
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4 changed files with 44 additions and 34 deletions

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@ -31,6 +31,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Changed
- TIMG: Allow use without the embedded-hal-02 traits in scope (#1367)
- DMA: use channel clusters
- Remove `Ext32` and `RateExtU64` from prelude
- Prefer mutable references over moving for DMA transactions (#1238)

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@ -305,9 +305,3 @@ impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
}
}
// TODO USB pins
// implement marker traits on USB pins
// impl<T> crate::otg_fs::UsbSel for Gpio??<T> {}
// impl<T> crate::otg_fs::UsbDp for Gpio27<T> {}
// impl<T> crate::otg_fs::UsbDm for Gpio26<T> {}

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@ -224,7 +224,6 @@ where
/// General-purpose Timer driver
pub struct Timer<T> {
timg: T,
#[allow(dead_code)] // FIXME
apb_clk_freq: HertzU32,
}
@ -232,7 +231,7 @@ impl<T> Timer<T>
where
T: Instance,
{
/// Create a new timer instance
/// Create a new timer instance.
pub fn new(timg: T, apb_clk_freq: HertzU32) -> Self {
// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
// way to select the XTAL_CLK.
@ -242,6 +241,46 @@ where
Self { timg, apb_clk_freq }
}
/// Start the timer with the given time period.
pub fn start(&mut self, timeout: MicrosDurationU64) {
self.timg.set_counter_active(false);
self.timg.set_alarm_active(false);
self.timg.reset_counter();
// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
// way to select the XTAL_CLK.
// TODO: can we cache the divider (only get it on initialization)?
let ticks = timeout_to_ticks(timeout, self.apb_clk_freq, self.timg.divider());
self.timg.load_alarm_value(ticks);
self.timg.set_counter_decrementing(false);
self.timg.set_auto_reload(true);
self.timg.set_counter_active(true);
self.timg.set_alarm_active(true);
}
/// Check if the timer has elapsed
pub fn has_elapsed(&mut self) -> bool {
if !self.timg.is_counter_active() {
panic!("Called wait on an inactive timer!")
}
if self.timg.is_interrupt_set() {
self.timg.clear_interrupt();
self.timg.set_alarm_active(true);
true
} else {
false
}
}
/// Block until the timer has elasped.
pub fn wait(&mut self) {
while !self.has_elapsed() {}
}
/// Return the raw interface to the underlying timer instance
pub fn free(self) -> T {
self.timg
@ -478,7 +517,6 @@ where
}
}
#[allow(dead_code)] // FIXME
fn timeout_to_ticks<T, F>(timeout: T, clock: F, divider: u32) -> u64
where
T: Into<MicrosDurationU64>,
@ -505,32 +543,11 @@ where
where
Time: Into<Self::Time>,
{
self.timg.set_counter_active(false);
self.timg.set_alarm_active(false);
self.timg.reset_counter();
// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
// way to select the XTAL_CLK.
// TODO: can we cache the divider (only get it on initialization)?
let ticks = timeout_to_ticks(timeout, self.apb_clk_freq, self.timg.divider());
self.timg.load_alarm_value(ticks);
self.timg.set_counter_decrementing(false);
self.timg.set_auto_reload(true);
self.timg.set_counter_active(true);
self.timg.set_alarm_active(true);
(*self).start(timeout.into())
}
fn wait(&mut self) -> nb::Result<(), Void> {
if !self.timg.is_counter_active() {
panic!("Called wait on an inactive timer!")
}
if self.timg.is_interrupt_set() {
self.timg.clear_interrupt();
self.timg.set_alarm_active(true);
if self.has_elapsed() {
Ok(())
} else {
Err(nb::Error::WouldBlock)

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@ -3,7 +3,6 @@
//! There is TIMG0 which contains a general purpose timer and a watchdog timer.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
//% FEATURES: embedded-hal-02
#![no_std]
#![no_main]
@ -11,7 +10,6 @@
use core::cell::RefCell;
use critical_section::Mutex;
use embedded_hal_02::timer::CountDown;
use esp_backtrace as _;
use esp_hal::{
clock::ClockControl,