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cleans up some timg fixmes, allows for use of timers without eh02 (#1367)
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@ -31,6 +31,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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### Changed
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- TIMG: Allow use without the embedded-hal-02 traits in scope (#1367)
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- DMA: use channel clusters
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- Remove `Ext32` and `RateExtU64` from prelude
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- Prefer mutable references over moving for DMA transactions (#1238)
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@ -305,9 +305,3 @@ impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
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unsafe { &*GPIO::PTR }.pcpu_nmi_int().read().bits()
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}
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}
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// TODO USB pins
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// implement marker traits on USB pins
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// impl<T> crate::otg_fs::UsbSel for Gpio??<T> {}
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// impl<T> crate::otg_fs::UsbDp for Gpio27<T> {}
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// impl<T> crate::otg_fs::UsbDm for Gpio26<T> {}
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@ -224,7 +224,6 @@ where
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/// General-purpose Timer driver
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pub struct Timer<T> {
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timg: T,
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#[allow(dead_code)] // FIXME
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apb_clk_freq: HertzU32,
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}
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@ -232,7 +231,7 @@ impl<T> Timer<T>
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where
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T: Instance,
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{
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/// Create a new timer instance
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/// Create a new timer instance.
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pub fn new(timg: T, apb_clk_freq: HertzU32) -> Self {
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// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
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// way to select the XTAL_CLK.
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@ -242,6 +241,46 @@ where
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Self { timg, apb_clk_freq }
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}
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/// Start the timer with the given time period.
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pub fn start(&mut self, timeout: MicrosDurationU64) {
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self.timg.set_counter_active(false);
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self.timg.set_alarm_active(false);
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self.timg.reset_counter();
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// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
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// way to select the XTAL_CLK.
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// TODO: can we cache the divider (only get it on initialization)?
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let ticks = timeout_to_ticks(timeout, self.apb_clk_freq, self.timg.divider());
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self.timg.load_alarm_value(ticks);
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self.timg.set_counter_decrementing(false);
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self.timg.set_auto_reload(true);
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self.timg.set_counter_active(true);
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self.timg.set_alarm_active(true);
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}
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/// Check if the timer has elapsed
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pub fn has_elapsed(&mut self) -> bool {
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if !self.timg.is_counter_active() {
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panic!("Called wait on an inactive timer!")
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}
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if self.timg.is_interrupt_set() {
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self.timg.clear_interrupt();
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self.timg.set_alarm_active(true);
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true
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} else {
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false
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}
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}
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/// Block until the timer has elasped.
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pub fn wait(&mut self) {
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while !self.has_elapsed() {}
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}
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/// Return the raw interface to the underlying timer instance
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pub fn free(self) -> T {
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self.timg
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@ -478,7 +517,6 @@ where
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}
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}
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#[allow(dead_code)] // FIXME
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fn timeout_to_ticks<T, F>(timeout: T, clock: F, divider: u32) -> u64
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where
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T: Into<MicrosDurationU64>,
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@ -505,32 +543,11 @@ where
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where
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Time: Into<Self::Time>,
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{
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self.timg.set_counter_active(false);
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self.timg.set_alarm_active(false);
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self.timg.reset_counter();
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// TODO: this currently assumes APB_CLK is being used, as we don't yet have a
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// way to select the XTAL_CLK.
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// TODO: can we cache the divider (only get it on initialization)?
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let ticks = timeout_to_ticks(timeout, self.apb_clk_freq, self.timg.divider());
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self.timg.load_alarm_value(ticks);
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self.timg.set_counter_decrementing(false);
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self.timg.set_auto_reload(true);
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self.timg.set_counter_active(true);
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self.timg.set_alarm_active(true);
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(*self).start(timeout.into())
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}
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fn wait(&mut self) -> nb::Result<(), Void> {
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if !self.timg.is_counter_active() {
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panic!("Called wait on an inactive timer!")
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}
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if self.timg.is_interrupt_set() {
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self.timg.clear_interrupt();
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self.timg.set_alarm_active(true);
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if self.has_elapsed() {
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Ok(())
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} else {
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Err(nb::Error::WouldBlock)
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@ -3,7 +3,6 @@
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//! There is TIMG0 which contains a general purpose timer and a watchdog timer.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: embedded-hal-02
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#![no_std]
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#![no_main]
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@ -11,7 +10,6 @@
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use core::cell::RefCell;
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use critical_section::Mutex;
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use embedded_hal_02::timer::CountDown;
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use esp_backtrace as _;
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use esp_hal::{
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clock::ClockControl,
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