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Update xtensa-lx-rt, fix interrupt related examples

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This commit is contained in:
bjoernQ 2022-04-04 17:38:12 +02:00 committed by Jesse Braham
parent 13ae45b4b9
commit 43c8f34e5f
10 changed files with 27 additions and 25 deletions
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2
esp-hal-common/Cargo.toml
View File

@ -26,7 +26,7 @@ riscv-atomic-emulation-trap = { version = "0.1", optional = true }
xtensa-lx = { version = "0.6", optional = true }
# Xtensa Runtime
xtensa-lx-rt = { version = "0.10.0", optional = true }
xtensa-lx-rt = { version = "0.11.0", optional = true }
# Part of `ufmt` containing only `uWrite` trait
ufmt-write = { version = "0.1", optional = true }

2
esp32-hal/Cargo.toml
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@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
nb = "1.0"
void = { version = "1.0", default-features = false }
xtensa-lx = { version = "0.6.0", features = ["esp32"] }
xtensa-lx-rt = { version = "0.10.0", features = ["esp32"], optional = true }
xtensa-lx-rt = { version = "0.11.0", features = ["esp32"], optional = true }
[dependencies.esp-hal-common]
path = "../esp-hal-common"

4
esp32-hal/examples/gpio_interrupt.rs
View File

@ -65,7 +65,9 @@ fn main() -> ! {
let mut delay = Delay::new();
unsafe {
xtensa_lx::interrupt::enable();
xtensa_lx::interrupt::enable_mask(
1 << 1
);
}
loop {

12
esp32-hal/examples/timer_interrupt.rs
View File

@ -48,7 +48,7 @@ fn main() -> ! {
interrupt::enable(
Cpu::ProCpu,
pac::Interrupt::TG1_T0_LEVEL,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
timer1.start(100_000_000u64);
timer1.listen();
@ -62,10 +62,10 @@ fn main() -> ! {
unsafe {
xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
1 << 20,
);
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level4.mask(),
1 << 23,
);
}
@ -98,18 +98,18 @@ pub fn level2_interrupt() {
}
#[no_mangle]
pub fn level4_interrupt() {
pub fn level3_interrupt() {
unsafe {
(&SERIAL).lock(|data| {
let mut serial = data.borrow_mut();
let serial = serial.as_mut().unwrap();
writeln!(serial, "Interrupt Level 4").ok();
writeln!(serial, "Interrupt Level 3").ok();
});
}
interrupt::clear(
Cpu::ProCpu,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
unsafe {

2
esp32s2-hal/Cargo.toml
View File

@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
nb = "1.0"
void = { version = "1.0", default-features = false }
xtensa-lx = { version = "0.6.0", features = ["esp32"] } # FIXME
xtensa-lx-rt = { version = "0.10.0", features = ["esp32s2"], optional = true }
xtensa-lx-rt = { version = "0.11.0", features = ["esp32s2"], optional = true }
[dependencies.esp-hal-common]
path = "../esp-hal-common"

2
esp32s2-hal/examples/gpio_interrupt.rs
View File

@ -65,7 +65,7 @@ fn main() -> ! {
unsafe {
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
1 << 19,
);
}

12
esp32s2-hal/examples/timer_interrupt.rs
View File

@ -48,7 +48,7 @@ fn main() -> ! {
interrupt::enable(
Cpu::ProCpu,
pac::Interrupt::TG1_T0_LEVEL,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
timer1.start(100_000_000u64);
timer1.listen();
@ -62,10 +62,10 @@ fn main() -> ! {
unsafe {
xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
1 << 20,
);
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level4.mask(),
1 << 23,
);
}
@ -98,18 +98,18 @@ pub fn level2_interrupt() {
}
#[no_mangle]
pub fn level4_interrupt() {
pub fn level3_interrupt() {
unsafe {
(&SERIAL).lock(|data| {
let mut serial = data.borrow_mut();
let serial = serial.as_mut().unwrap();
writeln!(serial, "Interrupt Level 4").ok();
writeln!(serial, "Interrupt Level 3").ok();
});
}
interrupt::clear(
Cpu::ProCpu,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
unsafe {

2
esp32s3-hal/Cargo.toml
View File

@ -29,7 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
nb = "1.0"
void = { version = "1.0", default-features = false }
xtensa-lx = { version = "0.6.0", features = ["esp32"] } # FIXME
xtensa-lx-rt = { version = "0.10.0", features = ["esp32s3"], optional = true }
xtensa-lx-rt = { version = "0.11.0", features = ["esp32s3"], optional = true }
[dependencies.esp-hal-common]
path = "../esp-hal-common"

2
esp32s3-hal/examples/gpio_interrupt.rs
View File

@ -65,7 +65,7 @@ fn main() -> ! {
unsafe {
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
1 << 19,
);
}

12
esp32s3-hal/examples/timer_interrupt.rs
View File

@ -48,7 +48,7 @@ fn main() -> ! {
interrupt::enable(
Cpu::ProCpu,
pac::Interrupt::TG1_T0_LEVEL,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
timer1.start(100_000_000u64);
timer1.listen();
@ -62,10 +62,10 @@ fn main() -> ! {
unsafe {
xtensa_lx::interrupt::disable();
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask(),
1 << 20,
);
xtensa_lx::interrupt::enable_mask(
xtensa_lx_rt::interrupt::CpuInterruptLevel::Level4.mask(),
1 << 23,
);
}
@ -98,18 +98,18 @@ pub fn level2_interrupt() {
}
#[no_mangle]
pub fn level4_interrupt() {
pub fn level3_interrupt() {
unsafe {
(&SERIAL).lock(|data| {
let mut serial = data.borrow_mut();
let serial = serial.as_mut().unwrap();
writeln!(serial, "Interrupt Level 4").ok();
writeln!(serial, "Interrupt Level 3").ok();
});
}
interrupt::clear(
Cpu::ProCpu,
interrupt::CpuInterrupt::Interrupt24LevelPriority4,
interrupt::CpuInterrupt::Interrupt23LevelPriority3,
);
unsafe {