diff --git a/CHANGELOG.md b/CHANGELOG.md index a26e340b0..da3a1b220 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,8 +19,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Add PARL_IO TX driver for ESP32-C6 / ESP32-H2 (#733) - Implement `ufmt_write::uWrite` trait for USB Serial JTAG (#751) - Add HMAC peripheral support (#755) -- Add multicore-aware embassy executor for Xtensa MCUs (#723). -- Add interrupt-executor for Xtensa MCUs (#723). - Add PARL_IO RX driver for ESP32-C6 / ESP32-H2 (#760) - Add multicore-aware embassy executor for Xtensa MCUs (#723, #756). - Add interrupt-executor for Xtensa MCUs (#723, #756). @@ -30,6 +28,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - Update the `embedded-hal-*` packages to `1.0.0-rc.1` and implement traits from `embedded-io` and `embedded-io-async` (#747) - Moved AlignmentHelper to its own module (#753) +- Disable all watchdog timers by default at startup (#763) ### Fixed diff --git a/esp-hal-common/src/rtc_cntl/mod.rs b/esp-hal-common/src/rtc_cntl/mod.rs index 1ddf39669..1f63bce61 100644 --- a/esp-hal-common/src/rtc_cntl/mod.rs +++ b/esp-hal-common/src/rtc_cntl/mod.rs @@ -701,6 +701,16 @@ impl Default for Rwdt { /// RTC Watchdog Timer driver impl Rwdt { + /// Enable the watchdog timer instance + pub fn enable(&mut self) { + self.set_enabled(true); + } + + /// Disable the watchdog timer instance + pub fn disable(&mut self) { + self.set_enabled(false); + } + pub fn listen(&mut self) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; @@ -782,7 +792,17 @@ impl Rwdt { } } - /// Enable/disable write protection for WDT registers + pub fn feed(&mut self) { + #[cfg(not(any(esp32c6, esp32h2)))] + let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; + #[cfg(any(esp32c6, esp32h2))] + let rtc_cntl = unsafe { &*LP_WDT::PTR }; + + self.set_write_protection(false); + rtc_cntl.wdtfeed.write(|w| unsafe { w.bits(1) }); + self.set_write_protection(true); + } + fn set_write_protection(&mut self, enable: bool) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; @@ -793,10 +813,8 @@ impl Rwdt { rtc_cntl.wdtwprotect.write(|w| unsafe { w.bits(wkey) }); } -} -impl WatchdogDisable for Rwdt { - fn disable(&mut self) { + fn set_enabled(&mut self, enable: bool) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; #[cfg(any(esp32c6, esp32h2))] @@ -806,26 +824,18 @@ impl WatchdogDisable for Rwdt { rtc_cntl .wdtconfig0 - .modify(|_, w| w.wdt_en().clear_bit().wdt_flashboot_mod_en().clear_bit()); + .modify(|_, w| w.wdt_en().bit(enable).wdt_flashboot_mod_en().bit(enable)); self.set_write_protection(true); } -} -// TODO: this can be refactored -impl WatchdogEnable for Rwdt { - type Time = MicrosDurationU64; - - fn start(&mut self, period: T) - where - T: Into, - { + fn set_timeout(&mut self, timeout: MicrosDurationU64) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; #[cfg(any(esp32c6, esp32h2))] let rtc_cntl = unsafe { &*LP_WDT::PTR }; - let timeout_raw = (period.into().to_millis() * (RtcClock::cycles_to_1ms() as u64)) as u32; + let timeout_raw = (timeout.to_millis() * (RtcClock::cycles_to_1ms() as u64)) as u32; self.set_write_protection(false); unsafe { @@ -835,7 +845,7 @@ impl WatchdogEnable for Rwdt { .modify(|_, w| w.wdt_stg0_hold().bits(timeout_raw)); #[cfg(any(esp32c6, esp32h2))] - (&*LP_WDT::PTR).config1.modify(|_, w| { + rtc_cntl.config1.modify(|_, w| { w.wdt_stg0_hold() .bits(timeout_raw >> (1 + Efuse::get_rwdt_multiplier())) }); @@ -868,16 +878,26 @@ impl WatchdogEnable for Rwdt { } } +impl WatchdogDisable for Rwdt { + fn disable(&mut self) { + self.disable(); + } +} + +impl WatchdogEnable for Rwdt { + type Time = MicrosDurationU64; + + fn start(&mut self, period: T) + where + T: Into, + { + self.set_timeout(period.into()); + } +} + impl Watchdog for Rwdt { fn feed(&mut self) { - #[cfg(not(any(esp32c6, esp32h2)))] - let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; - #[cfg(any(esp32c6, esp32h2))] - let rtc_cntl = unsafe { &*LP_WDT::PTR }; - - self.set_write_protection(false); - rtc_cntl.wdtfeed.write(|w| unsafe { w.bits(1) }); - self.set_write_protection(true); + self.feed(); } } @@ -888,10 +908,16 @@ pub struct Swd; #[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] /// Super Watchdog driver impl Swd { + /// Create a new super watchdog timer instance pub fn new() -> Self { Self } + /// Disable the watchdog timer instance + pub fn disable(&mut self) { + self.set_enabled(false); + } + /// Enable/disable write protection for WDT registers fn set_write_protection(&mut self, enable: bool) { #[cfg(not(any(esp32c6, esp32h2)))] @@ -908,22 +934,28 @@ impl Swd { .swd_wprotect .write(|w| unsafe { w.swd_wkey().bits(wkey) }); } -} -#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] -impl WatchdogDisable for Swd { - fn disable(&mut self) { + fn set_enabled(&mut self, enable: bool) { #[cfg(not(any(esp32c6, esp32h2)))] let rtc_cntl = unsafe { &*RTC_CNTL::PTR }; #[cfg(any(esp32c6, esp32h2))] let rtc_cntl = unsafe { &*LP_WDT::PTR }; self.set_write_protection(false); - rtc_cntl.swd_conf.write(|w| w.swd_auto_feed_en().set_bit()); + rtc_cntl + .swd_conf + .write(|w| w.swd_auto_feed_en().bit(!enable)); self.set_write_protection(true); } } +#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))] +impl WatchdogDisable for Swd { + fn disable(&mut self) { + self.disable(); + } +} + pub fn get_reset_reason(cpu: Cpu) -> Option { let reason = unsafe { rtc_get_reset_reason(cpu as u32) }; let reason = SocResetReason::from_repr(reason as usize); diff --git a/esp-hal-common/src/timer.rs b/esp-hal-common/src/timer.rs index bffaddbfb..e541411c4 100644 --- a/esp-hal-common/src/timer.rs +++ b/esp-hal-common/src/timer.rs @@ -728,13 +728,30 @@ where pub fn new(_peripheral_clock_control: &mut PeripheralClockControl) -> Self { #[cfg(lp_wdt)] _peripheral_clock_control.enable(crate::system::Peripheral::Wdt); + TG::configure_wdt_src_clk(); + Self { phantom: PhantomData::default(), } } - fn set_wdt_enabled(&mut self, enabled: bool) { + /// Enable the watchdog timer instance + pub fn enable(&mut self) { + // SAFETY: The `TG` instance being modified is owned by `self`, which is behind + // a mutable reference. + unsafe { Self::set_wdt_enabled(true) }; + } + + /// Disable the watchdog timer instance + pub fn disable(&mut self) { + // SAFETY: The `TG` instance being modified is owned by `self`, which is behind + // a mutable reference. + unsafe { Self::set_wdt_enabled(false) }; + } + + /// Forcibly enable or disable the watchdog timer + pub unsafe fn set_wdt_enabled(enabled: bool) { let reg_block = unsafe { &*TG::register_block() }; reg_block @@ -817,7 +834,7 @@ where TG: TimerGroupInstance, { fn disable(&mut self) { - self.set_wdt_enabled(false); + self.disable(); } } @@ -831,6 +848,7 @@ where where T: Into, { + self.enable(); self.set_timeout(period.into()); } } diff --git a/esp32-hal/examples/rtc_watchdog.rs b/esp32-hal/examples/rtc_watchdog.rs index d797bc074..49ce8a7be 100644 --- a/esp32-hal/examples/rtc_watchdog.rs +++ b/esp32-hal/examples/rtc_watchdog.rs @@ -28,10 +28,6 @@ fn main() -> ! { let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - // Disable watchdog timer - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); @@ -49,6 +45,8 @@ fn main() -> ! { #[interrupt] fn RTC_CORE() { critical_section::with(|cs| { + esp_println::println!("RWDT Interrupt"); + let mut rwdt = RWDT.borrow_ref_mut(cs); let rwdt = rwdt.as_mut().unwrap(); rwdt.clear_interrupt(); diff --git a/esp32-hal/examples/watchdog.rs b/esp32-hal/examples/watchdog.rs index 0cd19b35c..24620383b 100644 --- a/esp32-hal/examples/watchdog.rs +++ b/esp32-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -29,9 +23,6 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt = timer_group0.wdt; - let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - rtc.rwdt.disable(); wdt.start(2u64.secs()); timer0.start(1u64.secs()); diff --git a/esp32-hal/src/lib.rs b/esp32-hal/src/lib.rs index 2c0e7d0ba..0483159e9 100644 --- a/esp32-hal/src/lib.rs +++ b/esp32-hal/src/lib.rs @@ -94,3 +94,18 @@ pub unsafe extern "C" fn ESP32Reset() -> ! { pub extern "Rust" fn __init_data() -> bool { false } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{RTC_CNTL, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32c2-hal/examples/rtc_watchdog.rs b/esp32c2-hal/examples/rtc_watchdog.rs index f24ada1d1..c0f8ebb78 100644 --- a/esp32c2-hal/examples/rtc_watchdog.rs +++ b/esp32c2-hal/examples/rtc_watchdog.rs @@ -29,11 +29,6 @@ fn main() -> ! { let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32c2-hal/examples/watchdog.rs b/esp32c2-hal/examples/watchdog.rs index 863422eb7..9d6d471db 100644 --- a/esp32c2-hal/examples/watchdog.rs +++ b/esp32c2-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32c2_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32c2_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -22,7 +16,6 @@ fn main() -> ! { let mut system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new( peripherals.TIMG0, &clocks, @@ -31,11 +24,7 @@ fn main() -> ! { let mut timer0 = timer_group0.timer0; let mut wdt0 = timer_group0.wdt; - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); wdt0.start(2u64.secs()); - timer0.start(1u64.secs()); loop { diff --git a/esp32c2-hal/src/lib.rs b/esp32c2-hal/src/lib.rs index e01bc7fe6..c55238a1a 100644 --- a/esp32c2-hal/src/lib.rs +++ b/esp32c2-hal/src/lib.rs @@ -75,3 +75,18 @@ pub use esp_hal_common::*; pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{RTC_CNTL, TIMG0}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32c3-hal/examples/rtc_watchdog.rs b/esp32c3-hal/examples/rtc_watchdog.rs index 5a98e4912..b8f45fd5a 100644 --- a/esp32c3-hal/examples/rtc_watchdog.rs +++ b/esp32c3-hal/examples/rtc_watchdog.rs @@ -29,11 +29,6 @@ fn main() -> ! { let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32c3-hal/examples/watchdog.rs b/esp32c3-hal/examples/watchdog.rs index c070515a9..28452d90a 100644 --- a/esp32c3-hal/examples/watchdog.rs +++ b/esp32c3-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32c3_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32c3_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -22,7 +16,6 @@ fn main() -> ! { let mut system = peripherals.SYSTEM.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.RTC_CNTL); let timer_group0 = TimerGroup::new( peripherals.TIMG0, &clocks, @@ -30,19 +23,8 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt0 = timer_group0.wdt; - let timer_group1 = TimerGroup::new( - peripherals.TIMG1, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt1 = timer_group1.wdt; - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); wdt0.start(2u64.secs()); - wdt1.disable(); - timer0.start(1u64.secs()); loop { diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs index 2e842ecfe..bb28d53a1 100644 --- a/esp32c3-hal/src/lib.rs +++ b/esp32c3-hal/src/lib.rs @@ -205,13 +205,24 @@ unsafe fn configure_mmu() { cache_resume_icache(autoload); } -#[allow(unreachable_code)] #[export_name = "__post_init"] -#[doc(hidden)] #[cfg_attr(feature = "mcu-boot", link_section = ".rwtext")] -pub fn post_init() { +unsafe fn post_init() { #[cfg(feature = "mcu-boot")] unsafe { configure_mmu(); } + + use esp_hal_common::{ + peripherals::{RTC_CNTL, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); } diff --git a/esp32c6-hal/examples/rtc_watchdog.rs b/esp32c6-hal/examples/rtc_watchdog.rs index a3c37f7ff..787746b74 100644 --- a/esp32c6-hal/examples/rtc_watchdog.rs +++ b/esp32c6-hal/examples/rtc_watchdog.rs @@ -15,7 +15,6 @@ use esp32c6_hal::{ peripherals::{self, Peripherals}, prelude::*, riscv, - timer::TimerGroup, Rtc, Rwdt, }; @@ -26,30 +25,10 @@ static RWDT: Mutex>> = Mutex::new(RefCell::new(None)); #[entry] fn main() -> ! { let peripherals = Peripherals::take(); - let mut system = peripherals.PCR.split(); - let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); + let system = peripherals.PCR.split(); + let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let timer_group0 = TimerGroup::new( - peripherals.TIMG0, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt0 = timer_group0.wdt; - let timer_group1 = TimerGroup::new( - peripherals.TIMG1, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt1 = timer_group1.wdt; - - wdt0.disable(); - wdt1.disable(); let mut rtc = Rtc::new(peripherals.LP_CLKRST); - - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32c6-hal/examples/watchdog.rs b/esp32c6-hal/examples/watchdog.rs index 0cf7dad81..4c61b216d 100644 --- a/esp32c6-hal/examples/watchdog.rs +++ b/esp32c6-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32c6_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32c6_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -22,7 +16,6 @@ fn main() -> ! { let mut system = peripherals.PCR.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LP_CLKRST); let timer_group0 = TimerGroup::new( peripherals.TIMG0, &clocks, @@ -30,19 +23,8 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt0 = timer_group0.wdt; - let timer_group1 = TimerGroup::new( - peripherals.TIMG1, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt1 = timer_group1.wdt; - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); wdt0.start(2u64.secs()); - wdt1.disable(); - timer0.start(1u64.secs()); loop { diff --git a/esp32c6-hal/src/lib.rs b/esp32c6-hal/src/lib.rs index fea1935d7..fcc755f8d 100644 --- a/esp32c6-hal/src/lib.rs +++ b/esp32c6-hal/src/lib.rs @@ -73,3 +73,19 @@ pub use esp_hal_common::*; pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{LP_CLKRST, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(LP_CLKRST::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32h2-hal/examples/rtc_watchdog.rs b/esp32h2-hal/examples/rtc_watchdog.rs index 1186f5104..b0fc32ad3 100644 --- a/esp32h2-hal/examples/rtc_watchdog.rs +++ b/esp32h2-hal/examples/rtc_watchdog.rs @@ -15,7 +15,6 @@ use esp32h2_hal::{ peripherals::{self, Peripherals}, prelude::*, riscv, - timer::TimerGroup, Rtc, Rwdt, }; @@ -26,30 +25,10 @@ static RWDT: Mutex>> = Mutex::new(RefCell::new(None)); #[entry] fn main() -> ! { let peripherals = Peripherals::take(); - let mut system = peripherals.PCR.split(); - let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); + let system = peripherals.PCR.split(); + let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let timer_group0 = TimerGroup::new( - peripherals.TIMG0, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt0 = timer_group0.wdt; - let timer_group1 = TimerGroup::new( - peripherals.TIMG1, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt1 = timer_group1.wdt; - - wdt0.disable(); - wdt1.disable(); let mut rtc = Rtc::new(peripherals.LP_CLKRST); - - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); diff --git a/esp32h2-hal/examples/watchdog.rs b/esp32h2-hal/examples/watchdog.rs index 86a77ec87..310d2b15f 100644 --- a/esp32h2-hal/examples/watchdog.rs +++ b/esp32h2-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32h2_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32h2_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -22,7 +16,6 @@ fn main() -> ! { let mut system = peripherals.PCR.split(); let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - let mut rtc = Rtc::new(peripherals.LP_CLKRST); let timer_group0 = TimerGroup::new( peripherals.TIMG0, &clocks, @@ -30,19 +23,8 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt0 = timer_group0.wdt; - let timer_group1 = TimerGroup::new( - peripherals.TIMG1, - &clocks, - &mut system.peripheral_clock_control, - ); - let mut wdt1 = timer_group1.wdt; - // Disable watchdog timers - rtc.swd.disable(); - rtc.rwdt.disable(); wdt0.start(2u64.secs()); - wdt1.disable(); - timer0.start(1u64.secs()); loop { diff --git a/esp32h2-hal/src/lib.rs b/esp32h2-hal/src/lib.rs index 4c924c65c..175db3171 100644 --- a/esp32h2-hal/src/lib.rs +++ b/esp32h2-hal/src/lib.rs @@ -73,3 +73,19 @@ pub use esp_hal_common::*; pub mod analog { pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt}; } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{LP_CLKRST, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(LP_CLKRST::steal()); + rtc.swd.disable(); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32s2-hal/examples/rtc_watchdog.rs b/esp32s2-hal/examples/rtc_watchdog.rs index 88fd14810..c04f1d9b6 100644 --- a/esp32s2-hal/examples/rtc_watchdog.rs +++ b/esp32s2-hal/examples/rtc_watchdog.rs @@ -28,10 +28,6 @@ fn main() -> ! { let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - // Disable watchdog timer - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); @@ -49,6 +45,8 @@ fn main() -> ! { #[interrupt] fn RTC_CORE() { critical_section::with(|cs| { + esp_println::println!("RWDT Interrupt"); + let mut rwdt = RWDT.borrow_ref_mut(cs); let rwdt = rwdt.as_mut().unwrap(); rwdt.clear_interrupt(); diff --git a/esp32s2-hal/examples/watchdog.rs b/esp32s2-hal/examples/watchdog.rs index 330ab7ea8..4b706b9f5 100644 --- a/esp32s2-hal/examples/watchdog.rs +++ b/esp32s2-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32s2_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32s2_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -29,11 +23,8 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt = timer_group0.wdt; - let mut rtc = Rtc::new(peripherals.RTC_CNTL); wdt.start(2u64.secs()); - rtc.rwdt.disable(); - timer0.start(1u64.secs()); loop { diff --git a/esp32s2-hal/src/lib.rs b/esp32s2-hal/src/lib.rs index 0452c7b52..e558c89e5 100644 --- a/esp32s2-hal/src/lib.rs +++ b/esp32s2-hal/src/lib.rs @@ -148,3 +148,18 @@ unsafe fn exception(cause: ExceptionCause, save_frame: &mut trapframe::TrapFrame __user_exception(cause, save_frame); } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{RTC_CNTL, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +} diff --git a/esp32s3-hal/examples/rtc_watchdog.rs b/esp32s3-hal/examples/rtc_watchdog.rs index c9cc8aece..409a9c60f 100644 --- a/esp32s3-hal/examples/rtc_watchdog.rs +++ b/esp32s3-hal/examples/rtc_watchdog.rs @@ -28,10 +28,6 @@ fn main() -> ! { let _clocks = ClockControl::boot_defaults(system.clock_control).freeze(); let mut rtc = Rtc::new(peripherals.RTC_CNTL); - - // Disable watchdog timer - rtc.rwdt.disable(); - rtc.rwdt.start(2000u64.millis()); rtc.rwdt.listen(); @@ -49,6 +45,8 @@ fn main() -> ! { #[interrupt] fn RTC_CORE() { critical_section::with(|cs| { + esp_println::println!("RWDT Interrupt"); + let mut rwdt = RWDT.borrow_ref_mut(cs); let rwdt = rwdt.as_mut().unwrap(); rwdt.clear_interrupt(); diff --git a/esp32s3-hal/examples/watchdog.rs b/esp32s3-hal/examples/watchdog.rs index 5a6b0f83a..1ec57348e 100644 --- a/esp32s3-hal/examples/watchdog.rs +++ b/esp32s3-hal/examples/watchdog.rs @@ -5,13 +5,7 @@ #![no_std] #![no_main] -use esp32s3_hal::{ - clock::ClockControl, - peripherals::Peripherals, - prelude::*, - timer::TimerGroup, - Rtc, -}; +use esp32s3_hal::{clock::ClockControl, peripherals::Peripherals, prelude::*, timer::TimerGroup}; use esp_backtrace as _; use esp_println::println; use nb::block; @@ -29,11 +23,8 @@ fn main() -> ! { ); let mut timer0 = timer_group0.timer0; let mut wdt = timer_group0.wdt; - let mut rtc = Rtc::new(peripherals.RTC_CNTL); wdt.start(2u64.secs()); - rtc.rwdt.disable(); - timer0.start(1u64.secs()); loop { diff --git a/esp32s3-hal/src/lib.rs b/esp32s3-hal/src/lib.rs index 7a3c65b53..ac12a8e49 100644 --- a/esp32s3-hal/src/lib.rs +++ b/esp32s3-hal/src/lib.rs @@ -275,3 +275,18 @@ pub extern "Rust" fn __init_data() -> bool { res } + +#[export_name = "__post_init"] +unsafe fn post_init() { + use esp_hal_common::{ + peripherals::{RTC_CNTL, TIMG0, TIMG1}, + timer::Wdt, + }; + + // RTC domain must be enabled before we try to disable + let mut rtc = Rtc::new(RTC_CNTL::steal()); + rtc.rwdt.disable(); + + Wdt::::set_wdt_enabled(false); + Wdt::::set_wdt_enabled(false); +}