mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-29 21:30:39 +00:00
Merge/remove some GPIO-related macros (#2404)
* Remove redundant macros * Deduplicate rtcio dispatch macros * Clean up unnecessary import * Remove manual bank assignment
This commit is contained in:
Dániel Buga
GitHub
parent
f3c5286028
commit
4e257f74aa
@ -259,27 +259,5 @@ macro_rules! lp_gpio {
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}
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}
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)+
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio {
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($this:expr, $inner:ident, $code:tt) => {
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paste::paste! {
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match $this {
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$(
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AnyPinInner::[<Gpio $gpionum >]($inner) => {
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$code
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},
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)+
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_ => panic!("Unsupported")
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}
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}
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}
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}
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pub(crate) use handle_rtcio;
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pub(crate) use handle_rtcio as handle_rtcio_with_resistors;
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}
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}
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pub(crate) use lp_gpio;
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@ -61,14 +61,7 @@
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use portable_atomic::{AtomicPtr, Ordering};
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use procmacros::ram;
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#[cfg(any(adc, dac))]
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pub(crate) use crate::analog;
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pub(crate) use crate::gpio;
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#[cfg(any(xtensa, esp32c3, esp32c2))]
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pub(crate) use crate::rtc_pins;
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pub use crate::soc::gpio::*;
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#[cfg(touch)]
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pub(crate) use crate::touch;
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use crate::{
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interrupt::InterruptHandler,
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peripheral::{Peripheral, PeripheralRef},
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@ -528,6 +521,17 @@ pub enum GpioRegisterAccess {
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Bank1,
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}
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impl From<usize> for GpioRegisterAccess {
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fn from(_gpio_num: usize) -> Self {
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#[cfg(any(esp32, esp32s2, esp32s3))]
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if _gpio_num >= 32 {
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return GpioRegisterAccess::Bank1;
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}
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GpioRegisterAccess::Bank0
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}
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}
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impl GpioRegisterAccess {
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fn write_out_en(self, word: u32, enable: bool) {
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if enable {
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@ -880,6 +884,22 @@ macro_rules! if_output_pin {
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};
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! if_rtcio_pin {
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// Base case: not an RtcIo pin, substitute the else branch
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({ $($then:tt)* } else { $($else:tt)* }) => { $($else)* };
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// First is an RtcIo pin, skip checking and substitute the then branch
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(RtcIo $(, $other:ident)* { $($then:tt)* } else { $($else:tt)* }) => { $($then)* };
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(RtcIoInput $(, $other:ident)* { $($then:tt)* } else { $($else:tt)* }) => { $($then)* };
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// First is not an RtcIo pin, check the rest
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($not:ident $(, $other:ident)* { $($then:tt)* } else { $($else:tt)* }) => {
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$crate::if_rtcio_pin!($($other),* { $($then)* } else { $($else)* })
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};
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! io_type {
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@ -889,6 +909,27 @@ macro_rules! io_type {
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(Output, $gpionum:literal) => {
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impl $crate::gpio::OutputPin for GpioPin<$gpionum> {}
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};
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(Analog, $gpionum:literal) => {
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// FIXME: the implementation shouldn't be in the GPIO module
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2))]
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impl $crate::gpio::AnalogPin for GpioPin<$gpionum> {
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/// Configures the pin for analog mode.
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fn set_analog(&self, _: $crate::private::Internal) {
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use $crate::peripherals::GPIO;
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get_io_mux_reg($gpionum).modify(|_, w| unsafe {
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w.mcu_sel().bits(1);
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w.fun_ie().clear_bit();
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w.fun_wpu().clear_bit();
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w.fun_wpd().clear_bit()
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});
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unsafe { GPIO::steal() }
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.enable_w1tc()
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.write(|w| unsafe { w.bits(1 << $gpionum) });
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}
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}
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};
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($other:ident, $gpionum:literal) => {
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// TODO
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};
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@ -899,7 +940,7 @@ macro_rules! io_type {
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macro_rules! gpio {
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(
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$(
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($gpionum:literal, $bank:literal, [$($type:tt),*]
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($gpionum:literal, [$($type:tt),*]
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$(
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( $( $af_input_num:literal => $af_input_signal:ident )* )
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( $( $af_output_num:literal => $af_output_signal:ident )* )
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@ -946,7 +987,7 @@ macro_rules! gpio {
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}
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fn gpio_bank(&self, _: $crate::private::Internal) -> $crate::gpio::GpioRegisterAccess {
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$crate::gpio::GpioRegisterAccess::[<Bank $bank >]
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$crate::gpio::GpioRegisterAccess::from($gpionum)
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}
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fn output_signals(&self, _: $crate::private::Internal) -> &[(AlternateFunction, OutputSignal)] {
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@ -1031,6 +1072,52 @@ macro_rules! gpio {
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pub(crate) use handle_gpio_output;
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pub(crate) use handle_gpio_input;
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cfg_if::cfg_if! {
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if #[cfg(any(lp_io, rtc_cntl))] {
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio {
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($this:expr, $inner:ident, $code:tt) => {
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match $this {
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$(
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AnyPinInner::[<Gpio $gpionum >]($inner) => $crate::if_rtcio_pin!($($type),* {
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$code
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} else {{
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let _ = $inner;
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panic!("Unsupported")
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}}),
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)+
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}
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}
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio_with_resistors {
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($this:expr, $inner:ident, $code:tt) => {
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match $this {
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$(
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AnyPinInner::[<Gpio $gpionum >]($inner) => $crate::if_rtcio_pin!($($type),* {
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$crate::if_output_pin!($($type),* {
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$code
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} else {{
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let _ = $inner;
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panic!("Unsupported")
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}})
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} else {{
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let _ = $inner;
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panic!("Unsupported")
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}}),
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)+
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}
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}
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}
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pub(crate) use handle_rtcio;
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pub(crate) use handle_rtcio_with_resistors;
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}
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}
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}
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};
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}
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@ -1038,7 +1125,7 @@ macro_rules! gpio {
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#[cfg(xtensa)]
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#[doc(hidden)]
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#[macro_export]
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macro_rules! rtc_pins {
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macro_rules! rtcio_analog {
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( @ignore $rue:literal ) => {};
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(
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@ -1086,7 +1173,7 @@ macro_rules! rtc_pins {
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$(
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// FIXME: replace with $(ignore($rue)) once stable
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$crate::rtc_pins!(@ignore $rue);
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$crate::rtcio_analog!(@ignore $rue);
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impl $crate::gpio::RtcPinWithResistors for GpioPin<$pin_num>
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{
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fn rtcio_pullup(&mut self, enable: bool) {
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@ -1106,13 +1193,57 @@ macro_rules! rtc_pins {
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}
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}
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)?
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#[cfg(any(adc, dac))]
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impl $crate::gpio::AnalogPin for GpioPin<$pin_num> {
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/// Configures the pin for analog mode.
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fn set_analog(&self, _: $crate::private::Internal) {
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let rtcio = unsafe{ &*$crate::peripherals::RTC_IO::ptr() };
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#[cfg(esp32s2)]
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$crate::gpio::enable_iomux_clk_gate();
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// We need `paste` (and a [< >] in it) to rewrite the token stream to
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// handle indexed pins.
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paste::paste! {
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// disable input
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rtcio.$pin_reg.modify(|_,w| w.[<$prefix fun_ie>]().bit(false));
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// disable output
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rtcio.enable_w1tc().write(|w| unsafe { w.enable_w1tc().bits(1 << $rtc_pin) });
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// disable open drain
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rtcio.pin($rtc_pin).modify(|_,w| w.pad_driver().bit(false));
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rtcio.$pin_reg.modify(|_,w| {
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w.[<$prefix fun_ie>]().clear_bit();
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// Connect pin to analog / RTC module instead of standard GPIO
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w.[<$prefix mux_sel>]().set_bit();
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// Select function "RTC function 1" (GPIO) for analog use
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unsafe { w.[<$prefix fun_sel>]().bits(0b00) };
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// Disable pull-up and pull-down resistors on the pin, if it has them
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$(
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// FIXME: replace with $(ignore($rue)) once stable
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$crate::rtcio_analog!( @ignore $rue );
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w.[<$prefix rue>]().bit(false);
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w.[<$prefix rde>]().bit(false);
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)?
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w
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});
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}
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}
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}
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};
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(
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$( ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:literal )? ) )+
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) => {
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$(
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$crate::gpio::rtc_pins!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue )?);
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$crate::rtcio_analog!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue )?);
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)+
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#[cfg(esp32)]
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@ -1131,45 +1262,6 @@ macro_rules! rtc_pins {
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pin.rtcio_pulldown(pull_down);
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}
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio {
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($this:expr, $inner:ident, $code:tt) => {
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match $this {
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$(
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paste::paste! { AnyPinInner::[<Gpio $pin_num >]($inner) } => {
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$code
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},
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)+
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_ => panic!("Unsupported")
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}
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}
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio_with_resistors {
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(@ignore $a:tt) => {};
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($this:expr, $inner:ident, $code:tt) => {
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match $this {
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$(
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$(
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paste::paste! { AnyPinInner::[<Gpio $pin_num >]($inner) } => {
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// FIXME: replace with $(ignore($rue)) once stable
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handle_rtcio_with_resistors!(@ignore $rue);
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$code
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},
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)?
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)+
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_ => panic!("Unsupported")
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}
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}
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}
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pub(crate) use handle_rtcio;
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pub(crate) use handle_rtcio_with_resistors;
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};
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}
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@ -1177,66 +1269,45 @@ macro_rules! rtc_pins {
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#[doc(hidden)]
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#[macro_export]
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macro_rules! rtc_pins {
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( $pin_num:expr ) => {
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impl $crate::gpio::RtcPin for GpioPin<$pin_num> {
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unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
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let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
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cfg_if::cfg_if! {
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if #[cfg(esp32c2)] {
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let gpio_wakeup = rtc_cntl.cntl_gpio_wakeup();
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} else {
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let gpio_wakeup = rtc_cntl.gpio_wakeup();
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( $( $pin_num:expr )+ ) => {
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$(
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impl $crate::gpio::RtcPin for GpioPin<$pin_num> {
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unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
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let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
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cfg_if::cfg_if! {
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if #[cfg(esp32c2)] {
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let gpio_wakeup = rtc_cntl.cntl_gpio_wakeup();
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} else {
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let gpio_wakeup = rtc_cntl.gpio_wakeup();
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}
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}
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paste::paste! {
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gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _wakeup_enable >]().bit(wakeup));
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gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _int_type >]().bits(level));
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}
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}
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paste::paste! {
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gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _wakeup_enable >]().bit(wakeup));
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gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _int_type >]().bits(level));
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fn rtcio_pad_hold(&mut self, enable: bool) {
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let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
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paste::paste! {
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rtc_cntl.pad_hold().modify(|_, w| w.[< gpio_pin $pin_num _hold >]().bit(enable));
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}
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}
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}
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fn rtcio_pad_hold(&mut self, enable: bool) {
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let rtc_cntl = unsafe { &*$crate::peripherals::RTC_CNTL::ptr() };
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paste::paste! {
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rtc_cntl.pad_hold().modify(|_, w| w.[< gpio_pin $pin_num _hold >]().bit(enable));
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impl $crate::gpio::RtcPinWithResistors for GpioPin<$pin_num> {
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fn rtcio_pullup(&mut self, enable: bool) {
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let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
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io_mux.gpio($pin_num).modify(|_, w| w.fun_wpu().bit(enable));
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}
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fn rtcio_pulldown(&mut self, enable: bool) {
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let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
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io_mux.gpio($pin_num).modify(|_, w| w.fun_wpd().bit(enable));
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}
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}
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}
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impl $crate::gpio::RtcPinWithResistors for GpioPin<$pin_num> {
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fn rtcio_pullup(&mut self, enable: bool) {
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let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
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io_mux.gpio($pin_num).modify(|_, w| w.fun_wpu().bit(enable));
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}
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fn rtcio_pulldown(&mut self, enable: bool) {
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let io_mux = unsafe { &*$crate::peripherals::IO_MUX::ptr() };
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io_mux.gpio($pin_num).modify(|_, w| w.fun_wpd().bit(enable));
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}
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}
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};
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( $( $pin_num:expr )+ ) => {
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$( $crate::gpio::rtc_pins!($pin_num); )+
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#[doc(hidden)]
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#[macro_export]
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macro_rules! handle_rtcio {
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($this:expr, $inner:ident, $code:tt) => {
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match $this {
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$(
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paste::paste! { AnyPinInner::[<Gpio $pin_num >]($inner) } => {
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$code
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},
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)+
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_ => panic!("Unsupported")
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}
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}
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}
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pub(crate) use handle_rtcio;
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pub(crate) use handle_rtcio as handle_rtcio_with_resistors;
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)+
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};
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}
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@ -1257,94 +1328,6 @@ pub fn enable_iomux_clk_gate() {
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}
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}
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#[cfg(any(esp32, esp32s2, esp32s3))]
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#[doc(hidden)]
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#[macro_export]
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macro_rules! analog {
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(@ignore $rue:literal) => {};
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(
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$(
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(
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$pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat $(, $rue:literal)?
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)
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)+
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) => {
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$(
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#[cfg(any(adc, dac))]
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impl $crate::gpio::AnalogPin for GpioPin<$pin_num> {
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/// Configures the pin for analog mode.
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fn set_analog(&self, _: $crate::private::Internal) {
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let rtcio = unsafe{ &*$crate::peripherals::RTC_IO::ptr() };
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#[cfg(esp32s2)]
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$crate::gpio::enable_iomux_clk_gate();
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// We need `paste` (and a [< >] in it) to rewrite the token stream to
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// handle indexed pins.
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paste::paste! {
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// disable input
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rtcio.$pin_reg.modify(|_,w| w.[<$prefix fun_ie>]().bit(false));
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// disable output
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rtcio.enable_w1tc().write(|w| unsafe { w.enable_w1tc().bits(1 << $rtc_pin) });
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// disable open drain
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rtcio.pin($rtc_pin).modify(|_,w| w.pad_driver().bit(false));
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rtcio.$pin_reg.modify(|_,w| {
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w.[<$prefix fun_ie>]().clear_bit();
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// Connect pin to analog / RTC module instead of standard GPIO
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w.[<$prefix mux_sel>]().set_bit();
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// Select function "RTC function 1" (GPIO) for analog use
|
||||
unsafe { w.[<$prefix fun_sel>]().bits(0b00) };
|
||||
|
||||
// Disable pull-up and pull-down resistors on the pin, if it has them
|
||||
$(
|
||||
// FIXME: replace with $(ignore($rue)) once stable
|
||||
$crate::analog!( @ignore $rue );
|
||||
w.[<$prefix rue>]().bit(false);
|
||||
w.[<$prefix rde>]().bit(false);
|
||||
)?
|
||||
|
||||
w
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2))]
|
||||
#[doc(hidden)]
|
||||
#[macro_export]
|
||||
macro_rules! analog {
|
||||
(
|
||||
$($pin_num:literal)+
|
||||
) => {
|
||||
$(
|
||||
#[cfg(any(adc, dac))]
|
||||
impl $crate::gpio::AnalogPin for GpioPin<$pin_num> {
|
||||
/// Configures the pin for analog mode.
|
||||
fn set_analog(&self, _: $crate::private::Internal) {
|
||||
use $crate::peripherals::GPIO;
|
||||
|
||||
get_io_mux_reg($pin_num).modify(|_,w| unsafe {
|
||||
w.mcu_sel().bits(1);
|
||||
w.fun_ie().clear_bit();
|
||||
w.fun_wpu().clear_bit();
|
||||
w.fun_wpd().clear_bit()
|
||||
});
|
||||
|
||||
unsafe{ GPIO::steal() }.enable_w1tc().write(|w| unsafe { w.bits(1 << $pin_num) });
|
||||
}
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
/// Common functionality for all touch pads
|
||||
#[doc(hidden)]
|
||||
#[macro_export]
|
||||
|
||||
@ -527,67 +527,46 @@ pub enum OutputSignal {
|
||||
MTDO,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo, Touch] (5 => EMAC_TX_CLK) (1 => CLK_OUT1))
|
||||
(1, 0, [Input, Output] (5 => EMAC_RXD2) (0 => U0TXD 1 => CLK_OUT3))
|
||||
(2, 0, [Input, Output, Analog, RtcIo, Touch] (1 => HSPIWP 3 => HS2_DATA0 4 => SD_DATA0) (3 => HS2_DATA0 4 => SD_DATA0))
|
||||
(3, 0, [Input, Output] (0 => U0RXD) (1 => CLK_OUT2))
|
||||
(4, 0, [Input, Output, Analog, RtcIo, Touch] (1 => HSPIHD 3 => HS2_DATA1 4 => SD_DATA1 5 => EMAC_TX_ER) (3 => HS2_DATA1 4 => SD_DATA1))
|
||||
(5, 0, [Input, Output] (1 => VSPICS0 3 => HS1_DATA6 5 => EMAC_RX_CLK) (3 => HS1_DATA6))
|
||||
(6, 0, [Input, Output] (4 => U1CTS) (0 => SD_CLK 1 => SPICLK 3 => HS1_CLK))
|
||||
(7, 0, [Input, Output] (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0) (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0 4 => U2RTS))
|
||||
(8, 0, [Input, Output] (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1 4 => U2CTS) (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1))
|
||||
(9, 0, [Input, Output] (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2 4 => U1RXD) (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2))
|
||||
(10, 0, [Input, Output] ( 0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3) (0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3 4 => U1TXD))
|
||||
(11, 0, [Input, Output] ( 1 => SPICS0) (0 => SD_CMD 1 => SPICS0 3 => HS1_CMD 4 => U1RTS))
|
||||
(12, 0, [Input, Output, Analog, RtcIo, Touch] (0 => MTDI 1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2) (1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2 5 => EMAC_TXD3))
|
||||
(13, 0, [Input, Output, Analog, RtcIo, Touch] (0 => MTCK 1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3) (1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3 5 => EMAC_RX_ER))
|
||||
(14, 0, [Input, Output, Analog, RtcIo, Touch] (0 => MTMS 1 => HSPICLK) (1 => HSPICLK 3 => HS2_CLK 4 => SD_CLK 5 => EMAC_TXD2))
|
||||
(15, 0, [Input, Output, Analog, RtcIo, Touch] (1 => HSPICS0 5 => EMAC_RXD3) (0 => MTDO 1 => HSPICS0 3 => HS2_CMD 4 => SD_CMD))
|
||||
(16, 0, [Input, Output] (3 => HS1_DATA4 4 => U2RXD) (3 => HS1_DATA4 5 => EMAC_CLK_OUT))
|
||||
(17, 0, [Input, Output] (3 => HS1_DATA5) (3 => HS1_DATA5 4 => U2TXD 5 => EMAC_CLK_180))
|
||||
(18, 0, [Input, Output] (1 => VSPICLK 3 => HS1_DATA7) (1 => VSPICLK 3 => HS1_DATA7))
|
||||
(19, 0, [Input, Output] (1 => VSPIQ 3 => U0CTS) (1 => VSPIQ 5 => EMAC_TXD0))
|
||||
(20, 0, [Input, Output])
|
||||
(21, 0, [Input, Output] (1 => VSPIHD) (1 => VSPIHD 5 => EMAC_TX_EN))
|
||||
(22, 0, [Input, Output] (1 => VSPIWP) (1 => VSPIWP 3 => U0RTS 5 => EMAC_TXD1))
|
||||
(23, 0, [Input, Output] (1 => VSPID) (1 => VSPID 3 => HS1_STROBE))
|
||||
(24, 0, [Input, Output])
|
||||
(25, 0, [Input, Output, Analog, RtcIo] (5 => EMAC_RXD0) ())
|
||||
(26, 0, [Input, Output, Analog, RtcIo] (5 => EMAC_RXD1) ())
|
||||
(27, 0, [Input, Output, Analog, RtcIo, Touch] (5 => EMAC_RX_DV) ())
|
||||
(32, 1, [Input, Output, Analog, RtcIo, Touch])
|
||||
(33, 1, [Input, Output, Analog, RtcIo, Touch])
|
||||
(34, 1, [Input, Analog, RtcIoInput])
|
||||
(35, 1, [Input, Analog, RtcIoInput])
|
||||
(36, 1, [Input, Analog, RtcIoInput])
|
||||
(37, 1, [Input, Analog, RtcIoInput])
|
||||
(38, 1, [Input, Analog, RtcIoInput])
|
||||
(39, 1, [Input, Analog, RtcIoInput])
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo, Touch] (5 => EMAC_TX_CLK) (1 => CLK_OUT1))
|
||||
(1, [Input, Output] (5 => EMAC_RXD2) (0 => U0TXD 1 => CLK_OUT3))
|
||||
(2, [Input, Output, Analog, RtcIo, Touch] (1 => HSPIWP 3 => HS2_DATA0 4 => SD_DATA0) (3 => HS2_DATA0 4 => SD_DATA0))
|
||||
(3, [Input, Output] (0 => U0RXD) (1 => CLK_OUT2))
|
||||
(4, [Input, Output, Analog, RtcIo, Touch] (1 => HSPIHD 3 => HS2_DATA1 4 => SD_DATA1 5 => EMAC_TX_ER) (3 => HS2_DATA1 4 => SD_DATA1))
|
||||
(5, [Input, Output] (1 => VSPICS0 3 => HS1_DATA6 5 => EMAC_RX_CLK) (3 => HS1_DATA6))
|
||||
(6, [Input, Output] (4 => U1CTS) (0 => SD_CLK 1 => SPICLK 3 => HS1_CLK))
|
||||
(7, [Input, Output] (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0) (0 => SD_DATA0 1 => SPIQ 3 => HS1_DATA0 4 => U2RTS))
|
||||
(8, [Input, Output] (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1 4 => U2CTS) (0 => SD_DATA1 1 => SPID 3 => HS1_DATA1))
|
||||
(9, [Input, Output] (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2 4 => U1RXD) (0 => SD_DATA2 1 => SPIHD 3 => HS1_DATA2))
|
||||
(10, [Input, Output] ( 0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3) (0 => SD_DATA3 1 => SPIWP 3 => HS1_DATA3 4 => U1TXD))
|
||||
(11, [Input, Output] ( 1 => SPICS0) (0 => SD_CMD 1 => SPICS0 3 => HS1_CMD 4 => U1RTS))
|
||||
(12, [Input, Output, Analog, RtcIo, Touch] (0 => MTDI 1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2) (1 => HSPIQ 3 => HS2_DATA2 4 => SD_DATA2 5 => EMAC_TXD3))
|
||||
(13, [Input, Output, Analog, RtcIo, Touch] (0 => MTCK 1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3) (1 => HSPID 3 => HS2_DATA3 4 => SD_DATA3 5 => EMAC_RX_ER))
|
||||
(14, [Input, Output, Analog, RtcIo, Touch] (0 => MTMS 1 => HSPICLK) (1 => HSPICLK 3 => HS2_CLK 4 => SD_CLK 5 => EMAC_TXD2))
|
||||
(15, [Input, Output, Analog, RtcIo, Touch] (1 => HSPICS0 5 => EMAC_RXD3) (0 => MTDO 1 => HSPICS0 3 => HS2_CMD 4 => SD_CMD))
|
||||
(16, [Input, Output] (3 => HS1_DATA4 4 => U2RXD) (3 => HS1_DATA4 5 => EMAC_CLK_OUT))
|
||||
(17, [Input, Output] (3 => HS1_DATA5) (3 => HS1_DATA5 4 => U2TXD 5 => EMAC_CLK_180))
|
||||
(18, [Input, Output] (1 => VSPICLK 3 => HS1_DATA7) (1 => VSPICLK 3 => HS1_DATA7))
|
||||
(19, [Input, Output] (1 => VSPIQ 3 => U0CTS) (1 => VSPIQ 5 => EMAC_TXD0))
|
||||
(20, [Input, Output])
|
||||
(21, [Input, Output] (1 => VSPIHD) (1 => VSPIHD 5 => EMAC_TX_EN))
|
||||
(22, [Input, Output] (1 => VSPIWP) (1 => VSPIWP 3 => U0RTS 5 => EMAC_TXD1))
|
||||
(23, [Input, Output] (1 => VSPID) (1 => VSPID 3 => HS1_STROBE))
|
||||
(24, [Input, Output])
|
||||
(25, [Input, Output, Analog, RtcIo] (5 => EMAC_RXD0) ())
|
||||
(26, [Input, Output, Analog, RtcIo] (5 => EMAC_RXD1) ())
|
||||
(27, [Input, Output, Analog, RtcIo, Touch] (5 => EMAC_RX_DV) ())
|
||||
(32, [Input, Output, Analog, RtcIo, Touch])
|
||||
(33, [Input, Output, Analog, RtcIo, Touch])
|
||||
(34, [Input, Analog, RtcIoInput])
|
||||
(35, [Input, Analog, RtcIoInput])
|
||||
(36, [Input, Analog, RtcIoInput])
|
||||
(37, [Input, Analog, RtcIoInput])
|
||||
(38, [Input, Analog, RtcIoInput])
|
||||
(39, [Input, Analog, RtcIoInput])
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
(36, 0, sensor_pads(), "sense1_" )
|
||||
(37, 1, sensor_pads(), "sense2_" )
|
||||
(38, 2, sensor_pads(), "sense3_" )
|
||||
(39, 3, sensor_pads(), "sense4_" )
|
||||
(34, 4, adc_pad(), "adc1_" )
|
||||
(35, 5, adc_pad(), "adc2_" )
|
||||
(25, 6, pad_dac1(), "", true)
|
||||
(26, 7, pad_dac2(), "", true)
|
||||
(33, 8, xtal_32k_pad(), "x32p_", true)
|
||||
(32, 9, xtal_32k_pad(), "x32n_", true)
|
||||
(4, 10, touch_pad0(), "", true)
|
||||
(0, 11, touch_pad1(), "", true)
|
||||
(2, 12, touch_pad2(), "", true)
|
||||
(15, 13, touch_pad3(), "", true)
|
||||
(13, 14, touch_pad4(), "", true)
|
||||
(12, 15, touch_pad5(), "", true)
|
||||
(14, 16, touch_pad6(), "", true)
|
||||
(27, 17, touch_pad7(), "", true)
|
||||
}
|
||||
|
||||
crate::gpio::rtc_pins! {
|
||||
crate::rtcio_analog! {
|
||||
(36, 0, sensor_pads(), sense1_, sense1_hold_force )
|
||||
(37, 1, sensor_pads(), sense2_, sense2_hold_force )
|
||||
(38, 2, sensor_pads(), sense3_, sense3_hold_force )
|
||||
@ -608,7 +587,7 @@ crate::gpio::rtc_pins! {
|
||||
(27, 17, touch_pad7(), "", touch_pad7_hold_force, true)
|
||||
}
|
||||
|
||||
crate::gpio::touch! {
|
||||
crate::touch! {
|
||||
// touch_nr, pin_nr, rtc_pin, touch_out_reg, meas_field, touch_thres_reg, touch_thres_field, normal_pin
|
||||
(0, 4, 10, sar_touch_out1, touch_meas_out0, sar_touch_thres1, touch_out_th0, true)
|
||||
(1, 0, 11, sar_touch_out1, touch_meas_out1, sar_touch_thres1, touch_out_th1, true)
|
||||
|
||||
@ -171,24 +171,24 @@ pub enum OutputSignal {
|
||||
GPIO = 128,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo])
|
||||
(1, 0, [Input, Output, Analog, RtcIo])
|
||||
(2, 0, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, 0, [Input, Output, Analog, RtcIo])
|
||||
(4, 0, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (2 => FSPIHD))
|
||||
(5, 0, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (2 => FSPIWP))
|
||||
(6, 0, [Input, Output] (2 => FSPICLK) (2 => FSPICLK_MUX))
|
||||
(7, 0, [Input, Output] (2 => FSPID) (2 => FSPID))
|
||||
(8, 0, [Input, Output])
|
||||
(9, 0, [Input, Output])
|
||||
(10, 0, [Input, Output] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(18, 0, [Input, Output])
|
||||
(19, 0, [Input, Output])
|
||||
(20, 0, [Input, Output] (0 => U0RXD) ())
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo])
|
||||
(1, [Input, Output, Analog, RtcIo])
|
||||
(2, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, [Input, Output, Analog, RtcIo])
|
||||
(4, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (2 => FSPIHD))
|
||||
(5, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (2 => FSPIWP))
|
||||
(6, [Input, Output] (2 => FSPICLK) (2 => FSPICLK_MUX))
|
||||
(7, [Input, Output] (2 => FSPID) (2 => FSPID))
|
||||
(8, [Input, Output])
|
||||
(9, [Input, Output])
|
||||
(10, [Input, Output] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(18, [Input, Output])
|
||||
(19, [Input, Output])
|
||||
(20, [Input, Output] (0 => U0RXD) ())
|
||||
}
|
||||
|
||||
crate::gpio::rtc_pins! {
|
||||
crate::rtc_pins! {
|
||||
0
|
||||
1
|
||||
2
|
||||
@ -197,14 +197,6 @@ crate::gpio::rtc_pins! {
|
||||
5
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
0
|
||||
1
|
||||
2
|
||||
3
|
||||
4
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
pub(crate) enum InterruptStatusRegisterAccess {
|
||||
Bank0,
|
||||
|
||||
@ -198,42 +198,33 @@ pub enum OutputSignal {
|
||||
GPIO = 128,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo])
|
||||
(1, 0, [Input, Output, Analog, RtcIo])
|
||||
(2, 0, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, 0, [Input, Output, Analog, RtcIo])
|
||||
(4, 0, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD))
|
||||
(5, 0, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP))
|
||||
(6, 0, [Input, Output] (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX))
|
||||
(7, 0, [Input, Output] (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID))
|
||||
(8, 0, [Input, Output])
|
||||
(9, 0, [Input, Output])
|
||||
(10, 0, [Input, Output] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(11, 0, [Input, Output])
|
||||
(12, 0, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(13, 0, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(14, 0, [Input, Output] () (0 => SPICS0))
|
||||
(15, 0, [Input, Output] () (0 => SPICLK_MUX))
|
||||
(16, 0, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
(17, 0, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(18, 0, [Input, Output])
|
||||
(19, 0, [Input, Output])
|
||||
(20, 0, [Input, Output] (0 => U0RXD) ())
|
||||
(21, 0, [Input, Output] () (0 => U0TXD))
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo])
|
||||
(1, [Input, Output, Analog, RtcIo])
|
||||
(2, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, [Input, Output, Analog, RtcIo])
|
||||
(4, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD))
|
||||
(5, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP))
|
||||
(6, [Input, Output] (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX))
|
||||
(7, [Input, Output] (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID))
|
||||
(8, [Input, Output])
|
||||
(9, [Input, Output])
|
||||
(10, [Input, Output] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(11, [Input, Output])
|
||||
(12, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(13, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(14, [Input, Output] () (0 => SPICS0))
|
||||
(15, [Input, Output] () (0 => SPICLK_MUX))
|
||||
(16, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
(17, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(18, [Input, Output])
|
||||
(19, [Input, Output])
|
||||
(20, [Input, Output] (0 => U0RXD) ())
|
||||
(21, [Input, Output] () (0 => U0TXD))
|
||||
}
|
||||
|
||||
// RTC pins 0 through 5 (inclusive) support GPIO wakeup
|
||||
crate::gpio::rtc_pins! {
|
||||
0
|
||||
1
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
crate::rtc_pins! {
|
||||
0
|
||||
1
|
||||
2
|
||||
|
||||
@ -284,52 +284,41 @@ pub enum OutputSignal {
|
||||
GPIO = 128,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo])
|
||||
(1, 0, [Input, Output, Analog, RtcIo])
|
||||
(2, 0, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, 0, [Input, Output, Analog, RtcIo])
|
||||
(4, 0, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD))
|
||||
(5, 0, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP))
|
||||
(6, 0, [Input, Output, Analog, RtcIo] (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX))
|
||||
(7, 0, [Input, Output, Analog, RtcIo] (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID))
|
||||
(8, 0, [Input, Output])
|
||||
(9, 0, [Input, Output])
|
||||
(10, 0, [Input, Output])
|
||||
(11, 0, [Input, Output])
|
||||
(12, 0, [Input, Output])
|
||||
(13, 0, [Input, Output])
|
||||
(14, 0, [Input, Output])
|
||||
(15, 0, [Input, Output])
|
||||
(16, 0, [Input, Output] (0 => U0RXD) (2 => FSPICS0))
|
||||
(17, 0, [Input, Output] () (0 => U0TXD 2 => FSPICS1))
|
||||
(18, 0, [Input, Output] () (2 => FSPICS2)) // 0 => SDIO_CMD but there are no signals since it's a fixed pin
|
||||
(19, 0, [Input, Output] () (2 => FSPICS3)) // 0 => SDIO_CLK but there are no signals since it's a fixed pin
|
||||
(20, 0, [Input, Output] () (2 => FSPICS4)) // 0 => SDIO_DATA0 but there are no signals since it's a fixed pin
|
||||
(21, 0, [Input, Output] () (2 => FSPICS5)) // 0 => SDIO_DATA1 but there are no signals since it's a fixed pin
|
||||
(22, 0, [Input, Output] () ()) // 0 => SDIO_DATA2 but there are no signals since it's a fixed pin
|
||||
(23, 0, [Input, Output] () ()) // 0 => SDIO_DATA3 but there are no signals since it's a fixed pin
|
||||
(24, 0, [Input, Output] () (0 => SPICS0))
|
||||
(25, 0, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(26, 0, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(27, 0, [Input, Output])
|
||||
(28, 0, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(29, 0, [Input, Output] () (0 => SPICLK_MUX))
|
||||
(30, 0, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo])
|
||||
(1, [Input, Output, Analog, RtcIo])
|
||||
(2, [Input, Output, Analog, RtcIo] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(3, [Input, Output, Analog, RtcIo])
|
||||
(4, [Input, Output, Analog, RtcIo] (2 => FSPIHD) (0 => USB_JTAG_TMS 2 => FSPIHD))
|
||||
(5, [Input, Output, Analog, RtcIo] (2 => FSPIWP) (0 => USB_JTAG_TDI 2 => FSPIWP))
|
||||
(6, [Input, Output, Analog, RtcIo] (2 => FSPICLK) (0 => USB_JTAG_TCK 2 => FSPICLK_MUX))
|
||||
(7, [Input, Output, Analog, RtcIo] (2 => FSPID) (0 => USB_JTAG_TDO 2 => FSPID))
|
||||
(8, [Input, Output])
|
||||
(9, [Input, Output])
|
||||
(10, [Input, Output])
|
||||
(11, [Input, Output])
|
||||
(12, [Input, Output])
|
||||
(13, [Input, Output])
|
||||
(14, [Input, Output])
|
||||
(15, [Input, Output])
|
||||
(16, [Input, Output] (0 => U0RXD) (2 => FSPICS0))
|
||||
(17, [Input, Output] () (0 => U0TXD 2 => FSPICS1))
|
||||
(18, [Input, Output] () (2 => FSPICS2)) // 0 => SDIO_CMD but there are no signals since it's a fixed pin
|
||||
(19, [Input, Output] () (2 => FSPICS3)) // 0 => SDIO_CLK but there are no signals since it's a fixed pin
|
||||
(20, [Input, Output] () (2 => FSPICS4)) // 0 => SDIO_DATA0 but there are no signals since it's a fixed pin
|
||||
(21, [Input, Output] () (2 => FSPICS5)) // 0 => SDIO_DATA1 but there are no signals since it's a fixed pin
|
||||
(22, [Input, Output] () ()) // 0 => SDIO_DATA2 but there are no signals since it's a fixed pin
|
||||
(23, [Input, Output] () ()) // 0 => SDIO_DATA3 but there are no signals since it's a fixed pin
|
||||
(24, [Input, Output] () (0 => SPICS0))
|
||||
(25, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(26, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(27, [Input, Output])
|
||||
(28, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(29, [Input, Output] () (0 => SPICLK_MUX))
|
||||
(30, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
0
|
||||
1
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
6
|
||||
7
|
||||
}
|
||||
|
||||
crate::gpio::lp_io::lp_gpio! {
|
||||
crate::lp_gpio! {
|
||||
0
|
||||
1
|
||||
2
|
||||
|
||||
@ -249,43 +249,35 @@ pub enum OutputSignal {
|
||||
GPIO = 128,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(1, 0, [Input, Output, Analog] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(2, 0, [Input, Output, Analog] (2 => FSPIWP) (2 => FSPIWP))
|
||||
(3, 0, [Input, Output, Analog] (2 => FSPIHD) (2 => FSPIHD))
|
||||
(4, 0, [Input, Output, Analog] (2 => FSPICLK) (2 => FSPICLK_MUX))
|
||||
(5, 0, [Input, Output, Analog] (2 => FSPID) (2 => FSPID))
|
||||
(6, 0, [Input, Output])
|
||||
(7, 0, [Input, Output])
|
||||
(8, 0, [Input, Output])
|
||||
(9, 0, [Input, Output])
|
||||
(10, 0, [Input, Output])
|
||||
(11, 0, [Input, Output])
|
||||
(12, 0, [Input, Output])
|
||||
(13, 0, [Input, Output])
|
||||
(14, 0, [Input, Output])
|
||||
(15, 0, [Input, Output] () (0 => SPICS0))
|
||||
(16, 0, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(17, 0, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(18, 0, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(19, 0, [Input, Output] () (0 => SPICLK))
|
||||
(20, 0, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
(21, 0, [Input, Output])
|
||||
(22, 0, [Input, Output])
|
||||
(23, 0, [Input, Output] () (2 => FSPICS1))
|
||||
(24, 0, [Input, Output] () (2 => FSPICS2))
|
||||
(25, 0, [Input, Output] () (2 => FSPICS3))
|
||||
(26, 0, [Input, Output] () (2 => FSPICS4))
|
||||
(27, 0, [Input, Output] () (2 => FSPICS5))
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
1
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog] (2 => FSPIQ) (2 => FSPIQ))
|
||||
(1, [Input, Output, Analog] (2 => FSPICS0) (2 => FSPICS0))
|
||||
(2, [Input, Output, Analog] (2 => FSPIWP) (2 => FSPIWP))
|
||||
(3, [Input, Output, Analog] (2 => FSPIHD) (2 => FSPIHD))
|
||||
(4, [Input, Output, Analog] (2 => FSPICLK) (2 => FSPICLK_MUX))
|
||||
(5, [Input, Output, Analog] (2 => FSPID) (2 => FSPID))
|
||||
(6, [Input, Output])
|
||||
(7, [Input, Output])
|
||||
(8, [Input, Output])
|
||||
(9, [Input, Output])
|
||||
(10, [Input, Output])
|
||||
(11, [Input, Output])
|
||||
(12, [Input, Output])
|
||||
(13, [Input, Output])
|
||||
(14, [Input, Output])
|
||||
(15, [Input, Output] () (0 => SPICS0))
|
||||
(16, [Input, Output] (0 => SPIQ) (0 => SPIQ))
|
||||
(17, [Input, Output] (0 => SPIWP) (0 => SPIWP))
|
||||
(18, [Input, Output] (0 => SPIHD) (0 => SPIHD))
|
||||
(19, [Input, Output] () (0 => SPICLK))
|
||||
(20, [Input, Output] (0 => SPID) (0 => SPID))
|
||||
(21, [Input, Output])
|
||||
(22, [Input, Output])
|
||||
(23, [Input, Output] () (2 => FSPICS1))
|
||||
(24, [Input, Output] () (2 => FSPICS2))
|
||||
(25, [Input, Output] () (2 => FSPICS3))
|
||||
(26, [Input, Output] () (2 => FSPICS4))
|
||||
(27, [Input, Output] () (2 => FSPICS5))
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy)]
|
||||
|
||||
@ -314,79 +314,54 @@ pub enum OutputSignal {
|
||||
GPIO = 256,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo])
|
||||
(1, 0, [Input, Output, Analog, RtcIo])
|
||||
(2, 0, [Input, Output, Analog, RtcIo])
|
||||
(3, 0, [Input, Output, Analog, RtcIo])
|
||||
(4, 0, [Input, Output, Analog, RtcIo])
|
||||
(5, 0, [Input, Output, Analog, RtcIo])
|
||||
(6, 0, [Input, Output, Analog, RtcIo])
|
||||
(7, 0, [Input, Output, Analog, RtcIo])
|
||||
(8, 0, [Input, Output, Analog, RtcIo])
|
||||
(9, 0, [Input, Output, Analog, RtcIo])
|
||||
(10, 0, [Input, Output, Analog, RtcIo])
|
||||
(11, 0, [Input, Output, Analog, RtcIo])
|
||||
(12, 0, [Input, Output, Analog, RtcIo])
|
||||
(13, 0, [Input, Output, Analog, RtcIo])
|
||||
(14, 0, [Input, Output, Analog, RtcIo])
|
||||
(15, 0, [Input, Output, Analog, RtcIo])
|
||||
(16, 0, [Input, Output, Analog, RtcIo])
|
||||
(17, 0, [Input, Output, Analog, RtcIo])
|
||||
(18, 0, [Input, Output, Analog, RtcIo])
|
||||
(19, 0, [Input, Output, Analog, RtcIo])
|
||||
(20, 0, [Input, Output, Analog, RtcIo])
|
||||
(21, 0, [Input, Output, Analog, RtcIo])
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo])
|
||||
(1, [Input, Output, Analog, RtcIo])
|
||||
(2, [Input, Output, Analog, RtcIo])
|
||||
(3, [Input, Output, Analog, RtcIo])
|
||||
(4, [Input, Output, Analog, RtcIo])
|
||||
(5, [Input, Output, Analog, RtcIo])
|
||||
(6, [Input, Output, Analog, RtcIo])
|
||||
(7, [Input, Output, Analog, RtcIo])
|
||||
(8, [Input, Output, Analog, RtcIo])
|
||||
(9, [Input, Output, Analog, RtcIo])
|
||||
(10, [Input, Output, Analog, RtcIo])
|
||||
(11, [Input, Output, Analog, RtcIo])
|
||||
(12, [Input, Output, Analog, RtcIo])
|
||||
(13, [Input, Output, Analog, RtcIo])
|
||||
(14, [Input, Output, Analog, RtcIo])
|
||||
(15, [Input, Output, Analog, RtcIo])
|
||||
(16, [Input, Output, Analog, RtcIo])
|
||||
(17, [Input, Output, Analog, RtcIo])
|
||||
(18, [Input, Output, Analog, RtcIo])
|
||||
(19, [Input, Output, Analog, RtcIo])
|
||||
(20, [Input, Output, Analog, RtcIo])
|
||||
(21, [Input, Output, Analog, RtcIo])
|
||||
|
||||
(26, 0, [Input, Output])
|
||||
(27, 0, [Input, Output])
|
||||
(28, 0, [Input, Output])
|
||||
(29, 0, [Input, Output])
|
||||
(30, 0, [Input, Output])
|
||||
(31, 0, [Input, Output])
|
||||
(32, 1, [Input, Output])
|
||||
(33, 1, [Input, Output])
|
||||
(34, 1, [Input, Output])
|
||||
(35, 1, [Input, Output])
|
||||
(36, 1, [Input, Output])
|
||||
(37, 1, [Input, Output])
|
||||
(38, 1, [Input, Output])
|
||||
(39, 1, [Input, Output])
|
||||
(40, 1, [Input, Output])
|
||||
(41, 1, [Input, Output])
|
||||
(42, 1, [Input, Output])
|
||||
(43, 1, [Input, Output])
|
||||
(44, 1, [Input, Output])
|
||||
(45, 1, [Input, Output])
|
||||
(46, 1, [Input, Output])
|
||||
(26, [Input, Output])
|
||||
(27, [Input, Output])
|
||||
(28, [Input, Output])
|
||||
(29, [Input, Output])
|
||||
(30, [Input, Output])
|
||||
(31, [Input, Output])
|
||||
(32, [Input, Output])
|
||||
(33, [Input, Output])
|
||||
(34, [Input, Output])
|
||||
(35, [Input, Output])
|
||||
(36, [Input, Output])
|
||||
(37, [Input, Output])
|
||||
(38, [Input, Output])
|
||||
(39, [Input, Output])
|
||||
(40, [Input, Output])
|
||||
(41, [Input, Output])
|
||||
(42, [Input, Output])
|
||||
(43, [Input, Output])
|
||||
(44, [Input, Output])
|
||||
(45, [Input, Output])
|
||||
(46, [Input, Output])
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
( 0, 0, touch_pad(0), "", true)
|
||||
( 1, 1, touch_pad(1), "", true)
|
||||
( 2, 2, touch_pad(2), "", true)
|
||||
( 3, 3, touch_pad(3), "", true)
|
||||
( 4, 4, touch_pad(4), "", true)
|
||||
( 5, 5, touch_pad(5), "", true)
|
||||
( 6, 6, touch_pad(6), "", true)
|
||||
( 7, 7, touch_pad(7), "", true)
|
||||
( 8, 8, touch_pad(8), "", true)
|
||||
( 9, 9, touch_pad(9), "", true)
|
||||
(10, 10, touch_pad(10), "", true)
|
||||
(11, 11, touch_pad(11), "", true)
|
||||
(12, 12, touch_pad(12), "", true)
|
||||
(13, 13, touch_pad(13), "", true)
|
||||
(14, 14, touch_pad(14), "", true)
|
||||
(15, 15, xtal_32p_pad(), "x32p_", true)
|
||||
(16, 16, xtal_32n_pad(), "x32n_", true)
|
||||
(17, 17, pad_dac1(), "", true)
|
||||
(18, 18, pad_dac2(), "", true)
|
||||
(19, 19, rtc_pad19(), "", true)
|
||||
(20, 20, rtc_pad20(), "", true)
|
||||
(21, 21, rtc_pad21(), "", true)
|
||||
}
|
||||
|
||||
crate::gpio::rtc_pins! {
|
||||
crate::rtcio_analog! {
|
||||
( 0, 0, touch_pad(0), "", touch_pad0_hold, true)
|
||||
( 1, 1, touch_pad(1), "", touch_pad1_hold, true)
|
||||
( 2, 2, touch_pad(2), "", touch_pad2_hold, true)
|
||||
|
||||
@ -345,80 +345,55 @@ pub enum OutputSignal {
|
||||
GPIO = 256,
|
||||
}
|
||||
|
||||
crate::gpio::gpio! {
|
||||
(0, 0, [Input, Output, Analog, RtcIo])
|
||||
(1, 0, [Input, Output, Analog, RtcIo])
|
||||
(2, 0, [Input, Output, Analog, RtcIo])
|
||||
(3, 0, [Input, Output, Analog, RtcIo])
|
||||
(4, 0, [Input, Output, Analog, RtcIo])
|
||||
(5, 0, [Input, Output, Analog, RtcIo])
|
||||
(6, 0, [Input, Output, Analog, RtcIo])
|
||||
(7, 0, [Input, Output, Analog, RtcIo])
|
||||
(8, 0, [Input, Output, Analog, RtcIo] () (3 => SUBSPICS1))
|
||||
(9, 0, [Input, Output, Analog, RtcIo] (3 => SUBSPIHD 4 => FSPIHD) (3 => SUBSPIHD 4 => FSPIHD))
|
||||
(10, 0, [Input, Output, Analog, RtcIo] (2 => FSPIIO4 4 => FSPICS0) (2 => FSPIIO4 3 => SUBSPICS0 4 => FSPICS0))
|
||||
(11, 0, [Input, Output, Analog, RtcIo] (2 => FSPIIO5 3 => SUBSPID 4 => FSPID) (2 => FSPIIO5 3 => SUBSPID 4 => FSPID))
|
||||
(12, 0, [Input, Output, Analog, RtcIo] (2 => FSPIIO6 4 => FSPICLK) (2 => FSPIIO6 3=> SUBSPICLK 4 => FSPICLK))
|
||||
(13, 0, [Input, Output, Analog, RtcIo] (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ) (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ))
|
||||
(14, 0, [Input, Output, Analog, RtcIo] (3 => SUBSPIWP 4 => FSPIWP) (2 => FSPIDQS 3 => SUBSPIWP 4 => FSPIWP))
|
||||
(15, 0, [Input, Output, Analog, RtcIo] () (2 => U0RTS))
|
||||
(16, 0, [Input, Output, Analog, RtcIo] (2 => U0CTS) ())
|
||||
(17, 0, [Input, Output, Analog, RtcIo] () (2 => U1TXD))
|
||||
(18, 0, [Input, Output, Analog, RtcIo] (2 => U1RXD) ())
|
||||
(19, 0, [Input, Output, Analog, RtcIo] () (2 => U1RTS))
|
||||
(20, 0, [Input, Output, Analog, RtcIo] (2 => U1CTS) ())
|
||||
(21, 0, [Input, Output, Analog, RtcIo])
|
||||
(26, 0, [Input, Output])
|
||||
(27, 0, [Input, Output])
|
||||
(28, 0, [Input, Output])
|
||||
(29, 0, [Input, Output])
|
||||
(30, 0, [Input, Output])
|
||||
(31, 0, [Input, Output])
|
||||
(32, 1, [Input, Output])
|
||||
(33, 1, [Input, Output] (2 => FSPIHD 3 => SUBSPIHD) (2 => FSPIHD 3 => SUBSPIHD))
|
||||
(34, 1, [Input, Output] (2 => FSPICS0) (2 => FSPICS0 3 => SUBSPICS0))
|
||||
(35, 1, [Input, Output] (2 => FSPID 3 => SUBSPID) (2 => FSPID 3 => SUBSPID))
|
||||
(36, 1, [Input, Output] (2 => FSPICLK) (2 => FSPICLK 3 => SUBSPICLK))
|
||||
(37, 1, [Input, Output] (2 => FSPIQ 3 => SUBSPIQ 4 => SPIDQS) (2 => FSPIQ 3=> SUBSPIQ 4 => SPIDQS))
|
||||
(38, 1, [Input, Output] (2 => FSPIWP 3 => SUBSPIWP) (3 => FSPIWP 3 => SUBSPIWP))
|
||||
(39, 1, [Input, Output] () (4 => SUBSPICS1))
|
||||
(40, 1, [Input, Output])
|
||||
(41, 1, [Input, Output])
|
||||
(42, 1, [Input, Output])
|
||||
(43, 1, [Input, Output])
|
||||
(44, 1, [Input, Output])
|
||||
(45, 1, [Input, Output])
|
||||
(46, 1, [Input, Output])
|
||||
(47, 1, [Input, Output])
|
||||
(48, 1, [Input, Output])
|
||||
crate::gpio! {
|
||||
(0, [Input, Output, Analog, RtcIo])
|
||||
(1, [Input, Output, Analog, RtcIo])
|
||||
(2, [Input, Output, Analog, RtcIo])
|
||||
(3, [Input, Output, Analog, RtcIo])
|
||||
(4, [Input, Output, Analog, RtcIo])
|
||||
(5, [Input, Output, Analog, RtcIo])
|
||||
(6, [Input, Output, Analog, RtcIo])
|
||||
(7, [Input, Output, Analog, RtcIo])
|
||||
(8, [Input, Output, Analog, RtcIo] () (3 => SUBSPICS1))
|
||||
(9, [Input, Output, Analog, RtcIo] (3 => SUBSPIHD 4 => FSPIHD) (3 => SUBSPIHD 4 => FSPIHD))
|
||||
(10, [Input, Output, Analog, RtcIo] (2 => FSPIIO4 4 => FSPICS0) (2 => FSPIIO4 3 => SUBSPICS0 4 => FSPICS0))
|
||||
(11, [Input, Output, Analog, RtcIo] (2 => FSPIIO5 3 => SUBSPID 4 => FSPID) (2 => FSPIIO5 3 => SUBSPID 4 => FSPID))
|
||||
(12, [Input, Output, Analog, RtcIo] (2 => FSPIIO6 4 => FSPICLK) (2 => FSPIIO6 3=> SUBSPICLK 4 => FSPICLK))
|
||||
(13, [Input, Output, Analog, RtcIo] (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ) (2 => FSPIIO7 3 => SUBSPIQ 4 => FSPIQ))
|
||||
(14, [Input, Output, Analog, RtcIo] (3 => SUBSPIWP 4 => FSPIWP) (2 => FSPIDQS 3 => SUBSPIWP 4 => FSPIWP))
|
||||
(15, [Input, Output, Analog, RtcIo] () (2 => U0RTS))
|
||||
(16, [Input, Output, Analog, RtcIo] (2 => U0CTS) ())
|
||||
(17, [Input, Output, Analog, RtcIo] () (2 => U1TXD))
|
||||
(18, [Input, Output, Analog, RtcIo] (2 => U1RXD) ())
|
||||
(19, [Input, Output, Analog, RtcIo] () (2 => U1RTS))
|
||||
(20, [Input, Output, Analog, RtcIo] (2 => U1CTS) ())
|
||||
(21, [Input, Output, Analog, RtcIo])
|
||||
(26, [Input, Output])
|
||||
(27, [Input, Output])
|
||||
(28, [Input, Output])
|
||||
(29, [Input, Output])
|
||||
(30, [Input, Output])
|
||||
(31, [Input, Output])
|
||||
(32, [Input, Output])
|
||||
(33, [Input, Output] (2 => FSPIHD 3 => SUBSPIHD) (2 => FSPIHD 3 => SUBSPIHD))
|
||||
(34, [Input, Output] (2 => FSPICS0) (2 => FSPICS0 3 => SUBSPICS0))
|
||||
(35, [Input, Output] (2 => FSPID 3 => SUBSPID) (2 => FSPID 3 => SUBSPID))
|
||||
(36, [Input, Output] (2 => FSPICLK) (2 => FSPICLK 3 => SUBSPICLK))
|
||||
(37, [Input, Output] (2 => FSPIQ 3 => SUBSPIQ 4 => SPIDQS) (2 => FSPIQ 3=> SUBSPIQ 4 => SPIDQS))
|
||||
(38, [Input, Output] (2 => FSPIWP 3 => SUBSPIWP) (3 => FSPIWP 3 => SUBSPIWP))
|
||||
(39, [Input, Output] () (4 => SUBSPICS1))
|
||||
(40, [Input, Output])
|
||||
(41, [Input, Output])
|
||||
(42, [Input, Output])
|
||||
(43, [Input, Output])
|
||||
(44, [Input, Output])
|
||||
(45, [Input, Output])
|
||||
(46, [Input, Output])
|
||||
(47, [Input, Output])
|
||||
(48, [Input, Output])
|
||||
}
|
||||
|
||||
crate::gpio::analog! {
|
||||
( 0, 0, touch_pad(0), "", true)
|
||||
( 1, 1, touch_pad(1), "", true)
|
||||
( 2, 2, touch_pad(2), "", true)
|
||||
( 3, 3, touch_pad(3), "", true)
|
||||
( 4, 4, touch_pad(4), "", true)
|
||||
( 5, 5, touch_pad(5), "", true)
|
||||
( 6, 6, touch_pad(6), "", true)
|
||||
( 7, 7, touch_pad(7), "", true)
|
||||
( 8, 8, touch_pad(8), "", true)
|
||||
( 9, 9, touch_pad(9), "", true)
|
||||
(10, 10, touch_pad(10), "", true)
|
||||
(11, 11, touch_pad(11), "", true)
|
||||
(12, 12, touch_pad(12), "", true)
|
||||
(13, 13, touch_pad(13), "", true)
|
||||
(14, 14, touch_pad(14), "", true)
|
||||
(15, 15, xtal_32p_pad(), "x32p_", true)
|
||||
(16, 16, xtal_32n_pad(), "x32n_", true)
|
||||
(17, 17, pad_dac1(), "pdac1_", true)
|
||||
(18, 18, pad_dac2(), "pdac2_", true)
|
||||
(19, 19, rtc_pad19(), "", true)
|
||||
(20, 20, rtc_pad20(), "", true)
|
||||
(21, 21, rtc_pad21(), "", true)
|
||||
}
|
||||
|
||||
crate::gpio::rtc_pins! {
|
||||
crate::rtcio_analog! {
|
||||
( 0, 0, touch_pad(0), "", touch_pad0_hold, true)
|
||||
( 1, 1, touch_pad(1), "", touch_pad1_hold, true)
|
||||
( 2, 2, touch_pad(2), "", touch_pad2_hold, true)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user