diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
index 56680f8f1..6b723db70 100644
--- a/esp-hal/CHANGELOG.md
+++ b/esp-hal/CHANGELOG.md
@@ -42,6 +42,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - ESP32/ESP32-S2: Avoid running into timeouts with reads/writes larger than the FIFO (#3199)
 - ESP32: Enforce required pointer alignments in DMA buffers (#3296)
 - ESP32-C6: Keep ADC enabled to improve radio signal strength (#3249)
+- Flex: Revert removal of `Flex::set_as_input` (#3250)
 - Fix off-by-one in the allowed range of the spi clock calculations (#3266)
 - Fixed an issue where inverting a pin via the interconnect matrix was ineffective (#3312)
 - The half-duplex SPI APIs should accept more valid line width combinations (#3325)
diff --git a/esp-hal/src/gpio/mod.rs b/esp-hal/src/gpio/mod.rs
index 1cc320973..31f72f205 100644
--- a/esp-hal/src/gpio/mod.rs
+++ b/esp-hal/src/gpio/mod.rs
@@ -1794,6 +1794,14 @@ impl<'d> Flex<'d> {
         self.pin.set_to_push_pull_output();
     }
 
+    /// Set the GPIO to input mode.
+    #[inline]
+    #[instability::unstable]
+    pub fn set_as_input(&mut self, pull: Pull) {
+        self.pin.init_input(pull);
+        self.pin.enable_output(false);
+    }
+
     /// Set the output as high.
     #[inline]
     #[instability::unstable]