From 6e68da0f4db4a724a96f806668243cbf8828b8a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Wed, 14 Feb 2024 16:35:23 +0100 Subject: [PATCH] ESP32-S3: Use 32K ICACHE (#1169) * ESP32-S3: Use 32K ICACHE * CHANGELOG.md entry --- CHANGELOG.md | 1 + esp-hal/src/soc/esp32s3/mod.rs | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 14ead4f0a..cfcc2ca7c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -38,6 +38,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0 - The `esp-hal-common` package is now called `esp-hal` (#1131) - Refactor the `Trace` driver to be generic around its peripheral (#1140) - Auto detect crystal frequency based on `RtcClock::estimate_xtal_frequency()` (#1165) +- ESP32-S3: Configure 32k ICACHE (#1169) ### Removed - Remove `xtal-26mhz` and `xtal-40mhz` features (#1165) diff --git a/esp-hal/src/soc/esp32s3/mod.rs b/esp-hal/src/soc/esp32s3/mod.rs index a75a839e4..393379122 100644 --- a/esp-hal/src/soc/esp32s3/mod.rs +++ b/esp-hal/src/soc/esp32s3/mod.rs @@ -51,7 +51,7 @@ pub unsafe fn configure_cpu_caches() { } // ideally these should be configurable - const CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE: u32 = 0x4000; // ESP32S3_INSTRUCTION_CACHE_16KB + const CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE: u32 = 0x8000; // ESP32S3_INSTRUCTION_CACHE_32KB const CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS: u8 = 8; // ESP32S3_INSTRUCTION_CACHE_8WAYS const CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE: u8 = 32; // ESP32S3_INSTRUCTION_CACHE_LINE_32B