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Remove partial support for the ESP32-P4 (#1461)

Browse Source 
* Remove all code for and mentions of the ESP32-P4

* Update `CHANGELOG.md`
This commit is contained in:
Jesse Braham 2024-04-17 14:49:00 +00:00 committed by GitHub
parent 54f4f0e90d
commit 71db9fa55c
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
27 changed files with 21 additions and 1826 deletions
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5
.github/workflows/ci.yml vendored
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@ -57,7 +57,6 @@ jobs:
{ soc: "esp32c3", target: "riscv32imc-unknown-none-elf" },
{ soc: "esp32c6", target: "riscv32imac-unknown-none-elf" },
{ soc: "esp32h2", target: "riscv32imac-unknown-none-elf" },
{ soc: "esp32p4", target: "riscv32imafc-unknown-none-elf" },
# Xtensa devices:
{ soc: "esp32", target: "xtensa-esp32-none-elf" },
{ soc: "esp32s2", target: "xtensa-esp32s2-none-elf" },
@ -189,7 +188,6 @@ jobs:
cargo xtask build-package --features=esp32c3 --target=riscv32imc-unknown-none-elf esp-hal
cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-hal
cargo xtask build-package --features=esp32h2 --target=riscv32imac-unknown-none-elf esp-hal
# cargo xtask build-package --features=esp32p4 --target=riscv32imafc-unknown-none-elf esp-hal
- name: msrv (esp-lp-hal)
run: |
cargo xtask build-package --features=esp32c6 --target=riscv32imac-unknown-none-elf esp-lp-hal
@ -244,9 +242,6 @@ jobs:
run: cd esp-hal && cargo clippy --features=esp32c6 --target=riscv32imac-unknown-none-elf -- -D warnings
- name: clippy (esp-hal, esp32h2)
run: cd esp-hal && cargo clippy --features=esp32h2 --target=riscv32imac-unknown-none-elf -- -D warnings
# TODO: Re-enable when able
# - name: clippy (esp-hal, esp32p4)
# run: cd esp-hal && cargo clippy --features=esp32p4 --target=riscv32imafc-unknown-none-elf -- -D warnings
## esp-hal-smartled:
- name: clippy (esp-hal-smartled)
run: cd esp-hal-smartled && cargo clippy --features=esp32c6 --target=riscv32imac-unknown-none-elf -- -D warnings

1
README.md
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@ -10,7 +10,6 @@ Bare-metal (`no_std`) hardware abstraction layer for Espressif devices. Currentl
- ESP32 Series: _ESP32_
- ESP32-C Series: _ESP32-C2 (aka ESP8684), ESP32-C3 (aka ESP8685), ESP32-C6_
- ESP32-H Series: _ESP32-H2_
- ESP32-P Series: _ESP32-P4_
- ESP32-S Series: _ESP32-S2, ESP32-S3_
Additionally provides limited support for programming the low-power RISC-V cores found on the _ESP32-C6_, _ESP32-S2_, and _ESP32-S3_ via the [esp-lp-hal] package.

2
esp-hal-procmacros/Cargo.toml
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@ -41,7 +41,7 @@ rtc_slow = []
has-lp-core = ["dep:object"]
## Indicate that the SoC contains a ULP core.
has-ulp-core = ["dep:object"]
## Provide an `#[entry]` macro for running applications on the ESP32-C6/P4's
## Provide an `#[entry]` macro for running applications on the ESP32-C6's
## LP core.
is-lp-core = []
## Provide an `#[entry]` macro for running applications on the ESP32-S2/S3's

1
esp-hal/CHANGELOG.md
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@ -71,6 +71,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Remove package-level type exports (#1275)
- Removed `direct-vectoring` & `interrupt-preemption` features, as they are now enabled by default (#1310)
- Removed the `rt` and `vectored` features (#1380)
- Remove partial support for the ESP32-P4 (#1461)
## [0.16.1] - 2024-03-12

5
esp-hal/Cargo.toml
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@ -57,7 +57,6 @@ esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", feature
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1d58d95", features = ["critical-section", "rt"], optional = true }
@ -91,7 +90,6 @@ debug = [
"esp32c3?/impl-register-debug",
"esp32c6?/impl-register-debug",
"esp32h2?/impl-register-debug",
"esp32p4?/impl-register-debug",
"esp32s2?/impl-register-debug",
"esp32s3?/impl-register-debug",
]
@ -111,8 +109,6 @@ esp32c3 = ["dep:esp32c3", "riscv", "portable-atomic/unsafe-assume-single-core",
esp32c6 = ["dep:esp32c6", "riscv", "procmacros/has-lp-core", "rv-zero-rtc-bss"]
# Target the ESP32-H2.
esp32h2 = ["dep:esp32h2", "riscv", "rv-zero-rtc-bss"]
# Target the ESP32-P4.
esp32p4 = ["dep:esp32p4", "riscv", "procmacros/has-lp-core", "rv-zero-rtc-bss"]
# Target the ESP32-S2.
esp32s2 = ["dep:esp32s2", "xtensa", "portable-atomic/critical-section", "procmacros/has-ulp-core", "xtensa-lx-rt/esp32s2", "usb-otg"]
# Target the ESP32-S3.
@ -154,7 +150,6 @@ defmt = [
"esp32c3?/defmt",
"esp32c6?/defmt",
"esp32h2?/defmt",
"esp32p4?/defmt",
"esp32s2?/defmt",
"esp32s3?/defmt",
]

4
esp-hal/build.rs
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@ -23,7 +23,7 @@ fn main() -> Result<(), Box<dyn Error>> {
// NOTE: update when adding new device support!
// Ensure that exactly one chip has been specified:
assert_unique_used_features!(
"esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32p4", "esp32s2", "esp32s3"
"esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s2", "esp32s3"
);
// If the `embassy` feature is enabled, ensure that a time driver implementation
@ -57,8 +57,6 @@ fn main() -> Result<(), Box<dyn Error>> {
"esp32c6"
} else if cfg!(feature = "esp32h2") {
"esp32h2"
} else if cfg!(feature = "esp32p4") {
"esp32p4"
} else if cfg!(feature = "esp32s2") {
"esp32s2"
} else if cfg!(feature = "esp32s3") {

75
esp-hal/ld/esp32p4/esp32p4.x
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@ -1,75 +0,0 @@
ENTRY(_start)
PROVIDE(_stext = ORIGIN(ROTEXT));
PROVIDE(_max_hart_id = 1);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6,
ESP32-H2, and ESP32-P4 have IDs 0-31, so we much define the handler for the
one additional interrupt ID: */
PROVIDE(interrupt0 = DefaultHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = _data_start + 0x800);
SECTIONS {
.trap : ALIGN(4)
{
KEEP(*(.trap));
*(.trap.*);
} > RWTEXT
}
INSERT BEFORE .rwtext;
SECTIONS {
/**
* Bootloader really wants to have separate segments for ROTEXT and RODATA
* It also needs to be located in a separate 64k flash segment.
*/
.text_gap (NOLOAD): {
. = ALIGN(0x10000) + 0x20;
} > ROM
}
INSERT BEFORE .rodata;
/* Shared sections - ordering matters */
INCLUDE "text.x"
INCLUDE "rwtext.x"
INCLUDE "rodata.x"
INCLUDE "rwdata.x"
INCLUDE "rtc_fast.x"
INCLUDE "stack.x"
/* End of Shared sections */
INCLUDE "debug.x"

14
esp-hal/ld/esp32p4/linkall.x
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@ -1,14 +0,0 @@
INCLUDE "memory.x"
REGION_ALIAS("ROTEXT", ROM);
REGION_ALIAS("RODATA", ROM);
REGION_ALIAS("RWTEXT", RAM);
REGION_ALIAS("RWDATA", RAM);
REGION_ALIAS("RTC_FAST_RWTEXT", RTC_FAST);
REGION_ALIAS("RTC_FAST_RWDATA", RTC_FAST);
INCLUDE "esp32p4.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

26
esp-hal/ld/esp32p4/memory.x
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@ -1,26 +0,0 @@
MEMORY
{
/* MEMORY_MAP = [
[0x00000000, 0x00010000, "PADDING"],
[0x40000000, 0x4C000000, "DROM"],
[0x4FF00000, 0x4FFA0000, "DRAM"],
[0x4FF00000, 0x4FFA0000, "BYTE_ACCESSIBLE"],
[0x4FC00000, 0x4FC20000, "DROM_MASK"],
[0x4FC00000, 0x4FC20000, "IROM_MASK"],
[0x40000000, 0x4C000000, "IROM"],
[0x4FF00000, 0x4FFA0000, "IRAM"],
[0x50108000, 0x50110000, "RTC_IRAM"],
[0x50108000, 0x50110000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
] */
/* 768K of on soc RAM */
RAM : ORIGIN = 0x4FF00000, LENGTH = 0xC0000
/* External flash */
/* Instruction and Data ROM */
ROM : ORIGIN = 0x40000000 + 0x20, LENGTH = 0x400000 - 0x20
/* RTC fast memory (executable). Persists over deep sleep. */
RTC_FAST : ORIGIN = 0x50108000, LENGTH = 32K /*- ESP_BOOTLOADER_RESERVE_RTC*/
}

8
esp-hal/ld/esp32p4/rom-functions.x
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@ -1,8 +0,0 @@
ets_update_cpu_frequency = 0x4fc00044;
ets_printf = 0x4fc00024;
PROVIDE(ets_delay_us = 0x4fc0003c);
memset = 0x4fc00268;
memcpy = 0x4fc0026c;
memmove = 0x4fc00270;
memcmp = 0x4fc00274;

457
esp-hal/src/clock/clocks_ll/esp32p4.rs
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@ -1,457 +0,0 @@
use crate::clock::{Clock, CpuClock, PllClock, XtalClock};
const DR_REG_LPAON_BASE: u32 = 0x50110000;
const DR_REG_LP_SYS_BASE: u32 = DR_REG_LPAON_BASE + 0x0;
const DR_REG_LPPERIPH_BASE: u32 = 0x50120000;
const DR_REG_I2C_ANA_MST_BASE: u32 = DR_REG_LPPERIPH_BASE + 0x4000;
const LPPERI_CLK_EN_REG: u32 = DR_REG_LPPERIPH_BASE + 0x0;
const LPPERI_CK_EN_LP_I2CMST: u32 = 1 << 27;
const I2C_CPLL_OC_DCHGP_LSB: u8 = 4;
const I2C_CPLL_OC_ENB_FCAL_LSB: u8 = 7;
const I2C_CPLL_OC_DLREF_SEL_LSB: u8 = 6;
const I2C_CPLL_OC_DHREF_SEL_LSB: u8 = 4;
const I2C_ANA_MST_CLK160M_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x34;
const I2C_ANA_MST_CLK_I2C_MST_SEL_160M: u32 = 1 << 0;
const I2C_CPLL: u8 = 0x67;
const I2C_CPLL_HOSTID: u8 = 0;
const I2C_CPLL_OC_REF_DIV: u8 = 2;
const I2C_CPLL_OC_DIV_7_0: u8 = 3;
const I2C_CPLL_OC_DCUR: u8 = 6;
const I2C_ANA_MST_ANA_CONF1_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x1C;
const I2C_ANA_MST_ANA_CONF1: u32 = 0x00FFFFFF;
const I2C_ANA_MST_ANA_CONF1_V: u32 = 0xFFFFFF;
const I2C_ANA_MST_ANA_CONF1_S: u32 = 0;
const I2C_ANA_MST_ANA_CONF2_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x20;
const I2C_ANA_MST_ANA_CONF2: u32 = 0x00FFFFFF;
const I2C_ANA_MST_ANA_CONF2_V: u32 = 0xFFFFFF;
const I2C_ANA_MST_ANA_CONF2_S: u32 = 0;
const REGI2C_RTC_SLAVE_ID_V: u8 = 0xFF;
const REGI2C_RTC_SLAVE_ID_S: u8 = 0;
const REGI2C_RTC_ADDR_V: u8 = 0xFF;
const REGI2C_RTC_ADDR_S: u8 = 8;
const REGI2C_RTC_WR_CNTL_V: u8 = 0x1;
const REGI2C_RTC_WR_CNTL_S: u8 = 24;
const REGI2C_RTC_DATA_V: u8 = 0xFF;
const REGI2C_RTC_DATA_S: u8 = 16;
const REGI2C_RTC_BUSY: u32 = 1 << 25;
const I2C_ANA_MST_I2C0_CTRL_REG: u32 = DR_REG_I2C_ANA_MST_BASE + 0x0;
const DR_REG_PMU_BASE: u32 = DR_REG_LPAON_BASE + 0x5000;
const PMU_IMM_HP_CK_POWER: u32 = DR_REG_PMU_BASE + 0xcc;
const PMU_TIE_HIGH_XPD_CPLL: u32 = 1 << 27;
const PMU_TIE_HIGH_XPD_CPLL_I2C: u32 = 1 << 23;
const PMU_TIE_HIGH_GLOBAL_CPLL_ICG: u32 = 1 << 17;
const DR_REG_HPPERIPH1_BASE: u32 = 0x500C0000;
const DR_REG_HP_SYS_CLKRST_BASE: u32 = DR_REG_HPPERIPH1_BASE + 0x26000;
const HP_SYS_CLKRST_ANA_PLL_CTRL0: u32 = DR_REG_HP_SYS_CLKRST_BASE + 0xbc;
const HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP: u32 = 1 << 3;
const HP_SYS_CLKRST_REG_CPU_PLL_CAL_END: u32 = 1 << 2;
const HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V: u32 = 0x000000FF;
const REGI2C_DIG_REG: u8 = 0x6d;
const REGI2C_CPU_PLL: u8 = 0x67;
const REGI2C_SDIO_PLL: u8 = 0x62;
const REGI2C_BIAS: u8 = 0x6a;
const REGI2C_MSPI: u8 = 0x63;
const REGI2C_SYS_PLL: u8 = 0x66;
const REGI2C_PLLA: u8 = 0x6f;
const REGI2C_SAR_I2C: u8 = 0x69;
const REGI2C_DIG_REG_MST_SEL: u32 = 1 << 10;
const REGI2C_PLL_CPU_MST_SEL: u32 = 1 << 11;
const REGI2C_PLL_SDIO_MST_SEL: u32 = 1 << 6;
const REGI2C_BIAS_MST_SEL: u32 = 1 << 12;
const REGI2C_MSPI_XTAL_MST_SEL: u32 = 1 << 9;
const REGI2C_PLL_SYS_MST_SEL: u32 = 1 << 5;
const REGI2C_PLLA_MST_SEL: u32 = 1 << 8;
const REGI2C_SAR_I2C_MST_SEL: u32 = 1 << 7;
const RTC_XTAL_FREQ_REG: u32 = DR_REG_LP_SYS_BASE + 0x3c;
const RTC_DISABLE_ROM_LOG: u32 = (1 << 0) | (1 << 16);
// rtc_clk.c (L125) -> clk_tree_ll.h
pub(crate) fn esp32p4_rtc_cpll_enable() {
unsafe {
(PMU_IMM_HP_CK_POWER as *mut u32).write_volatile(
(PMU_IMM_HP_CK_POWER as *mut u32).read_volatile()
| (PMU_TIE_HIGH_XPD_CPLL | PMU_TIE_HIGH_XPD_CPLL_I2C),
);
(PMU_IMM_HP_CK_POWER as *mut u32).write_volatile(
(PMU_IMM_HP_CK_POWER as *mut u32).read_volatile() | PMU_TIE_HIGH_GLOBAL_CPLL_ICG,
)
}
}
// rtc_clk.c (L136)
pub(crate) fn esp32p4_rtc_cpll_configure(xtal_freq: XtalClock, cpll_freq: PllClock) {
// CPLL CALIBRATION START
unsafe {
(HP_SYS_CLKRST_ANA_PLL_CTRL0 as *mut u32).write_volatile(
(HP_SYS_CLKRST_ANA_PLL_CTRL0 as *mut u32).read_volatile()
| !HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP,
);
}
// Set configuration
let mut oc_div_ref = 0u32;
let mut div = 1u32;
let dcur = 3u32;
let dchgp = 5u32;
let enb_fcal = 0u32;
// Currently only supporting 40MHz XTAL
assert!(xtal_freq.mhz() == XtalClock::RtcXtalFreq40M.mhz());
match cpll_freq {
PllClock::Pll400MHz => {
div = 6u32;
oc_div_ref = 0u32;
}
PllClock::Pll360MHz => {
div = 5u32;
oc_div_ref = 0u32;
}
_ => (),
}
let i2c_cpll_lref =
(enb_fcal << I2C_CPLL_OC_ENB_FCAL_LSB) | (dchgp << I2C_CPLL_OC_DCHGP_LSB) | (oc_div_ref);
let i2c_cpll_dcur = (1 << I2C_CPLL_OC_DLREF_SEL_LSB) | (3 << I2C_CPLL_OC_DHREF_SEL_LSB) | dcur;
regi2c_write(
I2C_CPLL,
I2C_CPLL_HOSTID,
I2C_CPLL_OC_REF_DIV,
i2c_cpll_lref as u8,
);
regi2c_write(I2C_CPLL, I2C_CPLL_HOSTID, I2C_CPLL_OC_DIV_7_0, div as u8);
regi2c_write(
I2C_CPLL,
I2C_CPLL_HOSTID,
I2C_CPLL_OC_DCUR,
i2c_cpll_dcur as u8,
);
// Wait calibration done
while !reg_get_bit(
HP_SYS_CLKRST_ANA_PLL_CTRL0,
HP_SYS_CLKRST_REG_CPU_PLL_CAL_END,
) == 1
{}
crate::rom::ets_delay_us(10);
// CPLL calibration stop
set_peri_reg_mask(
HP_SYS_CLKRST_ANA_PLL_CTRL0,
HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP,
);
}
// rtc_clk.c (L161)
pub(crate) fn esp32p4_rtc_update_to_xtal(freq: XtalClock, div: u8, default: bool) {
let mut mem_divider = 1u32;
let mut sys_divider = 1u32;
let apb_divider = 1u32;
if default {
mem_divider = 2u32;
sys_divider = 2u32;
}
// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL -> 0)
unsafe {
(&*crate::soc::peripherals::LP_AON_CLKRST::PTR)
.lp_aonclkrst_hp_clk_ctrl()
.modify(|_, w| w.lp_aonclkrst_hp_root_clk_src_sel().bits(0b00))
}
// clk_ll_cpu_set_divider(div, 0, 0) ->
// clk_tree_ll.h(comp/hal/p4/include/hal/L407)
assert!(div >= 1 && (div as u32) < HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V);
let hp_sys_clkrst = unsafe { &*crate::soc::peripherals::HP_SYS_CLKRST::PTR };
unsafe {
// Set CPU divider:
hp_sys_clkrst.root_clk_ctrl0().modify(|_, w| {
w.cpu_clk_div_num()
.bits(div - 1)
.cpu_clk_div_numerator()
.bits(0)
.cpu_clk_div_denominator()
.bits(0)
});
// Set memory and system dividers:
hp_sys_clkrst.root_clk_ctrl1().modify(|_, w| {
w.mem_clk_div_num()
.bits((mem_divider - 1) as u8)
.sys_clk_div_num()
.bits((sys_divider - 1) as u8)
});
// Set APB divider:
hp_sys_clkrst
.root_clk_ctrl2()
.modify(|_, w| w.apb_clk_div_num().bits((apb_divider - 1) as u8));
// Bus update:
hp_sys_clkrst
.root_clk_ctrl0()
.modify(|_, w| w.soc_clk_div_update().set_bit());
while hp_sys_clkrst
.root_clk_ctrl0()
.read()
.soc_clk_div_update()
.bit_is_set()
{}
}
crate::rom::ets_update_cpu_frequency_rom(freq.mhz());
}
// esp_rom_regi2c_esp32p4.c (L84)
fn regi2c_enable_block(block: u8) {
reg_set_bit(LPPERI_CLK_EN_REG, LPPERI_CK_EN_LP_I2CMST);
set_peri_reg_mask(I2C_ANA_MST_CLK160M_REG, I2C_ANA_MST_CLK_I2C_MST_SEL_160M);
reg_set_field(
I2C_ANA_MST_ANA_CONF2_REG,
I2C_ANA_MST_ANA_CONF2_V,
I2C_ANA_MST_ANA_CONF2_S,
0,
);
reg_set_field(
I2C_ANA_MST_ANA_CONF1_REG,
I2C_ANA_MST_ANA_CONF1_V,
I2C_ANA_MST_ANA_CONF1_S,
0,
);
match block {
REGI2C_DIG_REG => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
}
REGI2C_CPU_PLL => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL);
}
REGI2C_SDIO_PLL => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL);
}
REGI2C_BIAS => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
}
REGI2C_MSPI => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL);
}
REGI2C_SYS_PLL => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL);
}
REGI2C_PLLA => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL);
}
REGI2C_SAR_I2C => {
reg_set_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
}
_ => (),
}
}
pub(crate) fn esp32p4_rtc_freq_to_cpll_mhz(cpu_clock_speed: CpuClock) {
// CPLL -> CPU_CLK -> MEM_CLK -> SYS_CLK -> APB_CLK
// Constraint: MEM_CLK <= 200MHz, APB_CLK <= 100MHz
// This implies that when clock source is CPLL,
// If cpu_divider < 2, mem_divider must be larger or equal to
// 2 If cpu_divider < 2, mem_divider = 2, sys_divider < 2,
// apb_divider must be larger or equal to 2 Current available
// configurations: 360 - 360 - 180 - 180 - 90
// 360 - 180 - 180 - 180 - 90
// 360 - 90 - 90 - 90 - 90
// freq_mhz_to_config part (rtc_clk.c L251)
// rtc_clk_xtal_freq_get() -> xtal_load_freq_mhz()
let xtal_freq_reg = unsafe { (RTC_XTAL_FREQ_REG as *mut u32).read_volatile() as u32 };
let mut xtal_freq = 0u32;
let mut real_freq = 0u32;
let mut div_integer = 0u32;
let div_denominator = 0u32;
let mut div_numerator = 0u32;
if (xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF)
&& xtal_freq_reg != 0
&& xtal_freq_reg != u32::MAX
{
xtal_freq = xtal_freq_reg & !RTC_DISABLE_ROM_LOG & u16::MAX as u32;
}
// Keep default CPLL at 360 MHz
if cpu_clock_speed.mhz() <= xtal_freq {
div_integer = xtal_freq / cpu_clock_speed.mhz();
real_freq = (xtal_freq + div_integer / 2) / div_integer; // round
// Check whether divider is suitable
assert!(real_freq == cpu_clock_speed.mhz());
} else {
div_integer = 1;
}
let mut mem_div = 0u32;
let mut sys_div = 0u32;
let mut apb_div = 0u32;
match cpu_clock_speed {
CpuClock::Clock360MHz => {
mem_div = 2;
apb_div = 2;
}
CpuClock::Clock180MHz => {
mem_div = 1;
apb_div = 2;
}
CpuClock::Clock90MHz => {
mem_div = 1;
apb_div = 1;
}
_ => {
panic!("Unsupported configuration")
}
}
// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); (rtc_clk.c L242)
unsafe {
(&*crate::soc::peripherals::LP_AON_CLKRST::PTR)
.lp_aonclkrst_hp_clk_ctrl()
.modify(|_, w| w.lp_aonclkrst_hp_root_clk_src_sel().bits(0b01));
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl0()
.modify(|_, w| w.cpu_clk_div_num().bits((div_integer - 1) as u8));
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl0()
.modify(|_, w| w.cpu_clk_div_numerator().bits(0));
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl0()
.modify(|_, w| w.cpu_clk_div_denominator().bits(0));
// Set memory divider
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl1()
.modify(|_, w| w.mem_clk_div_num().bits((mem_div - 1) as u8));
// Set system divider
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl1()
.modify(|_, w| w.sys_clk_div_num().bits((sys_div - 1) as u8));
// Set APB divider
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl2()
.modify(|_, w| w.apb_clk_div_num().bits((apb_div - 1) as u8));
// Bus update
(&*crate::soc::peripherals::HP_SYS_CLKRST::PTR)
.root_clk_ctrl0()
.modify(|_, w| w.soc_clk_div_update().set_bit());
}
crate::rom::ets_update_cpu_frequency_rom(cpu_clock_speed.mhz());
}
fn regi2c_disable_block(block: u8) {
match block {
REGI2C_DIG_REG => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
}
REGI2C_CPU_PLL => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_CPU_MST_SEL);
}
REGI2C_SDIO_PLL => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SDIO_MST_SEL);
}
REGI2C_BIAS => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
}
REGI2C_MSPI => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_MSPI_XTAL_MST_SEL);
}
REGI2C_SYS_PLL => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLL_SYS_MST_SEL);
}
REGI2C_PLLA => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_PLLA_MST_SEL);
}
REGI2C_SAR_I2C => {
reg_clr_bit(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
}
_ => (),
}
}
pub(crate) fn regi2c_write(block: u8, _host_id: u8, reg_add: u8, data: u8) {
regi2c_enable_block(block);
let temp: u32 = ((block as u32 & REGI2C_RTC_SLAVE_ID_V as u32) << REGI2C_RTC_SLAVE_ID_S as u32)
| ((reg_add as u32 & REGI2C_RTC_ADDR_V as u32) << REGI2C_RTC_ADDR_S as u32)
| ((0x1 & REGI2C_RTC_WR_CNTL_V as u32) << REGI2C_RTC_WR_CNTL_S as u32) // 0: READ I2C register; 1: Write I2C register;
| (((data as u32) & REGI2C_RTC_DATA_V as u32) << REGI2C_RTC_DATA_S as u32);
reg_write(I2C_ANA_MST_I2C0_CTRL_REG, temp);
while reg_get_bit(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY) != 0 {}
regi2c_disable_block(block);
}
fn reg_set_field(reg: u32, field_v: u32, field_s: u32, value: u32) {
unsafe {
(reg as *mut u32).write_volatile(
((reg as *mut u32).read_volatile() & !(field_v << field_s))
| ((value & field_v) << field_s),
)
}
}
fn reg_set_bit(reg: u32, bit: u32) {
unsafe {
(reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() | bit);
}
}
fn reg_write(reg: u32, v: u32) {
unsafe {
(reg as *mut u32).write_volatile(v);
}
}
fn reg_get_bit(reg: u32, b: u32) -> u32 {
unsafe { (reg as *mut u32).read_volatile() & b }
}
fn reg_clr_bit(reg: u32, bit: u32) {
unsafe {
(reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() & !bit);
}
}
fn set_peri_reg_mask(reg: u32, mask: u32) {
unsafe {
(reg as *mut u32).write_volatile((reg as *mut u32).read_volatile() | mask);
}
}

107
esp-hal/src/clock/mod.rs
View File

@ -67,7 +67,6 @@ use crate::{
#[cfg_attr(esp32c3, path = "clocks_ll/esp32c3.rs")]
#[cfg_attr(esp32c6, path = "clocks_ll/esp32c6.rs")]
#[cfg_attr(esp32h2, path = "clocks_ll/esp32h2.rs")]
#[cfg_attr(esp32p4, path = "clocks_ll/esp32p4.rs")]
#[cfg_attr(esp32s2, path = "clocks_ll/esp32s2.rs")]
#[cfg_attr(esp32s3, path = "clocks_ll/esp32s3.rs")]
pub(crate) mod clocks_ll;
@ -87,48 +86,32 @@ pub trait Clock {
/// CPU clock speed
#[derive(Debug, Clone, Copy)]
pub enum CpuClock {
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
Clock80MHz,
#[cfg(esp32p4)]
Clock90MHz,
#[cfg(esp32h2)]
Clock96MHz,
#[cfg(esp32c2)]
Clock120MHz,
#[cfg(not(any(esp32c2, esp32h2, esp32p4)))]
#[cfg(not(any(esp32c2, esp32h2)))]
Clock160MHz,
#[cfg(esp32p4)]
Clock180MHz,
#[cfg(xtensa)]
Clock240MHz,
#[cfg(esp32p4)]
Clock360MHz,
#[cfg(esp32p4)]
Clock400MHz,
}
#[allow(dead_code)]
impl Clock for CpuClock {
fn frequency(&self) -> HertzU32 {
match self {
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
CpuClock::Clock80MHz => HertzU32::MHz(80),
#[cfg(esp32p4)]
CpuClock::Clock90MHz => HertzU32::MHz(90),
#[cfg(esp32h2)]
CpuClock::Clock96MHz => HertzU32::MHz(96),
#[cfg(esp32c2)]
CpuClock::Clock120MHz => HertzU32::MHz(120),
#[cfg(not(any(esp32c2, esp32h2, esp32p4)))]
#[cfg(not(any(esp32c2, esp32h2)))]
CpuClock::Clock160MHz => HertzU32::MHz(160),
#[cfg(esp32p4)]
CpuClock::Clock180MHz => HertzU32::MHz(180),
#[cfg(xtensa)]
CpuClock::Clock240MHz => HertzU32::MHz(240),
#[cfg(esp32p4)]
CpuClock::Clock360MHz => HertzU32::MHz(360),
#[cfg(esp32p4)]
CpuClock::Clock400MHz => HertzU32::MHz(400),
}
}
}
@ -178,16 +161,10 @@ pub(crate) enum PllClock {
Pll160MHz,
#[cfg(esp32c6)]
Pll240MHz,
#[cfg(not(any(esp32c2, esp32c6, esp32h2, esp32p4)))]
#[cfg(not(any(esp32c2, esp32c6, esp32h2)))]
Pll320MHz,
#[cfg(esp32p4)]
Pll360MHz,
#[cfg(esp32p4)]
Pll400MHz,
#[cfg(not(esp32h2))]
Pll480MHz,
#[cfg(esp32p4)]
Pll500MHz,
}
impl Clock for PllClock {
@ -209,16 +186,10 @@ impl Clock for PllClock {
Self::Pll160MHz => HertzU32::MHz(160),
#[cfg(esp32c6)]
Self::Pll240MHz => HertzU32::MHz(240),
#[cfg(not(any(esp32c2, esp32c6, esp32h2, esp32p4)))]
#[cfg(not(any(esp32c2, esp32c6, esp32h2)))]
Self::Pll320MHz => HertzU32::MHz(320),
#[cfg(esp32p4)]
Self::Pll360MHz => HertzU32::MHz(360),
#[cfg(esp32p4)]
Self::Pll400MHz => HertzU32::MHz(400),
#[cfg(not(esp32h2))]
Self::Pll480MHz => HertzU32::MHz(480),
#[cfg(esp32p4)]
Self::Pll500MHz => HertzU32::MHz(500),
}
}
}
@ -228,12 +199,10 @@ impl Clock for PllClock {
pub(crate) enum ApbClock {
#[cfg(esp32h2)]
ApbFreq32MHz,
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
ApbFreq40MHz,
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
ApbFreq80MHz,
#[cfg(esp32p4)]
ApbFreq100MHz,
ApbFreqOther(u32),
}
@ -242,12 +211,10 @@ impl Clock for ApbClock {
match self {
#[cfg(esp32h2)]
ApbClock::ApbFreq32MHz => HertzU32::MHz(32),
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
ApbClock::ApbFreq40MHz => HertzU32::MHz(40),
#[cfg(not(any(esp32h2, esp32p4)))]
#[cfg(not(esp32h2))]
ApbClock::ApbFreq80MHz => HertzU32::MHz(80),
#[cfg(esp32p4)]
ApbClock::ApbFreq100MHz => HertzU32::MHz(100),
ApbClock::ApbFreqOther(mhz) => HertzU32::MHz(*mhz),
}
}
@ -643,60 +610,6 @@ impl<'d> ClockControl<'d> {
}
}
#[cfg(esp32p4)]
impl<'d> ClockControl<'d> {
/// Use what is considered the default settings after boot.
pub fn boot_defaults(
clock_control: impl Peripheral<P = SystemClockControl> + 'd,
) -> ClockControl<'d> {
ClockControl {
_private: clock_control.into_ref(),
desired_rates: RawClocks {
cpu_clock: HertzU32::MHz(400),
apb_clock: HertzU32::MHz(100),
xtal_clock: HertzU32::MHz(40),
},
}
}
/// Configure the CPU clock speed.
pub fn configure(
clock_control: impl Peripheral<P = SystemClockControl> + 'd,
cpu_clock_speed: CpuClock,
) -> ClockControl<'d> {
let apb_freq;
let xtal_freq = XtalClock::RtcXtalFreq40M;
let pll_freq = PllClock::Pll480MHz;
if cpu_clock_speed.mhz() <= xtal_freq.mhz() {
apb_freq = ApbClock::ApbFreqOther(cpu_clock_speed.mhz());
clocks_ll::esp32p4_rtc_update_to_xtal(xtal_freq, 1, true);
} else {
apb_freq = ApbClock::ApbFreq100MHz;
clocks_ll::esp32p4_rtc_cpll_enable();
// Calibrate CPLL freq to a new value requires to switch CPU clock source to
// XTAL first
clocks_ll::esp32p4_rtc_update_to_xtal(xtal_freq, 1, false);
clocks_ll::esp32p4_rtc_cpll_configure(xtal_freq, pll_freq);
clocks_ll::esp32p4_rtc_freq_to_cpll_mhz(cpu_clock_speed);
}
ClockControl {
_private: clock_control.into_ref(),
desired_rates: RawClocks {
cpu_clock: cpu_clock_speed.frequency(),
apb_clock: apb_freq.frequency(),
xtal_clock: xtal_freq.frequency(),
},
}
}
/// Use the highest possible frequency for a particular chip
pub fn max(clock_control: impl Peripheral<P = SystemClockControl> + 'd) -> ClockControl<'d> {
Self::configure(clock_control, CpuClock::Clock400MHz)
}
}
#[cfg(esp32s2)]
impl<'d> ClockControl<'d> {
/// Use what is considered the default settings after boot.

4
esp-hal/src/dma/gdma.rs
View File

@ -50,7 +50,7 @@ impl<const N: u8> Channel<N> {
dma.int_ch(N as usize)
}
#[inline(always)]
#[cfg(any(esp32c6, esp32h2))] // also esp32p4 AHB_DMA
#[cfg(any(esp32c6, esp32h2))]
fn in_int() -> &'static crate::peripherals::dma::in_int_ch::IN_INT_CH {
let dma = unsafe { &*crate::peripherals::DMA::PTR };
dma.in_int_ch(N as usize)
@ -69,7 +69,7 @@ impl<const N: u8> Channel<N> {
dma.int_ch(N as usize)
}
#[inline(always)]
#[cfg(any(esp32c6, esp32h2))] // also esp32p4 AHB_DMA
#[cfg(any(esp32c6, esp32h2))]
fn out_int() -> &'static crate::peripherals::dma::out_int_ch::OUT_INT_CH {
let dma = unsafe { &*crate::peripherals::DMA::PTR };
dma.out_int_ch(N as usize)

19
esp-hal/src/gpio/mod.rs
View File

@ -829,7 +829,6 @@ where
}
}
#[cfg(not(any(esp32p4)))]
unsafe {
(*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
w.int_ena()
@ -840,20 +839,6 @@ where
.bit(wake_up_from_light_sleep)
});
}
#[cfg(esp32p4)]
unsafe {
// there is no NMI_ENABLE but P4 could trigger 4 interrupts
// we'll only support GPIO_INT0 for now
(*GPIO::PTR).pin(GPIONUM as usize).modify(|_, w| {
w.int_ena()
.bits(gpio_intr_enable(int_enable, nmi_enable))
.int_type()
.bits(event as u8)
.wakeup_enable()
.bit(wake_up_from_light_sleep)
});
}
}
fn is_listening(&self) -> bool {
@ -2385,7 +2370,7 @@ mod asynch {
pub(super) fn handle_gpio_interrupt() {
let intrs_bank0 = InterruptStatusRegisterAccessBank0::interrupt_status_read();
#[cfg(any(esp32, esp32s2, esp32s3, esp32p4))]
#[cfg(any(esp32, esp32s2, esp32s3))]
let intrs_bank1 = InterruptStatusRegisterAccessBank1::interrupt_status_read();
let mut intr_bits = intrs_bank0;
@ -2399,7 +2384,7 @@ mod asynch {
// clear interrupt bits
Bank0GpioRegisterAccess::write_interrupt_status_clear(intrs_bank0);
#[cfg(any(esp32, esp32s2, esp32s3, esp32p4))]
#[cfg(any(esp32, esp32s2, esp32s3))]
{
let mut intr_bits = intrs_bank1;
while intr_bits != 0 {

2
esp-hal/src/rng.rs
View File

@ -76,7 +76,6 @@ pub struct Rng {
impl Rng {
/// Create a new random number generator instance
pub fn new(_rng: impl Peripheral<P = RNG>) -> Self {
#[cfg(not(esp32p4))]
crate::soc::trng::ensure_randomness();
Self {
@ -144,5 +143,4 @@ impl rand_core::RngCore for Rng {
}
}
#[cfg(not(esp32p4))]
impl rand_core::CryptoRng for Rng {}

96
esp-hal/src/rtc_cntl/rtc/esp32p4.rs
View File

@ -1,96 +0,0 @@
use fugit::HertzU32;
use strum::FromRepr;
use crate::clock::Clock;
pub(crate) fn init() {
todo!()
}
pub(crate) fn configure_clock() {
todo!()
}
// Terminology:
//
// CPU Reset: Reset CPU core only, once reset done, CPU will execute from
// reset vector
// Core Reset: Reset the whole digital system except RTC sub-system
// System Reset: Reset the whole digital system, including RTC sub-system
// Chip Reset: Reset the whole chip, including the analog part
// spc/p4/include/soc/reset_reasons.h
#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
pub enum SocResetReason {
/// Power on reset
///
/// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
/// `ChipSuperWdt`, however that is not really compatible with Rust-style
/// enums.
ChipPowerOn = 0x01,
/// Software resets the digital core by RTC_CNTL_SW_SYS_RST
CoreSw = 0x03,
/// Deep sleep reset the digital core
CoreDeepSleep = 0x05,
// PMU HP power down system reset
SysPmuPwrDown = 0x05,
// PMU HP power down CPU reset
CpuPmuPwrDown = 0x06,
/// HP watch dog resets system
SysHpWdt = 0x07,
/// LP watch dog resets system
SysLpWdt = 0x09,
/// HP watch dog resets digital core
CoreHpWdt = 0x0B,
/// Software resets CPU 0
Cpu0Sw = 0x0C,
/// LP watch dog resets digital core
CpuLpWdt = 0x0D,
/// VDD voltage is not stable and resets the digital core
SysBrownOut = 0x0F,
/// LP watch dog resets chip
ChipLpWdt = 0x10,
/// Super watch dog resets the digital core and rtc module
SysSuperWdt = 0x12,
/// Glitch on clock resets the digital core and rtc module
SysClkGlitch = 0x13,
/// eFuse CRC error resets the digital core
CoreEfuseCrc = 0x14,
/// USB JTAG resets the digital core
CoreUsbJtag = 0x16,
// USB Serial/JTAG controller's UART resets the digital core
CoreUsbUart = 0x17,
// Glitch on power resets the digital core
CpuJtag = 0x18,
}
/// RTC SLOW_CLK frequency values
#[derive(Debug, Clone, Copy)]
pub(crate) enum RtcFastClock {}
impl Clock for RtcFastClock {
fn frequency(&self) -> HertzU32 {
todo!()
}
}
/// RTC SLOW_CLK frequency values
#[derive(Debug, Clone, Copy, PartialEq)]
pub(crate) enum RtcSlowClock {}
impl Clock for RtcSlowClock {
fn frequency(&self) -> HertzU32 {
todo!()
}
}
/// RTC Watchdog Timer
pub struct RtcClock;
/// RTC Watchdog Timer driver
impl RtcClock {
/// Calculate the necessary RTC_SLOW_CLK cycles to complete 1 millisecond.
pub(crate) fn cycles_to_1ms() -> u16 {
todo!()
}
}

312
esp-hal/src/soc/esp32p4/efuse/fields.rs
View File

@ -1,312 +0,0 @@
//! eFuse fields for the ESP32-P4.
//!
//! This file was automatically generated, please do not edit it manually!
//!
//! For information on how to regenerate these files, please refer to the
//! `xtask` package's `README.md` file.
//!
//! Generated on: 2024-03-11
//! ESP-IDF Commit: 0de2912f
use super::EfuseBlock;
use crate::soc::efuse_field::EfuseField;
/// `[]` Disable programming of individual eFuses
pub const WR_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 32);
/// `[]` wr_dis of RD_DIS
pub const WR_DIS_RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 0, 1);
/// `[]` wr_dis of SPI_BOOT_CRYPT_CNT
pub const WR_DIS_SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 4, 1);
/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE0
pub const WR_DIS_SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 5, 1);
/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE1
pub const WR_DIS_SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 6, 1);
/// `[]` wr_dis of SECURE_BOOT_KEY_REVOKE2
pub const WR_DIS_SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 7, 1);
/// `[WR_DIS.KEY0_PURPOSE]` wr_dis of KEY_PURPOSE_0
pub const WR_DIS_KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 8, 1);
/// `[WR_DIS.KEY1_PURPOSE]` wr_dis of KEY_PURPOSE_1
pub const WR_DIS_KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 9, 1);
/// `[WR_DIS.KEY2_PURPOSE]` wr_dis of KEY_PURPOSE_2
pub const WR_DIS_KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 10, 1);
/// `[WR_DIS.KEY3_PURPOSE]` wr_dis of KEY_PURPOSE_3
pub const WR_DIS_KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 11, 1);
/// `[WR_DIS.KEY4_PURPOSE]` wr_dis of KEY_PURPOSE_4
pub const WR_DIS_KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 12, 1);
/// `[WR_DIS.KEY5_PURPOSE]` wr_dis of KEY_PURPOSE_5
pub const WR_DIS_KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 13, 1);
/// `[]` wr_dis of SECURE_BOOT_EN
pub const WR_DIS_SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 15, 1);
/// `[]` wr_dis of BLOCK1
pub const WR_DIS_BLK1: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[WR_DIS.MAC_FACTORY]` wr_dis of MAC
pub const WR_DIS_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of WAFER_VERSION_MINOR
pub const WR_DIS_WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of WAFER_VERSION_MAJOR
pub const WR_DIS_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of DISABLE_WAFER_VERSION_MAJOR
pub const WR_DIS_DISABLE_WAFER_VERSION_MAJOR: EfuseField =
EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of DISABLE_BLK_VERSION_MAJOR
pub const WR_DIS_DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of BLK_VERSION_MINOR
pub const WR_DIS_BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of BLK_VERSION_MAJOR
pub const WR_DIS_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of FLASH_CAP
pub const WR_DIS_FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of FLASH_TEMP
pub const WR_DIS_FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of FLASH_VENDOR
pub const WR_DIS_FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of PSRAM_CAP
pub const WR_DIS_PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of PSRAM_TEMP
pub const WR_DIS_PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of PSRAM_VENDOR
pub const WR_DIS_PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of PKG_VERSION
pub const WR_DIS_PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 20, 1);
/// `[]` wr_dis of BLOCK2
pub const WR_DIS_SYS_DATA_PART1: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1);
/// `[]` wr_dis of OPTIONAL_UNIQUE_ID
pub const WR_DIS_OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block0, 21, 1);
/// `[WR_DIS.USER_DATA]` wr_dis of BLOCK_USR_DATA
pub const WR_DIS_BLOCK_USR_DATA: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1);
/// `[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]` wr_dis of CUSTOM_MAC
pub const WR_DIS_CUSTOM_MAC: EfuseField = EfuseField::new(EfuseBlock::Block0, 22, 1);
/// `[WR_DIS.KEY0]` wr_dis of BLOCK_KEY0
pub const WR_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 23, 1);
/// `[WR_DIS.KEY1]` wr_dis of BLOCK_KEY1
pub const WR_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 24, 1);
/// `[WR_DIS.KEY2]` wr_dis of BLOCK_KEY2
pub const WR_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 25, 1);
/// `[WR_DIS.KEY3]` wr_dis of BLOCK_KEY3
pub const WR_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 26, 1);
/// `[WR_DIS.KEY4]` wr_dis of BLOCK_KEY4
pub const WR_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 27, 1);
/// `[WR_DIS.KEY5]` wr_dis of BLOCK_KEY5
pub const WR_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 28, 1);
/// `[WR_DIS.SYS_DATA_PART2]` wr_dis of BLOCK_SYS_DATA2
pub const WR_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 29, 1);
/// `[]` Disable reading from BlOCK4-10
pub const RD_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 7);
/// `[RD_DIS.KEY0]` rd_dis of BLOCK_KEY0
pub const RD_DIS_BLOCK_KEY0: EfuseField = EfuseField::new(EfuseBlock::Block0, 32, 1);
/// `[RD_DIS.KEY1]` rd_dis of BLOCK_KEY1
pub const RD_DIS_BLOCK_KEY1: EfuseField = EfuseField::new(EfuseBlock::Block0, 33, 1);
/// `[RD_DIS.KEY2]` rd_dis of BLOCK_KEY2
pub const RD_DIS_BLOCK_KEY2: EfuseField = EfuseField::new(EfuseBlock::Block0, 34, 1);
/// `[RD_DIS.KEY3]` rd_dis of BLOCK_KEY3
pub const RD_DIS_BLOCK_KEY3: EfuseField = EfuseField::new(EfuseBlock::Block0, 35, 1);
/// `[RD_DIS.KEY4]` rd_dis of BLOCK_KEY4
pub const RD_DIS_BLOCK_KEY4: EfuseField = EfuseField::new(EfuseBlock::Block0, 36, 1);
/// `[RD_DIS.KEY5]` rd_dis of BLOCK_KEY5
pub const RD_DIS_BLOCK_KEY5: EfuseField = EfuseField::new(EfuseBlock::Block0, 37, 1);
/// `[RD_DIS.SYS_DATA_PART2]` rd_dis of BLOCK_SYS_DATA2
pub const RD_DIS_BLOCK_SYS_DATA2: EfuseField = EfuseField::new(EfuseBlock::Block0, 38, 1);
/// `[]` Enable usb device exchange pins of D+ and D-
pub const USB_DEVICE_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 39, 1);
/// `[]` Enable usb otg11 exchange pins of D+ and D-
pub const USB_OTG11_EXCHG_PINS: EfuseField = EfuseField::new(EfuseBlock::Block0, 40, 1);
/// `[]` Represents whether the function of usb switch to jtag is disabled or
/// enabled. 1: disabled. 0: enabled
pub const DIS_USB_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 41, 1);
/// `[]` Represents whether power glitch function is enabled. 1: enabled. 0:
/// disabled
pub const POWERGLITCH_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 42, 1);
/// `[]` Represents whether the function that forces chip into download mode is
/// disabled or enabled. 1: disabled. 0: enabled
pub const DIS_FORCE_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 44, 1);
/// `[]` Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix
/// during boot_mode_download
pub const SPI_DOWNLOAD_MSPI_DIS: EfuseField = EfuseField::new(EfuseBlock::Block0, 45, 1);
/// `[]` Represents whether TWAI function is disabled or enabled. 1: disabled.
/// 0: enabled
pub const DIS_TWAI: EfuseField = EfuseField::new(EfuseBlock::Block0, 46, 1);
/// `[]` Represents whether the selection between usb_to_jtag and pad_to_jtag
/// through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG
/// are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
pub const JTAG_SEL_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 47, 1);
/// `[]` Represents whether JTAG is disabled in soft way. Odd number: disabled.
/// Even number: enabled
pub const SOFT_DIS_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 48, 3);
/// `[]` Represents whether JTAG is disabled in the hard way(permanently). 1:
/// disabled. 0: enabled
pub const DIS_PAD_JTAG: EfuseField = EfuseField::new(EfuseBlock::Block0, 51, 1);
/// `[]` Represents whether flash encrypt function is disabled or enabled(except
/// in SPI boot mode). 1: disabled. 0: enabled
pub const DIS_DOWNLOAD_MANUAL_ENCRYPT: EfuseField = EfuseField::new(EfuseBlock::Block0, 52, 1);
/// `[]` TBD
pub const USB_PHY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 57, 1);
/// `[]` Set this bit to control validation of HUK generate mode. Odd of 1 is
/// invalid; even of 1 is valid
pub const KM_HUK_GEN_STATE: EfuseField = EfuseField::new(EfuseBlock::Block0, 58, 9);
/// `[]` Set bits to control key manager random number switch cycle. 0: control
/// by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
pub const KM_RND_SWITCH_CYCLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 67, 2);
/// `[]` Set each bit to control whether corresponding key can only be deployed
/// once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
pub const KM_DEPLOY_ONLY_ONCE: EfuseField = EfuseField::new(EfuseBlock::Block0, 69, 4);
/// `[]` Set each bit to control whether corresponding key must come from key
/// manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3:
/// ds
pub const FORCE_USE_KEY_MANAGER_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 73, 4);
/// `[]` Set this bit to disable software written init key; and force use
/// efuse_init_key
pub const FORCE_DISABLE_SW_INIT_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 77, 1);
/// `[]` Set this bit to configure flash encryption use xts-128 key; else use
/// xts-256 key
pub const XTS_KEY_LENGTH_256: EfuseField = EfuseField::new(EfuseBlock::Block0, 78, 1);
/// `[]` Represents whether RTC watchdog timeout threshold is selected at
/// startup. 1: selected. 0: not selected
pub const WDT_DELAY_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 80, 2);
/// `[]` Enables flash encryption when 1 or 3 bits are set and disables
/// otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
pub const SPI_BOOT_CRYPT_CNT: EfuseField = EfuseField::new(EfuseBlock::Block0, 82, 3);
/// `[]` Revoke 1st secure boot key
pub const SECURE_BOOT_KEY_REVOKE0: EfuseField = EfuseField::new(EfuseBlock::Block0, 85, 1);
/// `[]` Revoke 2nd secure boot key
pub const SECURE_BOOT_KEY_REVOKE1: EfuseField = EfuseField::new(EfuseBlock::Block0, 86, 1);
/// `[]` Revoke 3rd secure boot key
pub const SECURE_BOOT_KEY_REVOKE2: EfuseField = EfuseField::new(EfuseBlock::Block0, 87, 1);
/// `[KEY0_PURPOSE]` Represents the purpose of Key0
pub const KEY_PURPOSE_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 88, 4);
/// `[KEY1_PURPOSE]` Represents the purpose of Key1
pub const KEY_PURPOSE_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 92, 4);
/// `[KEY2_PURPOSE]` Represents the purpose of Key2
pub const KEY_PURPOSE_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 96, 4);
/// `[KEY3_PURPOSE]` Represents the purpose of Key3
pub const KEY_PURPOSE_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 100, 4);
/// `[KEY4_PURPOSE]` Represents the purpose of Key4
pub const KEY_PURPOSE_4: EfuseField = EfuseField::new(EfuseBlock::Block0, 104, 4);
/// `[KEY5_PURPOSE]` Represents the purpose of Key5
pub const KEY_PURPOSE_5: EfuseField = EfuseField::new(EfuseBlock::Block0, 108, 4);
/// `[]` Represents the spa secure level by configuring the clock random divide
/// mode
pub const SEC_DPA_LEVEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 112, 2);
/// `[]` Represents whether hardware random number k is forced used in ESDCA. 1:
/// force used. 0: not force used
pub const ECDSA_ENABLE_SOFT_K: EfuseField = EfuseField::new(EfuseBlock::Block0, 114, 1);
/// `[]` Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
pub const CRYPT_DPA_ENABLE: EfuseField = EfuseField::new(EfuseBlock::Block0, 115, 1);
/// `[]` Represents whether secure boot is enabled or disabled. 1: enabled. 0:
/// disabled
pub const SECURE_BOOT_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 116, 1);
/// `[]` Represents whether revoking aggressive secure boot is enabled or
/// disabled. 1: enabled. 0: disabled
pub const SECURE_BOOT_AGGRESSIVE_REVOKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 117, 1);
/// `[]` The type of interfaced flash. 0: four data lines; 1: eight data lines
pub const FLASH_TYPE: EfuseField = EfuseField::new(EfuseBlock::Block0, 119, 1);
/// `[]` Set flash page size
pub const FLASH_PAGE_SIZE: EfuseField = EfuseField::new(EfuseBlock::Block0, 120, 2);
/// `[]` Set this bit to enable ecc for flash boot
pub const FLASH_ECC_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 122, 1);
/// `[]` Set this bit to disable download via USB-OTG
pub const DIS_USB_OTG_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 123, 1);
/// `[]` Represents the flash waiting time after power-up; in unit of ms. When
/// the value less than 15; the waiting time is the programmed value. Otherwise;
/// the waiting time is 2 times the programmed value
pub const FLASH_TPUW: EfuseField = EfuseField::new(EfuseBlock::Block0, 124, 4);
/// `[]` Represents whether Download mode is disabled or enabled. 1: disabled.
/// 0: enabled
pub const DIS_DOWNLOAD_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 128, 1);
/// `[]` Represents whether direct boot mode is disabled or enabled. 1:
/// disabled. 0: enabled
pub const DIS_DIRECT_BOOT: EfuseField = EfuseField::new(EfuseBlock::Block0, 129, 1);
/// `[]` Represents whether print from USB-Serial-JTAG is disabled or enabled.
/// 1: disabled. 0: enabled
pub const DIS_USB_SERIAL_JTAG_ROM_PRINT: EfuseField = EfuseField::new(EfuseBlock::Block0, 130, 1);
/// `[]` TBD
pub const LOCK_KM_KEY: EfuseField = EfuseField::new(EfuseBlock::Block0, 131, 1);
/// `[]` Represents whether the USB-Serial-JTAG download function is disabled or
/// enabled. 1: disabled. 0: enabled
pub const DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: EfuseField =
EfuseField::new(EfuseBlock::Block0, 132, 1);
/// `[]` Represents whether security download is enabled or disabled. 1:
/// enabled. 0: disabled
pub const ENABLE_SECURITY_DOWNLOAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 133, 1);
/// `[]` Represents the type of UART printing. 00: force enable printing. 01:
/// enable printing when GPIO8 is reset at low level. 10: enable printing when
/// GPIO8 is reset at high level. 11: force disable printing
pub const UART_PRINT_CONTROL: EfuseField = EfuseField::new(EfuseBlock::Block0, 134, 2);
/// `[]` Represents whether ROM code is forced to send a resume command during
/// SPI boot. 1: forced. 0:not forced
pub const FORCE_SEND_RESUME: EfuseField = EfuseField::new(EfuseBlock::Block0, 136, 1);
/// `[]` Represents the version used by ESP-IDF anti-rollback feature
pub const SECURE_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block0, 137, 16);
/// `[]` Represents whether FAST VERIFY ON WAKE is disabled or enabled when
/// Secure Boot is enabled. 1: disabled. 0: enabled
pub const SECURE_BOOT_DISABLE_FAST_WAKE: EfuseField = EfuseField::new(EfuseBlock::Block0, 153, 1);
/// `[]` Represents whether the hysteresis function of corresponding PAD is
/// enabled. 1: enabled. 0:disabled
pub const HYS_EN_PAD: EfuseField = EfuseField::new(EfuseBlock::Block0, 154, 1);
/// `[]` Set the dcdc voltage default
pub const DCDC_VSET: EfuseField = EfuseField::new(EfuseBlock::Block0, 155, 5);
/// `[]` TBD
pub const PXA0_TIEH_SEL_0: EfuseField = EfuseField::new(EfuseBlock::Block0, 160, 2);
/// `[]` TBD
pub const PXA0_TIEH_SEL_1: EfuseField = EfuseField::new(EfuseBlock::Block0, 162, 2);
/// `[]` TBD
pub const PXA0_TIEH_SEL_2: EfuseField = EfuseField::new(EfuseBlock::Block0, 164, 2);
/// `[]` TBD
pub const PXA0_TIEH_SEL_3: EfuseField = EfuseField::new(EfuseBlock::Block0, 166, 2);
/// `[]` TBD
pub const KM_DISABLE_DEPLOY_MODE: EfuseField = EfuseField::new(EfuseBlock::Block0, 168, 4);
/// `[]` HP system power source select. 0:LDO. 1: DCDC
pub const HP_PWR_SRC_SEL: EfuseField = EfuseField::new(EfuseBlock::Block0, 178, 1);
/// `[]` Select dcdc vset use efuse_dcdc_vset
pub const DCDC_VSET_EN: EfuseField = EfuseField::new(EfuseBlock::Block0, 179, 1);
/// `[]` Set this bit to disable watch dog
pub const DIS_WDT: EfuseField = EfuseField::new(EfuseBlock::Block0, 180, 1);
/// `[]` Set this bit to disable super-watchdog
pub const DIS_SWD: EfuseField = EfuseField::new(EfuseBlock::Block0, 181, 1);
/// `[MAC_FACTORY]` MAC address
pub const MAC: EfuseField = EfuseField::new(EfuseBlock::Block1, 0, 48);
/// `[]` Minor chip version
pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 64, 4);
/// `[]` Major chip version
pub const WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 68, 2);
/// `[]` Disables check of wafer version major
pub const DISABLE_WAFER_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 70, 1);
/// `[]` Disables check of blk version major
pub const DISABLE_BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 71, 1);
/// `[]` BLK_VERSION_MINOR of BLOCK2
pub const BLK_VERSION_MINOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 72, 3);
/// `[]` BLK_VERSION_MAJOR of BLOCK2
pub const BLK_VERSION_MAJOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 75, 2);
/// `[]` Flash capacity
pub const FLASH_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 77, 3);
/// `[]` Flash temperature
pub const FLASH_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 80, 2);
/// `[]` Flash vendor
pub const FLASH_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 82, 3);
/// `[]` PSRAM capacity
pub const PSRAM_CAP: EfuseField = EfuseField::new(EfuseBlock::Block1, 85, 2);
/// `[]` PSRAM temperature
pub const PSRAM_TEMP: EfuseField = EfuseField::new(EfuseBlock::Block1, 87, 2);
/// `[]` PSRAM vendor
pub const PSRAM_VENDOR: EfuseField = EfuseField::new(EfuseBlock::Block1, 89, 2);
/// `[]` Package version
pub const PKG_VERSION: EfuseField = EfuseField::new(EfuseBlock::Block1, 91, 3);
/// `[]` Optional unique 128-bit ID
pub const OPTIONAL_UNIQUE_ID: EfuseField = EfuseField::new(EfuseBlock::Block2, 0, 128);
/// `[BLOCK_USR_DATA]` User data
pub const USER_DATA: EfuseField = EfuseField::new(EfuseBlock::Block3, 0, 256);
/// `[MAC_CUSTOM CUSTOM_MAC]` Custom MAC
pub const USER_DATA_MAC_CUSTOM: EfuseField = EfuseField::new(EfuseBlock::Block3, 200, 48);
/// `[BLOCK_KEY0]` Key0 or user data
pub const KEY0: EfuseField = EfuseField::new(EfuseBlock::Block4, 0, 256);
/// `[BLOCK_KEY1]` Key1 or user data
pub const KEY1: EfuseField = EfuseField::new(EfuseBlock::Block5, 0, 256);
/// `[BLOCK_KEY2]` Key2 or user data
pub const KEY2: EfuseField = EfuseField::new(EfuseBlock::Block6, 0, 256);
/// `[BLOCK_KEY3]` Key3 or user data
pub const KEY3: EfuseField = EfuseField::new(EfuseBlock::Block7, 0, 256);
/// `[BLOCK_KEY4]` Key4 or user data
pub const KEY4: EfuseField = EfuseField::new(EfuseBlock::Block8, 0, 256);
/// `[BLOCK_KEY5]` Key5 or user data
pub const KEY5: EfuseField = EfuseField::new(EfuseBlock::Block9, 0, 256);
/// `[BLOCK_SYS_DATA2]` System data part 2 (reserved)
pub const SYS_DATA_PART2: EfuseField = EfuseField::new(EfuseBlock::Block10, 0, 256);

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esp-hal/src/soc/esp32p4/efuse/mod.rs
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//! # Reading of eFuses (ESP32-P4)
pub use self::fields::*;
use crate::peripherals::EFUSE;
mod fields;
pub struct Efuse;
impl Efuse {
/// Reads chip's MAC address from the eFuse storage.
pub fn read_base_mac_address() -> [u8; 6] {
Self::read_field_be(MAC)
}
/// Get status of SPI boot encryption.
pub fn get_flash_encryption() -> bool {
(Self::read_field_le::<u8>(SPI_BOOT_CRYPT_CNT).count_ones() % 2) != 0
}
/// Get the multiplier for the timeout value of the RWDT STAGE 0 register.
pub fn get_rwdt_multiplier() -> u8 {
Self::read_field_le::<u8>(WDT_DELAY_SEL)
}
}
#[derive(Clone, Copy)]
pub(crate) enum EfuseBlock {
Block0,
Block1,
Block2,
Block3,
Block4,
Block5,
Block6,
Block7,
Block8,
Block9,
Block10,
}
impl EfuseBlock {
pub(crate) fn address(self) -> *const u32 {
use EfuseBlock::*;
let efuse = unsafe { &*EFUSE::PTR };
match self {
Block0 => efuse.rd_wr_dis().as_ptr(),
Block1 => efuse.rd_mac_sys_0().as_ptr(),
Block2 => efuse.rd_sys_part1_data0().as_ptr(),
Block3 => efuse.rd_usr_data0().as_ptr(),
Block4 => efuse.rd_key0_data0().as_ptr(),
Block5 => efuse.rd_key1_data0().as_ptr(),
Block6 => efuse.rd_key2_data0().as_ptr(),
Block7 => efuse.rd_key3_data0().as_ptr(),
Block8 => efuse.rd_key4_data0().as_ptr(),
Block9 => efuse.rd_key5_data0().as_ptr(),
Block10 => efuse.rd_sys_part2_data0().as_ptr(),
}
}
}

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esp-hal/src/soc/esp32p4/gpio.rs
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//! # GPIO configuration module (ESP32-P4)
//!
//! ## Overview
//!
//! The `GPIO` module provides functions and configurations for controlling the
//! `General Purpose Input/Output` pins on the `ESP32-P4` chip. It allows you to
//! configure pins as inputs or outputs, set their state and read their state.
//!
//! Let's get through the functionality and configurations provided by this GPIO
//! module:
//! - `get_io_mux_reg(gpio_num: u8) -> &'static
//! crate::peripherals::io_mux::GPIO0:`:
//! * Returns the IO_MUX register for the specified GPIO pin number.
//! - `gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8`:
//! * This function enables or disables GPIO interrupts and Non-Maskable
//! Interrupts (NMI). It takes two boolean arguments int_enable and
//! nmi_enable to control the interrupt and NMI enable settings. The
//! function returns an u8 value representing the interrupt enable
//! settings.
//! - `gpio` block:
//! * Defines the pin configurations for various GPIO pins. Each line
//! represents a pin and its associated options such as input/output
//! mode, analog capability, and corresponding functions.
//! - `analog` block:
//! * Block defines the analog capabilities of various GPIO pins. Each
//! line represents a pin and its associated options such as mux
//! selection, function selection, and input enable.
//! - `enum InputSignal`:
//! * This enumeration defines input signals for the GPIO mux. Each input
//! signal is assigned a specific value.
//! - `enum OutputSignal`:
//! * This enumeration defines output signals for the GPIO mux. Each
//! output signal is assigned a specific value.
//!
//! This module also implements the `InterruptStatusRegisterAccess` trait for
//! two different banks:
//! * `InterruptStatusRegisterAccessBank0`
//! * `InterruptStatusRegisterAccessBank1`.
//! This trait provides functions to read the interrupt status and NMI status
//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
//! `gpio` peripheral to access the appropriate registers.
use crate::{
gpio::{
AlternateFunction,
GpioPin,
InterruptStatusRegisterAccess,
InterruptStatusRegisterAccessBank0,
InterruptStatusRegisterAccessBank1,
Unknown,
},
peripherals::GPIO,
};
pub const NUM_PINS: usize = 55;
pub(crate) const FUNC_IN_SEL_OFFSET: usize = 1;
pub type OutputSignalType = u16;
pub const OUTPUT_SIGNAL_MAX: u16 = 256;
pub const INPUT_SIGNAL_MAX: u16 = 203;
pub const ONE_INPUT: u8 = 0x3f;
pub const ZERO_INPUT: u8 = 0x3e;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }
}
pub(crate) fn gpio_intr_enable(int_enable: bool, _nmi_enable: bool) -> u8 {
// there is no nmi_enable
int_enable as u8
}
/// Peripheral input signals for the GPIO mux
#[allow(non_camel_case_types)]
#[derive(PartialEq, Copy, Clone)]
pub enum InputSignal {
SD_CARD_CCMD_2_PAD = 1,
SD_CARD_CDATA0_2_PAD = 2,
SD_CARD_CDATA1_2_PAD = 3,
SD_CARD_CDATA2_2_PAD = 4,
SD_CARD_CDATA3_2_PAD = 5,
SD_CARD_CDATA4_2_PAD = 6,
SD_CARD_CDATA5_2_PAD = 7,
SD_CARD_CDATA6_2_PAD = 8,
SD_CARD_CDATA7_2_PAD = 9,
UART0_RXD_PAD = 10,
UART0_CTS_PAD = 11,
UART0_DSR_PAD = 12,
UART1_RXD_PAD = 13,
UART1_CTS_PAD = 14,
UART1_DSR_PAD = 15,
UART2_RXD_PAD = 16,
UART2_CTS_PAD = 17,
UART2_DSR_PAD = 18,
UART3_RXD_PAD = 19,
UART3_CTS_PAD = 20,
UART3_DSR_PAD = 21,
UART4_RXD_PAD = 22,
UART4_CTS_PAD = 23,
UART4_DSR_PAD = 24,
I2S0_O_BCK_PAD = 25,
I2S0_MCLK_PAD = 26,
I2S0_O_WS_PAD = 27,
I2S0_I_SD_PAD = 28,
I2S0_I_BCK_PAD = 29,
I2S0_I_WS_PAD = 30,
I2S1_O_BCK_PAD = 31,
I2S1_MCLK_PAD = 32,
I2S1_O_WS_PAD = 33,
I2S1_I_SD_PAD = 34,
I2S1_I_BCK_PAD = 35,
I2S1_I_WS_PAD = 36,
I2S2_O_BCK_PAD = 37,
I2S2_MCLK_PAD = 38,
I2S2_O_WS_PAD = 39,
I2S2_I_SD_PAD = 40,
I2S2_I_BCK_PAD = 41,
I2S2_I_WS_PAD = 42,
I2S0_I_SD1_PAD = 43,
I2S0_I_SD2_PAD = 44,
I2S0_I_SD3_PAD = 45,
SPI3_CK_PAD = 47,
SPI3_Q_PAD = 48,
SPI3_D_PAD = 49,
SPI3_HOLD_PAD = 50,
SPI3_WP_PAD = 51,
SPI3_CS_PAD = 52,
SPI2_CK_PAD = 53,
SPI2_Q_PAD = 54,
SPI2_D_PAD = 55,
SPI2_HOLD_PAD = 56,
SPI2_WP_PAD = 57,
SPI2_IO4_PAD = 58,
SPI2_IO5_PAD = 59,
SPI2_IO6_PAD = 60,
SPI2_IO7_PAD = 61,
SPI2_CS_PAD = 62,
I2C0_SCL_PAD = 68,
I2C0_SDA_PAD = 69,
I2C1_SCL_PAD = 70,
I2C1_SDA_PAD = 71,
UART0_SLP_CLK_PAD = 74,
UART1_SLP_CLK_PAD = 75,
UART2_SLP_CLK_PAD = 76,
UART3_SLP_CLK_PAD = 77,
UART4_SLP_CLK_PAD = 78,
TWAI0_RX_PAD = 80,
TWAI1_RX_PAD = 83,
TWAI2_RX_PAD = 86,
PWM0_SYNC0_PAD = 89,
PWM0_SYNC1_PAD = 90,
PWM0_SYNC2_PAD = 91,
PWM0_F0_PAD = 92,
PWM0_F1_PAD = 93,
PWM0_F2_PAD = 94,
PWM0_CAP0_PAD = 95,
PWM0_CAP1_PAD = 96,
PWM0_CAP2_PAD = 97,
PWM1_SYNC0_PAD = 98,
PWM1_SYNC1_PAD = 99,
PWM1_SYNC2_PAD = 100,
PWM1_F0_PAD = 101,
PWM1_F1_PAD = 102,
PWM1_F2_PAD = 103,
PWM1_CAP0_PAD = 104,
PWM1_CAP1_PAD = 105,
PWM1_CAP2_PAD = 106,
GMII_MDI_PAD = 107,
GMAC_PHY_COL_PAD = 108,
GMAC_PHY_CRS_PAD = 109,
USB_OTG11_IDDIG_PAD = 110,
USB_OTG11_AVALID_PAD = 111,
USB_SRP_BVALID_PAD = 112,
USB_OTG11_VBUSVALID_PAD = 113,
USB_SRP_SESSEND_PAD = 114,
ULPI_CLK_PAD = 117,
USB_HSPHY_REFCLK = 118,
SD_CARD_DETECT_N_1_PAD = 126,
SD_CARD_DETECT_N_2_PAD = 127,
SD_CARD_INT_N_1_PAD = 128,
SD_CARD_INT_N_2_PAD = 129,
SD_CARD_WRITE_PRT_1_PAD = 130,
SD_CARD_WRITE_PRT_2_PAD = 131,
SD_DATA_STROBE_1_PAD = 132,
SD_DATA_STROBE_2_PAD = 133,
I3C_MST_SCL_PAD = 134,
I3C_MST_SDA_PAD = 135,
I3C_SLV_SCL_PAD = 136,
I3C_SLV_SDA_PAD = 137,
ADP_PRB_PAD = 138,
ADP_SNS_PAD = 139,
USB_JTAG_TDO_BRIDGE_PAD = 140,
CAM_PCLK_PAD = 158,
CAM_H_ENABLE_PAD = 159,
CAM_H_SYNC_PAD = 160,
CAM_V_SYNC_PAD = 161,
GMAC_PHY_RXDV_PAD = 178,
GMAC_PHY_RXD0_PAD = 179,
GMAC_PHY_RXD1_PAD = 180,
GMAC_PHY_RXD2_PAD = 181,
GMAC_PHY_RXD3_PAD = 182,
GMAC_PHY_RXER_PAD = 183,
GMAC_RX_CLK_PAD = 184,
GMAC_TX_CLK_PAD = 185,
PARLIO_RX_CLK_PAD = 186,
PARLIO_TX_CLK_PAD = 187,
PARLIO_RX_DATA0_PAD = 188,
PARLIO_RX_DATA1_PAD = 189,
PARLIO_RX_DATA2_PAD = 190,
PARLIO_RX_DATA3_PAD = 191,
PARLIO_RX_DATA4_PAD = 192,
PARLIO_RX_DATA5_PAD = 193,
PARLIO_RX_DATA6_PAD = 194,
PARLIO_RX_DATA7_PAD = 195,
PARLIO_RX_DATA8_PAD = 196,
PARLIO_RX_DATA9_PAD = 197,
PARLIO_RX_DATA10_PAD = 198,
PARLIO_RX_DATA11_PAD = 199,
PARLIO_RX_DATA12_PAD = 200,
PARLIO_RX_DATA13_PAD = 201,
PARLIO_RX_DATA14_PAD = 202,
PARLIO_RX_DATA15_PAD = 203,
}
/// Peripheral output signals for the GPIO mux
#[allow(non_camel_case_types)]
#[derive(PartialEq, Copy, Clone)]
pub enum OutputSignal {
SD_CARD_CCLK_2_PAD = 0,
SD_CARD_CCMD_2_PAD = 1,
SD_CARD_CDATA0_2_PAD = 2,
SD_CARD_CDATA1_2_PAD = 3,
SD_CARD_CDATA2_2_PAD = 4,
SD_CARD_CDATA3_2_PAD = 5,
SD_CARD_CDATA4_2_PAD = 6,
SD_CARD_CDATA5_2_PAD = 7,
SD_CARD_CDATA6_2_PAD = 8,
SD_CARD_CDATA7_2_PAD = 9,
UART0_TXD_PAD = 10,
UART0_RTS_PAD = 11,
UART0_DTR_PAD = 12,
UART1_TXD_PAD = 13,
UART1_RTS_PAD = 14,
UART1_DTR_PAD = 15,
UART2_TXD_PAD = 16,
UART2_RTS_PAD = 17,
UART2_DTR_PAD = 18,
UART3_TXD_PAD = 19,
UART3_RTS_PAD = 20,
UART3_DTR_PAD = 21,
UART4_TXD_PAD = 22,
UART4_RTS_PAD = 23,
UART4_DTR_PAD = 24,
I2S0_O_BCK_PAD = 25,
I2S0_MCLK_PAD = 26,
I2S0_O_WS_PAD = 27,
I2S0_O_SD_PAD = 28,
I2S0_I_BCK_PAD = 29,
I2S0_I_WS_PAD = 30,
I2S1_O_BCK_PAD = 31,
I2S1_MCLK_PAD = 32,
I2S1_O_WS_PAD = 33,
I2S1_O_SD_PAD = 34,
I2S1_I_BCK_PAD = 35,
I2S1_I_WS_PAD = 36,
I2S2_O_BCK_PAD = 37,
I2S2_MCLK_PAD = 38,
I2S2_O_WS_PAD = 39,
I2S2_O_SD_PAD = 40,
I2S2_I_BCK_PAD = 41,
I2S2_I_WS_PAD = 42,
I2S0_O_SD1_PAD = 43,
SPI2_DQS_PAD = 44,
SPI3_CS2_PAD = 45,
SPI3_CS1_PAD = 46,
SPI3_CK_PAD = 47,
SPI3_QO_PAD = 48,
SPI3_D_PAD = 49,
SPI3_HOLD_PAD = 50,
SPI3_WP_PAD = 51,
SPI3_CS_PAD = 52,
SPI2_CK_PAD = 53,
SPI2_Q_PAD = 54,
SPI2_D_PAD = 55,
SPI2_HOLD_PAD = 56,
SPI2_WP_PAD = 57,
SPI2_IO4_PAD = 58,
SPI2_IO5_PAD = 59,
SPI2_IO6_PAD = 60,
SPI2_IO7_PAD = 61,
SPI2_CS_PAD = 62,
SPI2_CS1_PAD = 63,
SPI2_CS2_PAD = 64,
SPI2_CS3_PAD = 65,
SPI2_CS4_PAD = 66,
SPI2_CS5_PAD = 67,
I2C0_SCL_PAD = 68,
I2C0_SDA_PAD = 69,
I2C1_SCL_PAD = 70,
I2C1_SDA_PAD = 71,
GPIO_SD0 = 72,
GPIO_SD1 = 73,
GPIO_SD2 = 74,
GPIO_SD3 = 75,
GPIO_SD4 = 76,
GPIO_SD5 = 77,
GPIO_SD6 = 78,
GPIO_SD7 = 79,
TWAI0_TX_PAD = 80,
TWAI0_BUS_OFF_ON_PAD = 81,
TWAI0_CLKOUT_PAD = 82,
TWAI1_TX_PAD = 83,
TWAI1_BUS_OFF_ON_PAD = 84,
TWAI1_CLKOUT_PAD = 85,
TWAI2_TX_PAD = 86,
TWAI2_BUS_OFF_ON_PAD = 87,
TWAI2_CLKOUT_PAD = 88,
PWM0_CH0_A_PAD = 89,
PWM0_CH0_B_PAD = 90,
PWM0_CH1_A_PAD = 91,
PWM0_CH1_B_PAD = 92,
PWM0_CH2_A_PAD = 93,
PWM0_CH2_B_PAD = 94,
PWM1_CH0_A_PAD = 95,
PWM1_CH0_B_PAD = 96,
PWM1_CH1_A_PAD = 97,
PWM1_CH1_B_PAD = 98,
PWM1_CH2_A_PAD = 99,
PWM1_CH2_B_PAD = 100,
ADP_CHRG_PAD = 101,
ADP_DISCHRG_PAD = 102,
ADP_PRB_EN_PAD = 103,
ADP_SNS_EN_PAD = 104,
TWAI0_STANDBY_PAD = 105,
TWAI1_STANDBY_PAD = 106,
TWAI2_STANDBY_PAD = 107,
GMII_MDC_PAD = 108,
GMII_MDO_PAD = 109,
USB_SRP_DISCHRGVBUS_PAD = 110,
USB_OTG11_IDPULLUP_PAD = 111,
USB_OTG11_DPPULLDOWN_PAD = 112,
USB_OTG11_DMPULLDOWN_PAD = 113,
USB_OTG11_DRVVBUS_PAD = 114,
USB_SRP_CHRGVBUS_PAD = 115,
OTG_DRVVBUS_PAD = 116,
RNG_CHAIN_CLK_PAD = 117,
I3C_MST_SCL_PAD = 134,
I3C_MST_SDA_PAD = 135,
I3C_SLV_SCL_PAD = 136,
I3C_SLV_SDA_PAD = 137,
I3C_MST_SCL_PULLUP_EN_PAD = 138,
I3C_MST_SDA_PULLUP_EN_PAD = 139,
USB_JTAG_TDI_BRIDGE_PAD = 140,
USB_JTAG_TMS_BRIDGE_PAD = 141,
USB_JTAG_TCK_BRIDGE_PAD = 142,
USB_JTAG_TRST_BRIDGE_PAD = 143,
LCD_CS_PAD = 144,
LCD_DC_PAD = 145,
SD_RST_N_1_PAD = 146,
SD_RST_N_2_PAD = 147,
SD_CCMD_OD_PULLUP_EN_N_PAD = 148,
LCD_PCLK_PAD = 149,
CAM_CLK_PAD = 150,
LCD_H_ENABLE_PAD = 151,
LCD_H_SYNC_PAD = 152,
LCD_V_SYNC_PAD = 153,
GMAC_PHY_TXEN_PAD = 178,
GMAC_PHY_TXD0_PAD = 179,
GMAC_PHY_TXD1_PAD = 180,
GMAC_PHY_TXD2_PAD = 181,
GMAC_PHY_TXD3_PAD = 182,
GMAC_PHY_TXER_PAD = 183,
PARLIO_RX_CLK_PAD = 186,
PARLIO_TX_CLK_PAD = 187,
PARLIO_TX_DATA0_PAD = 188,
PARLIO_TX_DATA1_PAD = 189,
PARLIO_TX_DATA2_PAD = 190,
PARLIO_TX_DATA3_PAD = 191,
PARLIO_TX_DATA4_PAD = 192,
PARLIO_TX_DATA5_PAD = 193,
PARLIO_TX_DATA6_PAD = 194,
PARLIO_TX_DATA7_PAD = 195,
PARLIO_TX_DATA8_PAD = 196,
PARLIO_TX_DATA9_PAD = 197,
PARLIO_TX_DATA10_PAD = 198,
PARLIO_TX_DATA11_PAD = 199,
PARLIO_TX_DATA12_PAD = 200,
PARLIO_TX_DATA13_PAD = 201,
PARLIO_TX_DATA14_PAD = 202,
PARLIO_TX_DATA15_PAD = 203,
CONSTANT0_PAD = 212,
CONSTANT1_PAD = 213,
GPIO = 256,
}
crate::gpio::gpio! {
(0, 0, InputOutput)
(1, 0, InputOutput)
(2, 0, InputOutput)
(3, 0, InputOutput)
(4, 0, InputOutput)
(5, 0, InputOutput)
(6, 0, InputOutput (3 => SPI2_HOLD_PAD) (3 => SPI2_HOLD_PAD))
(7, 0, InputOutput (3 => SPI2_CS_PAD) (3 => SPI2_CS_PAD))
(8, 0, InputOutput (3 => SPI2_D_PAD) (2 => UART0_RTS_PAD 3 => SPI2_D_PAD))
(9, 0, InputOutput (2 => UART0_CTS_PAD) (3 => SPI2_CK_PAD))
(10, 0, InputOutput (3 => SPI2_Q_PAD) (2 => UART1_TXD_PAD))
(11, 0, InputOutput (2 => UART1_RXD_PAD 3 => SPI2_WP_PAD) (3 => SPI2_WP_PAD))
(12, 0, InputOutput () (2 => UART1_RTS_PAD))
(13, 0, InputOutput (2 => UART1_CTS_PAD) ())
(14, 0, InputOutput)
(15, 0, InputOutput)
(16, 0, InputOutput)
(17, 0, InputOutput)
(18, 0, InputOutput)
(19, 0, InputOutput)
(20, 0, InputOutput)
(21, 0, InputOutput)
(22, 0, InputOutput)
(23, 0, InputOutput)
(24, 0, InputOutput)
(25, 0, InputOutput)
(26, 0, InputOutput)
(27, 0, InputOutput)
(28, 0, InputOutput (2 => SPI2_CS_PAD 3 => GMAC_PHY_RXDV_PAD) ())
(29, 0, InputOutput (2 => SPI2_D_PAD 3 => GMAC_PHY_RXD0_PAD) ())
(30, 0, InputOutput (3 => GMAC_PHY_RXD1_PAD) (2 => SPI2_CK_PAD))
(31, 0, InputOutput (2 => SPI2_Q_PAD 3 => GMAC_PHY_RXER_PAD) ())
(32, 1, InputOutput (2 => SPI2_HOLD_PAD 3 => GMAC_RX_CLK_PAD) (2 => SPI2_HOLD_PAD))
(33, 1, InputOutput (2 => SPI2_WP_PAD) (2 => SPI2_WP_PAD 3 => GMAC_PHY_TXEN_PAD))
(34, 1, InputOutput (2 => SPI2_IO4_PAD) (2 => SPI2_IO4_PAD 3 => GMAC_PHY_TXD0_PAD))
(35, 1, InputOutput (2 => SPI2_IO5_PAD) (2 => SPI2_IO5_PAD 3 => GMAC_PHY_TXD1_PAD))
(36, 1, InputOutput (2 => SPI2_IO6_PAD) (2 => SPI2_IO6_PAD 3 => GMAC_PHY_TXER_PAD))
(37, 1, InputOutput (2 => SPI2_IO7_PAD) (2 => SPI2_IO7_PAD))
(38, 1, InputOutput (2 => SPI2_Q_PAD) (2 => SPI2_Q_PAD))
(39, 1, InputOutput)
(40, 1, InputOutput () (3 => GMAC_PHY_TXEN_PAD))
(41, 1, InputOutput () (3 => GMAC_PHY_TXD0_PAD))
(42, 1, InputOutput () (3 => GMAC_PHY_TXD1_PAD))
(43, 1, InputOutput () (3 => GMAC_PHY_TXER_PAD))
(44, 1, InputOutput (3 => GMAC_RX_CLK_PAD) ())
(45, 1, InputOutput (3 => GMAC_PHY_RXDV_PAD) ())
(46, 1, InputOutput (3 => GMAC_PHY_RXD0_PAD) ())
(47, 1, InputOutput (3 => GMAC_PHY_RXD1_PAD) ())
(48, 1, InputOutput (3 => GMAC_PHY_RXER_PAD) ())
(49, 1, InputOutput () (3 => GMAC_PHY_TXEN_PAD))
(50, 1, InputOutput (3 => GMAC_RX_CLK_PAD) ())
(51, 1, InputOutput (3 => GMAC_PHY_RXDV_PAD) ())
(52, 1, InputOutput (3 => GMAC_PHY_RXD0_PAD) ())
(53, 1, InputOutput (3 => GMAC_PHY_RXD1_PAD) ())
(54, 1, InputOutput (3 => GMAC_PHY_RXER_PAD) ())
}
// crate::gpio::analog! {
// }
// crate::gpio::lp_io::lp_gpio! {
// 0
// 1
// 2
// 3
// 4
// 5
// 6
// 7
// 9
// 10
// 11
// 12
// 13
// 13
// 15
// }
// ESP32-P4 supports four interrupts for GPIO - for now just using INTR_0
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank0 {
fn pro_cpu_interrupt_status_read() -> u32 {
unsafe { &*GPIO::PTR }.intr_0().read().bits()
}
fn pro_cpu_nmi_status_read() -> u32 {
unsafe { &*GPIO::PTR }.intr_0().read().bits()
}
}
impl InterruptStatusRegisterAccess for InterruptStatusRegisterAccessBank1 {
fn pro_cpu_interrupt_status_read() -> u32 {
unsafe { &*GPIO::PTR }.intr1_0().read().bits()
}
fn pro_cpu_nmi_status_read() -> u32 {
unsafe { &*GPIO::PTR }.intr1_0().read().bits()
}
}
// TODO USB pins
// implement marker traits on USB pins

18
esp-hal/src/soc/esp32p4/mod.rs
View File

@ -1,18 +0,0 @@
pub mod efuse;
pub mod gpio;
pub mod peripherals;
pub(crate) mod registers {
pub const INTERRUPT_MAP_BASE: u32 = 0x500D_6000;
pub const INTERRUPT_MAP_BASE_APP_CPU: u32 = 0x500D_6800;
}
pub(crate) mod constants {
pub const SOC_DRAM_LOW: u32 = 0x4FF0_0000;
pub const SOC_DRAM_HIGH: u32 = 0x4FFC_0000;
}
#[export_name = "__post_init"]
unsafe fn post_init() {
// TODO: Disable watchdog timers
}

107
esp-hal/src/soc/esp32p4/peripherals.rs
View File

@ -1,107 +0,0 @@
//! # Peripheral Instances
//!
//! This module creates singleton instances for each of the various peripherals,
//! and re-exports them to allow users to access and use them in their
//! applications.
//!
//! Should be noted that that the module also re-exports the [Interrupt] enum
//! from the PAC, allowing users to handle interrupts associated with these
//! peripherals.
use esp32p4 as pac;
// We need to export this for users to use
pub use pac::Interrupt;
// We need to export this in the hal for the drivers to use
pub(crate) use self::peripherals::*;
// Note that certain are marked with `virtual` in the invocation of the
// `peripherals!` macro below. Basically, this indicates there's no physical
// peripheral (no `PSRAM`, `RADIO`, etc. peripheral in the PACs), so we're
// creating "virtual peripherals" for them.
crate::peripherals! {
ADC <= ADC,
AES <= AES,
ASSIST_DEBUG <= ASSIST_DEBUG,
AXI_DMA <= AXI_DMA,
AXI_ICM <= AXI_ICM,
BITSCRAMBLER <= BITSCRAMBLER,
CACHE <= CACHE,
DMA <= DMA,
DS <= DS,
ECC <= ECC,
ECDSA <= ECDSA,
EFUSE <= EFUSE,
GPIO <= GPIO (GPIO,GPIO_INT1,GPIO_INT2,GPIO_INT3),
GPIO_SD <= GPIO_SD,
H264 <= H264,
H264_DMA <= H264_DMA,
HMAC <= HMAC,
HP_SYS_CLKRST <= HP_SYS_CLKRST,
I2C0 <= I2C0,
I2C1 <= I2C1,
I2S0 <= I2S0,
I2S1 <= I2S1,
I2S2 <= I2S2,
I3C_MST <= I3C_MST,
I3C_MST_MEM <= I3C_MST_MEM,
I3C_SLV <= I3C_SLV,
INTERRUPT_CORE0 <= INTERRUPT_CORE0,
INTERRUPT_CORE1 <= INTERRUPT_CORE1,
IO_MUX <= IO_MUX,
ISP <= ISP,
JPEG <= JPEG,
LCD_CAM <= LCD_CAM,
LEDC <= LEDC,
LP_ADC <= LP_ADC,
LP_ANA <= LP_ANA,
LP_AON_CLKRST <= LP_AON_CLKRST,
LP_GPIO <= LP_GPIO,
LP_HUK <= LP_HUK,
LP_I2C_ANA_MST <= LP_I2C_ANA_MST,
LP_I2C0 <= LP_I2C0,
LP_I2S0 <= LP_I2S0,
LP_INTR <= LP_INTR,
LP_IO_MUX <= LP_IO_MUX,
LP_PERI <= LP_PERI,
LP_SYS <= LP_SYS,
LP_TIMER <= LP_TIMER,
LP_TOUCH <= LP_TOUCH,
LP_TSENS <= LP_TSENS,
LP_UART <= LP_UART,
LP_WDT <= LP_WDT,
MCPWM0 <= MCPWM0,
MCPWM1 <= MCPWM1,
MIPI_CSI_BRIDGE <= MIPI_CSI_BRIDGE,
MIPI_CSI_HOST <= MIPI_CSI_HOST,
MIPI_DSI_BRIDGE <= MIPI_DSI_BRIDGE,
MIPI_DSI_HOST <= MIPI_DSI_HOST,
PARL_IO <= PARL_IO,
PAU <= PAU,
PCNT <= PCNT,
PMU <= PMU,
PPA <= PPA,
PVT <= PVT,
RMT <= RMT,
RSA <= RSA,
SDHOST <= SDHOST,
SHA <= SHA,
SOC_ETM <= SOC_ETM,
SPI0 <= SPI0,
SPI1 <= SPI1,
SPI2 <= SPI2,
SPI3 <= SPI3,
SYSTEM <= HP_SYS,
SYSTIMER <= SYSTIMER,
TIMG0 <= TIMG0,
TIMG1 <= TIMG1,
TRACE0 <= TRACE0,
TRACE1 <= TRACE1,
TWAI0 <= TWAI0,
TWAI1 <= TWAI1,
TWAI2 <= TWAI2,
UART0 <= UART0,
UHCI0 <= UHCI0,
USB_DEVICE <= USB_DEVICE,
USB_WRAP <= USB_WRAP,
}

1
esp-hal/src/soc/mod.rs
View File

@ -7,7 +7,6 @@ pub use self::implementation::*;
#[cfg_attr(esp32c3, path = "esp32c3/mod.rs")]
#[cfg_attr(esp32c6, path = "esp32c6/mod.rs")]
#[cfg_attr(esp32h2, path = "esp32h2/mod.rs")]
#[cfg_attr(esp32p4, path = "esp32p4/mod.rs")]
#[cfg_attr(esp32s2, path = "esp32s2/mod.rs")]
#[cfg_attr(esp32s3, path = "esp32s3/mod.rs")]
mod implementation;

14
esp-hal/src/system.rs
View File

@ -105,8 +105,6 @@ pub struct SoftwareInterrupt<const NUM: u8> {}
impl<const NUM: u8> SoftwareInterrupt<NUM> {
/// Sets the interrupt handler for this software-interrupt
// TODO interrupts missing in PAC or named wrong for P4
#[cfg(not(esp32p4))]
pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
let interrupt = match NUM {
0 => crate::peripherals::Interrupt::FROM_CPU_INTR0,
@ -241,7 +239,7 @@ impl SoftwareInterruptControl {
/// Controls the enablement of peripheral clocks.
pub(crate) struct PeripheralClockControl;
#[cfg(not(any(esp32c6, esp32h2, esp32p4)))]
#[cfg(not(any(esp32c6, esp32h2)))]
impl PeripheralClockControl {
/// Enables and resets the given peripheral
pub(crate) fn enable(peripheral: Peripheral) {
@ -256,7 +254,7 @@ impl PeripheralClockControl {
&system.peri_rst_en(),
)
};
#[cfg(not(any(esp32, esp32p4)))]
#[cfg(not(esp32))]
let (perip_clk_en0, perip_rst_en0) = { (&system.perip_clk_en0(), &system.perip_rst_en0()) };
#[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))]
@ -465,7 +463,7 @@ impl PeripheralClockControl {
#[cfg(esp32)]
let (perip_rst_en0, peri_rst_en) = { (&system.perip_rst_en(), &system.peri_rst_en()) };
#[cfg(not(any(esp32, esp32p4)))]
#[cfg(not(esp32))]
let perip_rst_en0 = { &system.perip_rst_en0() };
#[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))]
@ -1074,12 +1072,6 @@ impl PeripheralClockControl {
}
}
#[cfg(esp32p4)]
impl PeripheralClockControl {
/// Enables and resets the given peripheral
pub(crate) fn enable(_peripheral: Peripheral) {}
}
/// Controls the configuration of the chip's clocks.
pub struct SystemClockControl {
_private: (),

1
examples/.cargo/config.toml
View File

@ -4,7 +4,6 @@ esp32c2 = "run --release --features=esp32c2 --target=riscv32imc-unknown-none-elf
esp32c3 = "run --release --features=esp32c3 --target=riscv32imc-unknown-none-elf"
esp32c6 = "run --release --features=esp32c6 --target=riscv32imac-unknown-none-elf"
esp32h2 = "run --release --features=esp32h2 --target=riscv32imac-unknown-none-elf"
esp32p4 = "run --release --features=esp32p4 --target=riscv32imafc-unknown-none-elf"
esp32s2 = "run --release --features=esp32s2 --target=xtensa-esp32s2-none-elf"
esp32s3 = "run --release --features=esp32s3 --target=xtensa-esp32s3-none-elf"

1
examples/Cargo.toml
View File

@ -50,7 +50,6 @@ esp32c2 = ["esp-hal/esp32c2", "esp-backtrace/esp32c2", "esp-println/esp32c2"]
esp32c3 = ["esp-hal/esp32c3", "esp-backtrace/esp32c3", "esp-println/esp32c3", "esp-hal-smartled/esp32c3"]
esp32c6 = ["esp-hal/esp32c6", "esp-backtrace/esp32c6", "esp-println/esp32c6", "esp-hal-smartled/esp32c6"]
esp32h2 = ["esp-hal/esp32h2", "esp-backtrace/esp32h2", "esp-println/esp32h2", "esp-hal-smartled/esp32h2"]
esp32p4 = ["esp-hal/esp32p4", "esp-backtrace/esp32p4", "esp-println/esp32p4"]
esp32s2 = ["esp-hal/esp32s2", "esp-backtrace/esp32s2", "esp-println/esp32s2", "esp-hal-smartled/esp32s2"]
esp32s3 = ["esp-hal/esp32s3", "esp-backtrace/esp32s3", "esp-println/esp32s3", "esp-hal-smartled/esp32s3"]

1
examples/src/lib.rs
View File

@ -1,6 +1,5 @@
#![no_std]
#[cfg(not(feature = "esp32p4"))] // TODO: Remove me
pub fn cycles() -> u64 {
#[cfg(feature = "esp32")]
{

5
xtask/src/lib.rs
View File

@ -34,7 +34,6 @@ pub enum Chip {
Esp32c3,
Esp32c6,
Esp32h2,
Esp32p4,
Esp32s2,
Esp32s3,
}
@ -47,7 +46,6 @@ impl Chip {
Esp32 => "xtensa-esp32-none-elf",
Esp32c2 | Esp32c3 => "riscv32imc-unknown-none-elf",
Esp32c6 | Esp32h2 => "riscv32imac-unknown-none-elf",
Esp32p4 => "riscv32imafc-unknown-none-elf",
Esp32s2 => "xtensa-esp32s2-none-elf",
Esp32s3 => "xtensa-esp32s3-none-elf",
}
@ -56,7 +54,7 @@ impl Chip {
pub fn has_lp_core(&self) -> bool {
use Chip::*;
matches!(self, Esp32c6 | Esp32p4 | Esp32s2 | Esp32s3)
matches!(self, Esp32c6 | Esp32s2 | Esp32s3)
}
pub fn lp_target(&self) -> Result<&str> {
@ -76,7 +74,6 @@ impl Chip {
Chip::Esp32c3 => "ESP32-C3",
Chip::Esp32c6 => "ESP32-C6",
Chip::Esp32h2 => "ESP32-H2",
Chip::Esp32p4 => "ESP32-P4",
Chip::Esp32s2 => "ESP32-S2",
Chip::Esp32s3 => "ESP32-S3",
}