use riscv 0.14.0 (#3842)

* use riscv 0.14.0

* Don't use the re-exports from esp-riscv-rt because of the RT feature

* fmt

* More fixes caused by the existence of the `rt` feature

esp-hal/Cargo.toml

@@ -82,7 +82,7 @@ esp32s2 = { version = "0.29.0", features = ["critical-section", "rt"], optional
 esp32s3 = { version = "0.33.0", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "7232b3e" }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
-riscv            = { version = "0.12.1" }
+riscv            = { version = "0.14.0", optional = true }
 esp-riscv-rt     = { version = "0.12.0", path = "../esp-riscv-rt", optional = true }
 
 [target.'cfg(target_arch = "xtensa")'.dependencies]
@@ -127,6 +127,7 @@ esp32   = [
 # Target the ESP32-C2.
 esp32c2 = [
     "dep:esp32c2",
+    "dep:riscv",
     "portable-atomic/unsafe-assume-single-core",
     "esp-rom-sys/esp32c2",
     "esp-metadata-generated/esp32c2",
@@ -134,6 +135,7 @@ esp32c2 = [
 # Target the ESP32-C3.
 esp32c3 = [
     "dep:esp32c3",
+    "dep:riscv",
     "esp-riscv-rt/rtc-ram",
     "portable-atomic/unsafe-assume-single-core",
     "esp-rom-sys/esp32c3",
@@ -142,7 +144,9 @@ esp32c3 = [
 # Target the ESP32-C6.
 esp32c6 = [
     "dep:esp32c6",
+    "dep:riscv",
     "esp-riscv-rt/rtc-ram",
+    "esp-riscv-rt/has-mie-mip",
     "procmacros/has-lp-core",
     "esp-rom-sys/esp32c6",
     "esp-metadata-generated/esp32c6",
@@ -150,7 +154,9 @@ esp32c6 = [
 # Target the ESP32-H2.
 esp32h2 = [
     "dep:esp32h2",
+    "dep:riscv",
     "esp-riscv-rt/rtc-ram",
+    "esp-riscv-rt/has-mie-mip",
     "esp-rom-sys/esp32h2",
     "esp-metadata-generated/esp32h2",
 ]

esp-hal/src/interrupt/riscv.rs

@@ -818,7 +818,12 @@ mod rt {
 
         unsafe {
             let vec_table = (&_vector_table as *const u32).addr();
-            mtvec::write(vec_table, mtvec::TrapMode::Vectored);
+            mtvec::write({
+                let mut mtvec = mtvec::Mtvec::from_bits(0);
+                mtvec.set_trap_mode(mtvec::TrapMode::Vectored);
+                mtvec.set_address(vec_table);
+                mtvec
+            });
 
             crate::interrupt::init_vectoring();
         };

esp-riscv-rt/Cargo.toml

@@ -17,11 +17,11 @@ test  = false
 
 [dependencies]
 document-features = "0.2.11"
-riscv             = "0.12.1"
+riscv             = "0.14.0"
-riscv-rt-macros   = "0.4.0"
+riscv-rt-macros   = "0.5.0"
 
 [features]
-## Indicate that the device supports `mie` and `mip` instructions.
+## Indicate that the device supports `mie` and `mip` CSRs.
 has-mie-mip = []
 ## Indicate that the device has RTC RAM.
 rtc-ram = []

esp-riscv-rt/src/lib.rs

@@ -16,10 +16,7 @@
 use core::arch::global_asm;
 
 pub use riscv;
-use riscv::register::{
+use riscv::register::{mcause, mtvec};
-    mcause,
-    mtvec::{self, TrapMode},
-};
 pub use riscv_rt_macros::{entry, pre_init};
 
 pub use self::Interrupt as interrupt;
@@ -297,7 +294,14 @@ pub unsafe extern "Rust" fn default_setup_interrupts() { unsafe {
         fn _start_trap();
     }
 
-    mtvec::write(_start_trap as usize, TrapMode::Direct);
+    mtvec::write(
+        {
+            let mut mtvec = mtvec::Mtvec::from_bits(0);
+            mtvec.set_trap_mode(mtvec::TrapMode::Vectored);
+            mtvec.set_address(_start_trap as usize);
+            mtvec
+        }
+    );
 }}
 
 /// Parse cfg attributes inside a global_asm call.