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Replace some inline ASM with xtensa_lx implementations (#4144)

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* Fix incorrect uses of wsr.intset

* Also use interrupt::clear

* Also replace wsr.vecbase

* Remove cause_sw_intr_to_core from C3/S3
This commit is contained in:
Dániel Buga 2025-09-19 13:52:33 +02:00 committed by GitHub
parent e57530c9b5
commit 83105b4dbb
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GPG Key ID: B5690EEEBB952194
6 changed files with 10 additions and 18 deletions
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2
esp-hal/src/soc/esp32/cpu_control.rs
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@ -286,7 +286,7 @@ impl<'d> CpuControl<'d> {
// set vector table and stack pointer
unsafe {
core::arch::asm!("wsr.vecbase {0}", in(reg) &raw const _init_start, options(nostack));
xtensa_lx::set_vecbase(&raw const _init_start);
xtensa_lx::set_stack_pointer(APP_CORE_STACK_TOP.load(Ordering::Acquire));
}

2
esp-hal/src/soc/esp32s3/cpu_control.rs
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@ -225,7 +225,7 @@ impl<'d> CpuControl<'d> {
// set vector table and stack pointer
unsafe {
core::arch::asm!("wsr.vecbase {0}", in(reg) &raw const _init_start, options(nostack));
xtensa_lx::set_vecbase(&raw const _init_start);
xtensa_lx::set_stack_pointer(APP_CORE_STACK_TOP.load(Ordering::Acquire));
}

6
esp-preempt/src/task/xtensa.rs
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@ -87,14 +87,12 @@ pub(crate) fn setup_multitasking() {
#[cfg_attr(not(esp32), unsafe(export_name = "Software0"))]
#[cfg_attr(esp32, unsafe(export_name = "Software1"))]
fn task_switch_interrupt(context: &mut CpuContext) {
let intr = SW_INTERRUPT;
unsafe { core::arch::asm!("wsr.intclear {0}", in(reg) intr, options(nostack)) };
unsafe { xtensa_lx_rt::xtensa_lx::interrupt::clear(SW_INTERRUPT) };
SCHEDULER.with(|scheduler| scheduler.switch_task(context));
}
#[inline]
pub(crate) fn yield_task() {
let intr = SW_INTERRUPT;
unsafe { core::arch::asm!("wsr.intset {0}", in(reg) intr, options(nostack)) };
unsafe { xtensa_lx::interrupt::set(SW_INTERRUPT) };
}

14
esp-radio/src/ble/btdm.rs
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@ -192,18 +192,12 @@ unsafe extern "C" fn is_in_isr() -> i32 {
crate::is_interrupts_disabled() as i32
}
#[cfg(esp32)]
#[ram]
unsafe extern "C" fn cause_sw_intr_to_core(_core: i32, _intr_no: i32) -> i32 {
#[cfg(any(esp32c3, esp32s3))]
todo!("cause_sw_intr_to_core is not implemented for this target");
#[cfg(esp32)]
{
trace!("cause_sw_intr_to_core {} {}", _core, _intr_no);
let intr = 1 << _intr_no;
unsafe { core::arch::asm!("wsr.intset {0}", in(reg) intr, options(nostack)) };
0
}
trace!("cause_sw_intr_to_core {} {}", _core, _intr_no);
unsafe { xtensa_lx_rt::xtensa_lx::interrupt::set(1 << _intr_no) };
0
}
#[allow(unused)]

2
esp-radio/src/ble/os_adapter_esp32c3.rs
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@ -117,7 +117,7 @@ pub(super) static G_OSI_FUNCS: osi_funcs_s = osi_funcs_s {
task_create: Some(task_create),
task_delete: Some(task_delete),
is_in_isr: Some(is_in_isr),
cause_sw_intr_to_core: Some(cause_sw_intr_to_core),
cause_sw_intr_to_core: None,
malloc: Some(crate::ble::malloc),
malloc_internal: Some(crate::ble::malloc_internal),
free: Some(crate::ble::free),

2
esp-radio/src/ble/os_adapter_esp32s3.rs
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@ -118,7 +118,7 @@ pub(super) static G_OSI_FUNCS: osi_funcs_s = osi_funcs_s {
task_create: Some(task_create),
task_delete: Some(task_delete),
is_in_isr: Some(is_in_isr),
cause_sw_intr_to_core: Some(cause_sw_intr_to_core),
cause_sw_intr_to_core: None,
malloc: Some(crate::ble::malloc),
malloc_internal: Some(crate::ble::malloc_internal),
free: Some(crate::ble::free),