mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-27 04:10:28 +00:00
Miscellaneous cleanup in rtc_cntl module (#4112)
* Define a metadata symbol for SWD * Use `cfg_if` rather than multiple `cfg`s * Eliminate some pointless variable declarations * Make derives match for both versions of `RtcCalSel` * Disallow instantiation of `Rtwdt` or `Swd` outside of `Rtc`
This commit is contained in:
Jesse Braham
GitHub
parent
9c35cf9b16
commit
92bf58f6ec
@ -188,7 +188,7 @@ bitflags::bitflags! {
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}
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}
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/// Clock source to be calibrated using rtc_clk_cal function
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/// Clock source to be calibrated using `rtc_clk_cal` function
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#[allow(unused)]
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#[cfg(not(any(esp32c6, esp32h2)))]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -205,9 +205,10 @@ pub(crate) enum RtcCalSel {
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InternalOsc = 3,
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}
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/// Clock source to be calibrated using rtc_clk_cal function
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#[derive(Debug, Clone, Copy, PartialEq)]
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/// Clock source to be calibrated using `rtc_clk_cal` function
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#[cfg(any(esp32c6, esp32h2))]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
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pub(crate) enum RtcCalSel {
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/// Currently selected RTC SLOW_CLK
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RtcMux = -1,
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@ -229,8 +230,8 @@ pub struct Rtc<'d> {
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_inner: LPWR<'d>,
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/// Reset Watchdog Timer.
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pub rwdt: Rwdt,
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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/// Super Watchdog
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#[cfg(swd)]
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pub swd: Swd,
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}
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@ -241,9 +242,9 @@ impl<'d> Rtc<'d> {
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pub fn new(rtc_cntl: LPWR<'d>) -> Self {
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Self {
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_inner: rtc_cntl,
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rwdt: Rwdt::new(),
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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swd: Swd::new(),
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rwdt: Rwdt(()),
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#[cfg(swd)]
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swd: Swd(()),
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}
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}
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@ -256,35 +257,33 @@ impl<'d> Rtc<'d> {
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fn time_since_boot_raw(&self) -> u64 {
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let rtc_cntl = LP_TIMER::regs();
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#[cfg(esp32)]
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let (l, h) = {
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rtc_cntl.time_update().write(|w| w.time_update().set_bit());
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while rtc_cntl.time_update().read().time_valid().bit_is_clear() {
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// might take 1 RTC slowclk period, don't flood RTC bus
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crate::rom::ets_delay_us(1);
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cfg_if::cfg_if! {
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if #[cfg(esp32)] {
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rtc_cntl.time_update().write(|w| w.time_update().set_bit());
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while rtc_cntl.time_update().read().time_valid().bit_is_clear() {
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// Might take 1 RTC slowclk period, don't flood RTC bus
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crate::rom::ets_delay_us(1);
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}
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let h = rtc_cntl.time1().read().time_hi().bits();
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let l = rtc_cntl.time0().read().time_lo().bits();
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} else if #[cfg(any(esp32c6, esp32h2))] {
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rtc_cntl.update().write(|w| w.main_timer_update().set_bit());
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let h = rtc_cntl
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.main_buf0_high()
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.read()
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.main_timer_buf0_high()
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.bits();
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let l = rtc_cntl.main_buf0_low().read().main_timer_buf0_low().bits();
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} else {
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rtc_cntl.time_update().write(|w| w.time_update().set_bit());
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let h = rtc_cntl.time_high0().read().timer_value0_high().bits();
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let l = rtc_cntl.time_low0().read().timer_value0_low().bits();
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}
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let h = rtc_cntl.time1().read().time_hi().bits();
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let l = rtc_cntl.time0().read().time_lo().bits();
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(l, h)
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};
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#[cfg(any(esp32c2, esp32c3, esp32s2, esp32s3))]
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let (l, h) = {
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rtc_cntl.time_update().write(|w| w.time_update().set_bit());
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let h = rtc_cntl.time_high0().read().timer_value0_high().bits();
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let l = rtc_cntl.time_low0().read().timer_value0_low().bits();
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(l, h)
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};
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#[cfg(any(esp32c6, esp32h2))]
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let (l, h) = {
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rtc_cntl.update().write(|w| w.main_timer_update().set_bit());
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let h = rtc_cntl
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.main_buf0_high()
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.read()
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.main_timer_buf0_high()
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.bits();
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let l = rtc_cntl.main_buf0_low().read().main_timer_buf0_low().bits();
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(l, h)
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};
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}
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((h as u64) << 32) | (l as u64)
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}
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@ -314,10 +313,8 @@ impl<'d> Rtc<'d> {
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let rtc_cntl = LP_AON::regs();
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let (l, h) = (rtc_cntl.store2(), rtc_cntl.store3());
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let l = l.read().bits() as u64;
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let h = h.read().bits() as u64;
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let l = rtc_cntl.store2().read().bits() as u64;
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let h = rtc_cntl.store3().read().bits() as u64;
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// https://github.com/espressif/esp-idf/blob/23e4823f17a8349b5e03536ff7653e3e584c9351/components/newlib/port/esp_time_impl.c#L115
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l + (h << 32)
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@ -330,11 +327,13 @@ impl<'d> Rtc<'d> {
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let rtc_cntl = LP_AON::regs();
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let (l, h) = (rtc_cntl.store2(), rtc_cntl.store3());
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// https://github.com/espressif/esp-idf/blob/23e4823f17a8349b5e03536ff7653e3e584c9351/components/newlib/port/esp_time_impl.c#L102-L103
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l.write(|w| unsafe { w.bits((boot_time_us & 0xffffffff) as u32) });
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h.write(|w| unsafe { w.bits((boot_time_us >> 32) as u32) });
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// https://github.com/espressif/esp-idf/blob/23e4823/components/newlib/port/esp_time_impl.c#L102-L103
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rtc_cntl
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.store2() // Low bits
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.write(|w| unsafe { w.bits((boot_time_us & 0xffff_ffff) as u32) });
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rtc_cntl
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.store3() // High bits
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.write(|w| unsafe { w.bits((boot_time_us >> 32) as u32) });
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}
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#[procmacros::doc_replace]
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@ -446,8 +445,7 @@ impl<'d> Rtc<'d> {
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// ESP32-S3: TRM v1.5 chapter 8.3
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// ESP32-H2: TRM v0.5 chapter 8.2.3
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let rtc_cntl = LP_AON::regs();
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rtc_cntl
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LP_AON::regs()
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.store4()
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.modify(|r, w| unsafe { w.bits(r.bits() | Self::RTC_DISABLE_ROM_LOG) });
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}
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@ -472,6 +470,7 @@ impl<'d> Rtc<'d> {
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unwrap!(interrupt::enable(interrupt, handler.priority()));
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}
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}
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impl crate::private::Sealed for Rtc<'_> {}
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#[instability::unstable]
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@ -515,21 +514,10 @@ pub enum RwdtStage {
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}
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/// RTC Watchdog Timer.
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pub struct Rwdt;
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impl Default for Rwdt {
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fn default() -> Self {
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Self::new()
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}
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}
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pub struct Rwdt(());
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/// RTC Watchdog Timer driver.
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impl Rwdt {
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/// Create a new RTC watchdog timer instance
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pub fn new() -> Self {
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Self
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}
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/// Enable the watchdog timer instance.
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/// Watchdog starts with default settings (`stage 0` resets the system, the
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/// others are deactivated)
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@ -576,37 +564,33 @@ impl Rwdt {
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/// Clear interrupt.
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pub fn clear_interrupt(&mut self) {
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let rtc_cntl = LP_WDT::regs();
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self.set_write_protection(false);
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rtc_cntl.int_clr().write(|w| w.wdt().clear_bit_by_one());
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LP_WDT::regs()
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.int_clr()
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.write(|w| w.wdt().clear_bit_by_one());
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self.set_write_protection(true);
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}
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/// Check if the interrupt is set.
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pub fn is_interrupt_set(&self) -> bool {
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let rtc_cntl = LP_WDT::regs();
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rtc_cntl.int_st().read().wdt().bit_is_set()
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LP_WDT::regs().int_st().read().wdt().bit_is_set()
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}
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/// Feed the watchdog timer.
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pub fn feed(&mut self) {
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let rtc_cntl = LP_WDT::regs();
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self.set_write_protection(false);
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rtc_cntl.wdtfeed().write(|w| w.wdt_feed().set_bit());
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LP_WDT::regs().wdtfeed().write(|w| w.wdt_feed().set_bit());
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self.set_write_protection(true);
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}
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fn set_write_protection(&mut self, enable: bool) {
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let rtc_cntl = LP_WDT::regs();
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let wkey = if enable { 0u32 } else { 0x50D8_3AA1 };
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rtc_cntl.wdtwprotect().write(|w| unsafe { w.bits(wkey) });
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LP_WDT::regs()
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.wdtwprotect()
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.write(|w| unsafe { w.bits(wkey) });
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}
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fn set_enabled(&mut self, enable: bool) {
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@ -666,10 +650,9 @@ impl Rwdt {
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/// Set the action for a specific stage.
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pub fn set_stage_action(&mut self, stage: RwdtStage, action: RwdtStageAction) {
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let rtc_cntl = LP_WDT::regs();
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self.set_write_protection(false);
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rtc_cntl.wdtconfig0().modify(|_, w| unsafe {
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LP_WDT::regs().wdtconfig0().modify(|_, w| unsafe {
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match stage {
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RwdtStage::Stage0 => w.wdt_stg0().bits(action as u8),
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RwdtStage::Stage1 => w.wdt_stg1().bits(action as u8),
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@ -682,18 +665,13 @@ impl Rwdt {
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}
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}
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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/// Super Watchdog
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pub struct Swd;
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#[cfg(swd)]
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pub struct Swd(());
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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/// Super Watchdog driver
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#[cfg(swd)]
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impl Swd {
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/// Create a new super watchdog timer instance
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pub fn new() -> Self {
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Self
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}
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/// Enable the watchdog timer instance
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pub fn enable(&mut self) {
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self.set_enabled(true);
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@ -706,33 +684,24 @@ impl Swd {
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/// Enable/disable write protection for WDT registers
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fn set_write_protection(&mut self, enable: bool) {
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let rtc_cntl = LP_WDT::regs();
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#[cfg(not(any(esp32c6, esp32h2)))]
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let wkey = if enable { 0u32 } else { 0x8F1D_312A };
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#[cfg(any(esp32c6, esp32h2))]
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let wkey = if enable { 0u32 } else { 0x50D8_3AA1 };
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rtc_cntl
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LP_WDT::regs()
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.swd_wprotect()
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.write(|w| unsafe { w.swd_wkey().bits(wkey) });
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}
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fn set_enabled(&mut self, enable: bool) {
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let rtc_cntl = LP_WDT::regs();
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self.set_write_protection(false);
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rtc_cntl
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LP_WDT::regs()
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.swd_conf()
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.write(|w| w.swd_auto_feed_en().bit(!enable));
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self.set_write_protection(true);
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}
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}
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#[cfg(any(esp32c2, esp32c3, esp32c6, esp32h2, esp32s3))]
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impl Default for Swd {
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fn default() -> Self {
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Self::new()
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self.set_write_protection(true);
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}
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}
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@ -749,22 +718,21 @@ pub fn wakeup_cause() -> SleepSource {
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return SleepSource::Undefined;
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}
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#[cfg(any(esp32c6, esp32h2))]
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let wakeup_cause = WakeupReason::from_bits_retain(
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crate::peripherals::PMU::regs()
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.slp_wakeup_status0()
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.read()
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.wakeup_cause()
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.bits(),
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);
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#[cfg(not(any(esp32, esp32c6, esp32h2)))]
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let wakeup_cause = WakeupReason::from_bits_retain(
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LPWR::regs().slp_wakeup_cause().read().wakeup_cause().bits(),
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);
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#[cfg(esp32)]
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let wakeup_cause = WakeupReason::from_bits_retain(
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LPWR::regs().wakeup_state().read().wakeup_cause().bits() as u32,
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);
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cfg_if::cfg_if! {
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if #[cfg(esp32)] {
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let wakeup_cause_bits = LPWR::regs().wakeup_state().read().wakeup_cause().bits() as u32;
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} else if #[cfg(any(esp32c6, esp32h2))] {
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let wakeup_cause_bits = crate::peripherals::PMU::regs()
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.slp_wakeup_status0()
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.read()
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.wakeup_cause()
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.bits();
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} else {
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let wakeup_cause_bits = LPWR::regs().slp_wakeup_cause().read().wakeup_cause().bits();
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}
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}
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let wakeup_cause = WakeupReason::from_bits_retain(wakeup_cause_bits);
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if wakeup_cause.contains(WakeupReason::TimerTrigEn) {
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return SleepSource::Timer;
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@ -502,6 +502,7 @@ impl Chip {
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"soc_has_mem2mem8",
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"gdma",
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"phy",
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"swd",
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"rom_crc_le",
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"rom_crc_be",
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"rom_md5_mbedtls",
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@ -619,6 +620,7 @@ impl Chip {
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"cargo:rustc-cfg=soc_has_mem2mem8",
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"cargo:rustc-cfg=gdma",
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"cargo:rustc-cfg=phy",
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"cargo:rustc-cfg=swd",
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"cargo:rustc-cfg=rom_crc_le",
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"cargo:rustc-cfg=rom_crc_be",
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"cargo:rustc-cfg=rom_md5_mbedtls",
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@ -748,6 +750,7 @@ impl Chip {
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"soc_has_wifi",
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"gdma",
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"phy",
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"swd",
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"rom_crc_le",
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"rom_crc_be",
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"rom_md5_bsd",
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@ -894,6 +897,7 @@ impl Chip {
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"cargo:rustc-cfg=soc_has_wifi",
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"cargo:rustc-cfg=gdma",
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"cargo:rustc-cfg=phy",
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"cargo:rustc-cfg=swd",
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"cargo:rustc-cfg=rom_crc_le",
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"cargo:rustc-cfg=rom_crc_be",
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"cargo:rustc-cfg=rom_md5_bsd",
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@ -1084,6 +1088,7 @@ impl Chip {
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"plic",
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"phy",
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"lp_core",
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"swd",
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"rom_crc_le",
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"rom_crc_be",
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"rom_md5_bsd",
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@ -1287,6 +1292,7 @@ impl Chip {
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"cargo:rustc-cfg=plic",
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"cargo:rustc-cfg=phy",
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"cargo:rustc-cfg=lp_core",
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"cargo:rustc-cfg=swd",
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"cargo:rustc-cfg=rom_crc_le",
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"cargo:rustc-cfg=rom_crc_be",
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"cargo:rustc-cfg=rom_md5_bsd",
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@ -1481,6 +1487,7 @@ impl Chip {
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"gdma",
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"plic",
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"phy",
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"swd",
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"rom_crc_le",
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"rom_crc_be",
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"rom_md5_bsd",
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@ -1658,6 +1665,7 @@ impl Chip {
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"cargo:rustc-cfg=gdma",
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"cargo:rustc-cfg=plic",
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"cargo:rustc-cfg=phy",
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"cargo:rustc-cfg=swd",
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"cargo:rustc-cfg=rom_crc_le",
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"cargo:rustc-cfg=rom_crc_be",
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"cargo:rustc-cfg=rom_md5_bsd",
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@ -2172,6 +2180,7 @@ impl Chip {
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"psram",
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"psram_dma",
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"octal_psram",
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"swd",
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"ulp_riscv_core",
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"rom_crc_le",
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"rom_crc_be",
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@ -2354,6 +2363,7 @@ impl Chip {
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"cargo:rustc-cfg=psram",
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"cargo:rustc-cfg=psram_dma",
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"cargo:rustc-cfg=octal_psram",
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"cargo:rustc-cfg=swd",
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"cargo:rustc-cfg=ulp_riscv_core",
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"cargo:rustc-cfg=rom_crc_le",
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"cargo:rustc-cfg=rom_crc_be",
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@ -2630,6 +2640,7 @@ impl Config {
|
||||
println!("cargo:rustc-check-cfg=cfg(soc_has_mem2mem7)");
|
||||
println!("cargo:rustc-check-cfg=cfg(soc_has_mem2mem8)");
|
||||
println!("cargo:rustc-check-cfg=cfg(gdma)");
|
||||
println!("cargo:rustc-check-cfg=cfg(swd)");
|
||||
println!("cargo:rustc-check-cfg=cfg(rom_md5_mbedtls)");
|
||||
println!("cargo:rustc-check-cfg=cfg(pm_support_wifi_wakeup)");
|
||||
println!("cargo:rustc-check-cfg=cfg(pm_support_bt_wakeup)");
|
||||
|
||||
@ -62,6 +62,7 @@ symbols = [
|
||||
# Additional peripherals defined by us (the developers):
|
||||
"gdma",
|
||||
"phy",
|
||||
"swd",
|
||||
|
||||
# ROM capabilities
|
||||
"rom_crc_le",
|
||||
|
||||
@ -70,6 +70,7 @@ symbols = [
|
||||
# Additional peripherals defined by us (the developers):
|
||||
"gdma",
|
||||
"phy",
|
||||
"swd",
|
||||
|
||||
# ROM capabilities
|
||||
"rom_crc_le",
|
||||
|
||||
@ -110,6 +110,7 @@ symbols = [
|
||||
"plic",
|
||||
"phy",
|
||||
"lp_core",
|
||||
"swd",
|
||||
|
||||
# ROM capabilities
|
||||
"rom_crc_le",
|
||||
|
||||
@ -97,6 +97,7 @@ symbols = [
|
||||
"gdma",
|
||||
"plic",
|
||||
"phy",
|
||||
"swd",
|
||||
|
||||
# ROM capabilities
|
||||
"rom_crc_le",
|
||||
|
||||
@ -90,6 +90,7 @@ symbols = [
|
||||
"psram",
|
||||
"psram_dma",
|
||||
"octal_psram",
|
||||
"swd",
|
||||
"ulp_riscv_core",
|
||||
|
||||
# ROM capabilities
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user