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Adjust ESP32-S2 and ESP32-S3 memory region lengths to reflect those defined in ESP-IDF (#3709)

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* fix(esp-hal/ld): adjust esp32s2 SRAM size from 188K to 184K

* fix(esp-hal/ld): extend esp32s2 heap size from 130.5K to 136K

* fix(esp-hal/ld): reduce esp32s3 SRAM size with 1K

* docs(changelog): add esp-rs#3709 entry
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Gabriel Hansson 2025-07-01 10:17:41 +02:00 committed by GitHub
parent 0e8bc25b70
commit 9eadaa147f
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4 changed files with 7 additions and 7 deletions
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1
esp-hal/CHANGELOG.md
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@ -25,6 +25,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- The RMT `Error` type has been marked `non_exhaustive` (#3701)
- Increase ESP32 DRAM memory region by 16K (#3703)
- The I2C async interrupt handler is now placed into IRAM (#3722)
- Adjusted ESP32-S2 and ESP-S3 memory region lengths to reflect those defined in ESP-IDF. (#3709)
### Fixed

7
esp-hal/ld/esp32s2/memory.x
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@ -16,12 +16,12 @@ VECTORS_SIZE = 0x400;
MEMORY
{
vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES, len = VECTORS_SIZE
iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES + VECTORS_SIZE, len = 188k - RESERVE_CACHES - VECTORS_SIZE
iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES + VECTORS_SIZE, len = 184k - RESERVE_CACHES - VECTORS_SIZE
dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_CACHES + VECTORS_SIZE, len = 188k - RESERVE_CACHES - VECTORS_SIZE
dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_CACHES + VECTORS_SIZE, len = 184k - RESERVE_CACHES - VECTORS_SIZE
/* memory available after the 2nd stage bootloader is finished */
dram2_seg ( RW ) : ORIGIN = ORIGIN(dram_seg) + LENGTH(dram_seg), len = 0x3ffffa10 - (ORIGIN(dram_seg) + LENGTH(dram_seg))
dram2_seg ( RW ) : ORIGIN = ORIGIN(dram_seg) + LENGTH(dram_seg), len = 136K
/* external flash
The 0x20 offset is a convenience for the app binary image generation.
@ -33,7 +33,6 @@ MEMORY
irom_seg ( RX ) : ORIGIN = 0x40080020, len = 3M - 0x20
drom_seg ( R ) : ORIGIN = 0x3F000020, len = 4M - 0x20
/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
rtc_fast_iram_seg(RWX) : ORIGIN = 0x40070000, len = 8k

4
esp-hal/ld/esp32s3/memory.x
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@ -22,10 +22,10 @@ MEMORY
{
vectors_seg ( RX ) : ORIGIN = 0x40370000 + RESERVE_ICACHE, len = VECTORS_SIZE
iram_seg ( RX ) : ORIGIN = 0x40370000 + RESERVE_ICACHE + VECTORS_SIZE, len = 328k - VECTORS_SIZE - RESERVE_ICACHE
dram_seg ( RW ) : ORIGIN = 0x3FC88000 , len = 345856
/* memory available after the 2nd stage bootloader is finished */
dram2_seg ( RW ) : ORIGIN = ORIGIN(dram_seg) + LENGTH(dram_seg), len = 0x3fced710 - (ORIGIN(dram_seg) + LENGTH(dram_seg))
dram2_seg ( RW ) : ORIGIN = 0x3FCDB700, len = 0x3FCED710 - 0x3FCDB700
dram_seg ( RW ) : ORIGIN = 0x3FC88000 , len = ORIGIN(dram2_seg) - 0x3FC88000
/* external flash
The 0x20 offset is a convenience for the app binary image generation.

2
hil-test/tests/stack_protector.rs
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@ -28,7 +28,7 @@ fn trigger_overflow() {
} else if cfg!(esp32h2) {
235 * 1024
} else if cfg!(esp32s2) {
173 * 1024
169 * 1024
} else if cfg!(esp32s3) {
322 * 1024
} else {