mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-28 04:40:52 +00:00
Add direct-boot support for ESP32-S3 (#107)
* Add direct-boot support for ESP32-S3 * Make sure to use correct alignments * Only enable naked_functions and asm_experimental_arch when direct-boot feature is selected
This commit is contained in:
Björn Quentin
GitHub
parent
147d8de988
commit
9fa1d1ecdb
@ -29,6 +29,7 @@ embedded-hal = { version = "0.2", features = ["unproven"] }
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embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.8" }
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xtensa-lx = { version = "0.7", features = ["esp32s3"] }
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xtensa-lx-rt = { version = "0.12", features = ["esp32s3"], optional = true }
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r0 = { version = "1.0.0", optional = true }
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[dependencies.esp-hal-common]
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path = "../esp-hal-common"
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@ -43,6 +44,7 @@ esp-println = { version = "0.2.0", features = ["esp32s3"] }
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[features]
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default = ["rt"]
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direct-boot = ["r0"]
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eh1 = ["esp-hal-common/eh1"]
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rt = ["xtensa-lx-rt/esp32s3"]
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ufmt = ["esp-hal-common/ufmt"]
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@ -1,5 +1,6 @@
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use std::{env, fs::File, io::Write, path::PathBuf};
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#[cfg(not(feature = "direct-boot"))]
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fn main() {
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// Put the linker script somewhere the linker can find it
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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@ -34,3 +35,39 @@ fn main() {
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// instead of when any part of the source code changes.
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println!("cargo:rerun-if-changed=memory.x");
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}
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#[cfg(feature = "direct-boot")]
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fn main() {
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// Put the linker script somewhere the linker can find it
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(include_bytes!("ld/db-memory.x"))
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.unwrap();
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File::create(out.join("alias.x"))
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.unwrap()
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.write_all(include_bytes!("ld/rom.x"))
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.unwrap();
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File::create(out.join("hal-defaults.x"))
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.unwrap()
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.write_all(include_bytes!("ld/hal-defaults.x"))
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.unwrap();
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File::create(out.join("esp32s3.x"))
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.unwrap()
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.write_all(include_bytes!("ld/db-esp32s3.x"))
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.unwrap();
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File::create(out.join("linkall.x"))
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.unwrap()
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.write_all(include_bytes!("ld/linkall.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// Only re-run the build script when memory.x is changed,
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// instead of when any part of the source code changes.
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println!("cargo:rerun-if-changed=memory.x");
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}
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300
esp32s3-hal/ld/db-esp32s3.x
Normal file
300
esp32s3-hal/ld/db-esp32s3.x
Normal file
@ -0,0 +1,300 @@
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/* before memory.x to allow override */
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ENTRY(Reset)
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INCLUDE memory.x
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/* map generic regions to output sections */
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INCLUDE "alias.x"
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_external_ram_start = ABSOLUTE(ORIGIN(psram_seg));
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_external_ram_end = ABSOLUTE(ORIGIN(psram_seg)+LENGTH(psram_seg));
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_heap_end = ABSOLUTE(ORIGIN(dram_seg))+LENGTH(dram_seg)+LENGTH(reserved_for_boot_seg) - 2*STACK_SIZE;
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_text_heap_end = ABSOLUTE(ORIGIN(iram_seg)+LENGTH(iram_seg));
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_external_heap_end = ABSOLUTE(ORIGIN(psram_seg)+LENGTH(psram_seg));
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_stack_start_cpu1 = _heap_end;
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_stack_end_cpu1 = _stack_start_cpu1 + STACK_SIZE;
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_stack_start_cpu0 = _stack_end_cpu1;
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_stack_end_cpu0 = _stack_start_cpu0 + STACK_SIZE;
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EXTERN(DefaultHandler);
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INCLUDE "device.x"
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/* after memory.x to allow override */
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PROVIDE(__pre_init = DefaultPreInit);
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PROVIDE(__zero_bss = default_mem_hook);
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PROVIDE(__init_data = default_mem_hook);
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/*INCLUDE exception.x*/
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/* exception vector for the ESP32, requiring high priority interrupts and register window support */
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/* high level exception/interrupt routines, which can be override with Rust functions */
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PROVIDE(__exception = __default_exception);
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PROVIDE(__user_exception = __default_user_exception);
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PROVIDE(__double_exception = __default_double_exception);
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PROVIDE(__level_1_interrupt = __default_interrupt);
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PROVIDE(__level_2_interrupt = __default_interrupt);
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PROVIDE(__level_3_interrupt = __default_interrupt);
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PROVIDE(__level_4_interrupt = __default_interrupt);
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PROVIDE(__level_5_interrupt = __default_interrupt);
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PROVIDE(__level_6_interrupt = __default_interrupt);
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PROVIDE(__level_7_interrupt = __default_interrupt);
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/* low level exception/interrupt, which must be overridden using naked functions */
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PROVIDE(__naked_user_exception = __default_naked_exception);
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PROVIDE(__naked_kernel_exception = __default_naked_exception);
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PROVIDE(__naked_double_exception = __default_naked_double_exception);
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PROVIDE(__naked_level_2_interrupt = __default_naked_level_2_interrupt);
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PROVIDE(__naked_level_3_interrupt = __default_naked_level_3_interrupt);
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PROVIDE(__naked_level_4_interrupt = __default_naked_level_4_interrupt);
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PROVIDE(__naked_level_5_interrupt = __default_naked_level_5_interrupt);
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PROVIDE(__naked_level_6_interrupt = __default_naked_level_6_interrupt);
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PROVIDE(__naked_level_7_interrupt = __default_naked_level_7_interrupt);
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/* needed to force inclusion of the vectors */
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EXTERN(__default_exception);
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EXTERN(__default_double_exception);
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EXTERN(__default_interrupt);
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EXTERN(__default_naked_exception);
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EXTERN(__default_naked_double_exception);
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EXTERN(__default_naked_level_2_interrupt);
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EXTERN(__default_naked_level_3_interrupt);
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EXTERN(__default_naked_level_4_interrupt);
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EXTERN(__default_naked_level_5_interrupt);
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EXTERN(__default_naked_level_6_interrupt);
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EXTERN(__default_naked_level_7_interrupt);
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SECTIONS {
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.pre_header (NOLOAD) : AT(0)
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{
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. = . + 0x400;
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}
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.header ORIGIN(ROTEXT) : AT(0x400)
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{
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LONG(0xaedb041d)
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LONG(0xaedb041d)
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}
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.text ORIGIN(ROTEXT) + 0x408 : AT(0x408)
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{
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_stext = .;
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. = ALIGN (4);
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_text_start = ABSOLUTE(.);
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. = ALIGN (4);
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KEEP(*(.init));
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*(.literal .text .literal.* .text.*)
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. = ALIGN (4);
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_text_end = ABSOLUTE(.);
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_etext = .;
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}
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_text_size = _etext - _stext;
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.rodata ORIGIN(RODATA) + 0x408 + _text_size : AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header))
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{
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_rodata_start = ABSOLUTE(.);
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. = ALIGN (4);
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*(.rodata .rodata.*)
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. = ALIGN (4);
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_rodata_end = ABSOLUTE(.);
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}
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.rwtext ORIGIN(RWTEXT) + 0x408 + _text_size + SIZEOF(.rodata) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata))
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{
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_irwtext = ORIGIN(RODATA) + 0x408 + _text_size + SIZEOF(.rodata);
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_srwtext = .;
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. = ALIGN (4);
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. = ALIGN(0x1000);
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_init_start = ABSOLUTE(.);
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KEEP(*(.WindowOverflow4.text));
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. = ALIGN(64);
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KEEP(*(.WindowUnderflow4.text));
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. = ALIGN(64);
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KEEP(*(.WindowOverflow8.text));
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. = ALIGN(64);
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KEEP(*(.WindowUnderflow8.text));
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. = ALIGN(64);
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KEEP(*(.WindowOverflow12.text));
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. = ALIGN(64);
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KEEP(*(.WindowUnderflow12.text));
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. = ALIGN(64);
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KEEP(*(.Level2InterruptVector.text));
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. = ALIGN(64);
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KEEP(*(.Level3InterruptVector.text));
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. = ALIGN(64);
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KEEP(*(.Level4InterruptVector.text));
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. = ALIGN(64);
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KEEP(*(.Level5InterruptVector.text));
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. = ALIGN(64);
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KEEP(*(.DebugExceptionVector.text));
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. = ALIGN(64);
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KEEP(*(.NMIExceptionVector.text));
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. = ALIGN(64);
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KEEP(*(.KernelExceptionVector.text));
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. = ALIGN(64);
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KEEP(*(.UserExceptionVector.text));
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. = ALIGN(128);
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KEEP(*(.DoubleExceptionVector.text));
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. = ALIGN(0x400);
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_init_end = ABSOLUTE(.);
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*(.rwtext.literal .rwtext .rwtext.literal.* .rwtext.*)
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. = ALIGN (4);
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_erwtext = .;
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}
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.data ORIGIN(RWDATA) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext))
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{
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_data_start = ABSOLUTE(.);
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. = ALIGN (4);
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*(.data .data.*)
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. = ALIGN (4);
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_data_end = ABSOLUTE(.);
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}
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/* LMA of .data */
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_sidata = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext);
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.bss (NOLOAD) : ALIGN(4)
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{
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_bss_start = ABSOLUTE(.);
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. = ALIGN (4);
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*(.bss .bss.* COMMON)
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. = ALIGN (4);
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_bss_end = ABSOLUTE(.);
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} > RWDATA
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.noinit (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.noinit .noinit.*)
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. = ALIGN (4);
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} > RWDATA
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.rtc_fast.text ORIGIN(rtc_fast_iram_seg) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) )
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{
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. = ALIGN(4);
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_rtc_fast_text_start = ABSOLUTE(.);
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*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
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. = ALIGN(4);
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_rtc_fast_text_end = ABSOLUTE(.);
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}
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_irtc_fast_text = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext);
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.rtc_fast.data ORIGIN(rtc_fast_dram_seg) + SIZEOF(.rtc_fast.text) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.rtc_fast.text) )
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{
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. = ALIGN(4);
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_rtc_fast_data_start = ABSOLUTE(.);
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*(.rtc_fast.data .rtc_fast.data.*)
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. = ALIGN(4);
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_rtc_fast_data_end = ABSOLUTE(.);
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}
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_irtc_fast_data = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) + SIZEOF(.rtc_fast.text);
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.rtc_fast.bss ORIGIN(rtc_fast_dram_seg) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) (NOLOAD) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) +
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SIZEOF(.rwtext) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data))
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{
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. = ALIGN(4);
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_rtc_fast_bss_start = ABSOLUTE(.);
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*(.rtc_fast.bss .rtc_fast.bss.*)
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. = ALIGN (4);
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_rtc_fast_bss_end = ABSOLUTE(.);
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}
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.rtc_fast.noinit ORIGIN(rtc_fast_dram_seg) + SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) (NOLOAD) :
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{
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. = ALIGN(4);
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*(.rtc_fast.noinit .rtc_fast.noinit.*)
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. = ALIGN (4);
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}
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.rtc_slow.text ORIGIN(rtc_slow_seg) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
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SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss))
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{
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. = ALIGN(4);
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_rtc_slow_text_start = ABSOLUTE(.);
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*(.rtc_slow.literal .rtc_slow.text .rtc_slow.literal.* .rtc_slow.text.*)
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. = ALIGN(4);
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_rtc_slow_text_end = ABSOLUTE(.);
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}
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_irtc_slow_text = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
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SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss);
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.rtc_slow.data ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
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SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text))
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{
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. = ALIGN(4);
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_rtc_slow_data_start = ABSOLUTE(.);
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*(.rtc_slow.data .rtc_slow.data.*)
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. = ALIGN(4);
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_rtc_slow_data_end = ABSOLUTE(.);
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}
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_irtc_slow_data = ORIGIN(RODATA) + _text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
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SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text);
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.rtc_slow.bss ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data) (NOLOAD) :
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AT(_text_size + SIZEOF(.header) + SIZEOF(.pre_header) + SIZEOF(.rodata) + SIZEOF(.rwtext) +
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SIZEOF(.rtc_fast.text) + SIZEOF(.rtc_fast.data) + SIZEOF(.rtc_fast.bss) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data))
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{
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. = ALIGN(4);
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_rtc_slow_bss_start = ABSOLUTE(.);
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*(.rtc_slow.bss .rtc_slow.bss.*)
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. = ALIGN (4);
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_rtc_slow_bss_end = ABSOLUTE(.);
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}
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.rtc_slow.noinit ORIGIN(rtc_slow_seg) + SIZEOF(.rtc_slow.text) + SIZEOF(.rtc_slow.data) + SIZEOF(.rtc_slow.bss) (NOLOAD) :
|
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{
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. = ALIGN(4);
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*(.rtc_slow.noinit .rtc_slow.noinit.*)
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. = ALIGN (4);
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}
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.external.data :
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{
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_external_data_start = ABSOLUTE(.);
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. = ALIGN(4);
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*(.external.data .external.data.*)
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. = ALIGN (4);
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_external_data_end = ABSOLUTE(.);
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} > psram_seg AT > RODATA
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.external.bss (NOLOAD) :
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{
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_external_bss_start = ABSOLUTE(.);
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. = ALIGN(4);
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*(.external.bss .external.bss.*)
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. = ALIGN (4);
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_external_bss_end = ABSOLUTE(.);
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} > psram_seg
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.external.noinit (NOLOAD) :
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{
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. = ALIGN(4);
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*(.external.noinit .external.noinit.*)
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. = ALIGN (4);
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} > psram_seg
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/* must be last segment using psram_seg */
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.external_heap_start (NOLOAD) :
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{
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. = ALIGN (4);
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_external_heap_start = ABSOLUTE(.);
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. = ALIGN (4);
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} > psram_seg
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}
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44
esp32s3-hal/ld/db-memory.x
Normal file
44
esp32s3-hal/ld/db-memory.x
Normal file
@ -0,0 +1,44 @@
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/* override entry point */
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ENTRY(ESP32Reset)
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/* reserved at the start of DRAM */
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RESERVE_DRAM = 0x8000;
|
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/* reserved at the start of the RTC memories for use by the ULP processor */
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RESERVE_RTC_FAST = 0;
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RESERVE_RTC_SLOW = 0;
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|
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/* define stack size for both cores */
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STACK_SIZE = 8k;
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|
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/* Specify main memory areas */
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MEMORY
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{
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iram_seg ( RX ) : ORIGIN = 0x40370400 + RESERVE_DRAM, len = 328k - 0x400
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dram_seg ( RW ) : ORIGIN = 0x3FC80000 + RESERVE_DRAM, len = 328k - RESERVE_DRAM
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reserved_for_boot_seg : ORIGIN = 0x3FFDC200, len = 144k /* ???? SRAM1; reserved for static ROM usage; can be used for heap */
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/* external flash
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||||
The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
|
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header. Setting this offset makes it simple to meet the flash cache MMU's
|
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constraint that (paddr % 64KB == vaddr % 64KB).)
|
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*/
|
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irom_seg ( RX ) : ORIGIN = 0x42000000, len = 4M
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drom_seg ( R ) : ORIGIN = 0x3C000000, len = 4M
|
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|
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|
||||
/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
|
||||
rtc_fast_iram_seg(RWX) : ORIGIN = 0x600fe000, len = 8k
|
||||
|
||||
/* RTC fast memory (same block as above), viewed from data bus. Only for core 0 (PRO_CPU) */
|
||||
rtc_fast_dram_seg(RW) : ORIGIN = 0x600fe000 + RESERVE_RTC_FAST, len = 8k - RESERVE_RTC_FAST
|
||||
|
||||
/* RTC slow memory (data accessible). Persists over deep sleep. */
|
||||
rtc_slow_seg(RW) : ORIGIN = 0x50000000 + RESERVE_RTC_SLOW, len = 8k - RESERVE_RTC_SLOW
|
||||
|
||||
/* external memory, including data and text */
|
||||
psram_seg(RWX) : ORIGIN = 0x3F500000, len = 0xA80000 /* ??? */
|
||||
}
|
||||
@ -1,4 +1,6 @@
|
||||
#![no_std]
|
||||
#![cfg_attr(feature = "direct-boot", feature(naked_functions))]
|
||||
#![cfg_attr(feature = "direct-boot", feature(asm_experimental_arch))]
|
||||
|
||||
pub use embedded_hal as ehal;
|
||||
pub use esp_hal_common::{
|
||||
@ -34,6 +36,118 @@ pub mod gpio;
|
||||
#[no_mangle]
|
||||
extern "C" fn DefaultHandler(_level: u32, _interrupt: pac::Interrupt) {}
|
||||
|
||||
#[cfg(all(feature = "rt", feature = "direct-boot"))]
|
||||
#[doc(hidden)]
|
||||
#[no_mangle]
|
||||
#[link_section = ".init"]
|
||||
#[naked]
|
||||
unsafe extern "C" fn init() {
|
||||
core::arch::asm!("call0 startup_direct_boot", options(noreturn));
|
||||
}
|
||||
|
||||
#[cfg(all(feature = "rt", feature = "direct-boot"))]
|
||||
#[doc(hidden)]
|
||||
#[no_mangle]
|
||||
pub unsafe fn startup_direct_boot() -> ! {
|
||||
// These symbols are from `memory.x`
|
||||
extern "C" {
|
||||
static mut _rtc_fast_bss_start: u32;
|
||||
static mut _rtc_fast_bss_end: u32;
|
||||
|
||||
static mut _rtc_slow_bss_start: u32;
|
||||
static mut _rtc_slow_bss_end: u32;
|
||||
|
||||
// Boundaries of the .rtc_fast.text section
|
||||
static mut _rtc_fast_text_start: u32;
|
||||
static mut _rtc_fast_text_end: u32;
|
||||
static mut _irtc_fast_text: u32;
|
||||
|
||||
// Boundaries of the .rtc_fast.data section
|
||||
static mut _rtc_fast_data_start: u32;
|
||||
static mut _rtc_fast_data_end: u32;
|
||||
static mut _irtc_fast_data: u32;
|
||||
|
||||
// Boundaries of the .rtc_slow.text section
|
||||
static mut _rtc_slow_text_start: u32;
|
||||
static mut _rtc_slow_text_end: u32;
|
||||
static mut _irtc_slow_text: u32;
|
||||
|
||||
// Boundaries of the .rtc_slow.data section
|
||||
static mut _rtc_slow_data_start: u32;
|
||||
static mut _rtc_slow_data_end: u32;
|
||||
static mut _irtc_slow_data: u32;
|
||||
|
||||
static mut _stack_end_cpu0: u32;
|
||||
}
|
||||
|
||||
// set stack pointer to end of memory: no need to retain stack up to this point
|
||||
xtensa_lx::set_stack_pointer(&mut _stack_end_cpu0);
|
||||
|
||||
// copy rtc data from flash to destinations
|
||||
r0::init_data(
|
||||
&mut _rtc_fast_data_start,
|
||||
&mut _rtc_fast_data_end,
|
||||
&_irtc_fast_data,
|
||||
);
|
||||
|
||||
r0::init_data(
|
||||
&mut _rtc_fast_text_start,
|
||||
&mut _rtc_fast_text_end,
|
||||
&_irtc_fast_text,
|
||||
);
|
||||
|
||||
r0::init_data(
|
||||
&mut _rtc_slow_data_start,
|
||||
&mut _rtc_slow_data_end,
|
||||
&_irtc_slow_data,
|
||||
);
|
||||
|
||||
r0::init_data(
|
||||
&mut _rtc_slow_text_start,
|
||||
&mut _rtc_slow_text_end,
|
||||
&_irtc_slow_text,
|
||||
);
|
||||
|
||||
// Initialize RTC RAM
|
||||
xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
|
||||
xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
|
||||
|
||||
// first of all copy rwtext
|
||||
extern "C" {
|
||||
// Boundaries of the .iram section
|
||||
static mut _srwtext: u32;
|
||||
static mut _erwtext: u32;
|
||||
static mut _irwtext: u32;
|
||||
}
|
||||
r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
|
||||
|
||||
// do some configurations for compatability with the 2nd stage bootloader
|
||||
// this is a workaround and ideally we should deal with these settings in other
|
||||
// places
|
||||
(&*crate::pac::TIMG0::PTR)
|
||||
.int_ena_timers
|
||||
.modify(|_, w| w.t0_int_ena().set_bit().t1_int_ena().set_bit());
|
||||
(&*crate::pac::TIMG1::PTR)
|
||||
.int_ena_timers
|
||||
.modify(|_, w| w.t0_int_ena().set_bit().t1_int_ena().set_bit());
|
||||
|
||||
(&*crate::pac::RTC_CNTL::PTR)
|
||||
.swd_wprotect
|
||||
.write(|w| w.bits(0x8f1d312a));
|
||||
(&*crate::pac::RTC_CNTL::PTR)
|
||||
.swd_conf
|
||||
.modify(|_, w| w.swd_disable().set_bit());
|
||||
(&*crate::pac::RTC_CNTL::PTR)
|
||||
.swd_wprotect
|
||||
.write(|w| w.bits(0));
|
||||
|
||||
(&*crate::pac::SYSTEM::PTR)
|
||||
.sysclk_conf
|
||||
.modify(|_, w| w.soc_clk_sel().bits(1));
|
||||
|
||||
xtensa_lx_rt::Reset();
|
||||
}
|
||||
|
||||
#[cfg(feature = "rt")]
|
||||
#[doc(hidden)]
|
||||
#[link_section = ".rwtext"]
|
||||
@ -107,7 +221,13 @@ pub unsafe extern "C" fn ESP32Reset() -> ! {
|
||||
#[no_mangle]
|
||||
#[rustfmt::skip]
|
||||
pub extern "Rust" fn __init_data() -> bool {
|
||||
false
|
||||
#[cfg(feature = "direct-boot")]
|
||||
let res = true;
|
||||
|
||||
#[cfg(not(feature = "direct-boot"))]
|
||||
let res = false;
|
||||
|
||||
res
|
||||
}
|
||||
|
||||
fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user