itsscb/esp-hal
1
0
Fork 0
mirror of https://github.com/esp-rs/esp-hal.git synced 2025-10-02 14:44:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

ESP32-C6/H2: UART sync registers and use xtal (#893)

Browse Source 
* ESP32-C6/H2: UART sync registers and use xtal

* CHANGELOG.md entry
This commit is contained in:
Björn Quentin 2023-11-01 15:58:15 +01:00 committed by GitHub
parent 8eddb9e737
commit a13ab2943a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
CHANGELOG.md
View File

@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Fixed ### Fixed
- ESP32-C3: Make sure BLE and WiFi are not powered down when esp-wifi needs them (#891) - ESP32-C3: Make sure BLE and WiFi are not powered down when esp-wifi needs them (#891)
- ESP32-C6/H2: Fix setting UART baud rate (#893)
### Removed ### Removed

14
esp-hal-common/src/uart.rs
View File

@ -721,9 +721,9 @@ where
#[cfg(any(esp32c6, esp32h2))] #[cfg(any(esp32c6, esp32h2))]
fn change_baud(&self, baudrate: u32, clocks: &Clocks) { fn change_baud(&self, baudrate: u32, clocks: &Clocks) {
// we force the clock source to be APB and don't use the decimal part of the // we force the clock source to be XTAL and don't use the decimal part of
// divider // the divider
let clk = clocks.apb_clock.to_Hz(); let clk = clocks.xtal_clock.to_Hz();
let max_div = 0b1111_1111_1111 - 1; let max_div = 0b1111_1111_1111 - 1;
let clk_div = ((clk) + (max_div * baudrate) - 1) / (max_div * baudrate); let clk_div = ((clk) + (max_div * baudrate) - 1) / (max_div * baudrate);
@ -743,7 +743,7 @@ where
.uart0_sclk_div_num() .uart0_sclk_div_num()
.bits(clk_div as u8 - 1) .bits(clk_div as u8 - 1)
.uart0_sclk_sel() .uart0_sclk_sel()
.bits(0x1) // TODO: this probably shouldn't be hard-coded .bits(0x3) // TODO: this probably shouldn't be hard-coded
.uart0_sclk_en() .uart0_sclk_en()
.set_bit() .set_bit()
}); });
@ -760,7 +760,7 @@ where
.uart1_sclk_div_num() .uart1_sclk_div_num()
.bits(clk_div as u8 - 1) .bits(clk_div as u8 - 1)
.uart1_sclk_sel() .uart1_sclk_sel()
.bits(0x1) // TODO: this probably shouldn't be hard-coded .bits(0x3) // TODO: this probably shouldn't be hard-coded
.uart1_sclk_en() .uart1_sclk_en()
.set_bit() .set_bit()
}); });
@ -775,6 +775,8 @@ where
T::register_block() T::register_block()
.clkdiv .clkdiv
.write(|w| unsafe { w.clkdiv().bits(divider).frag().bits(0) }); .write(|w| unsafe { w.clkdiv().bits(divider).frag().bits(0) });
self.sync_regs();
} }
#[cfg(any(esp32, esp32s2))] #[cfg(any(esp32, esp32s2))]
@ -795,7 +797,7 @@ where
#[cfg(any(esp32c6, esp32h2))] // TODO introduce a cfg symbol for this #[cfg(any(esp32c6, esp32h2))] // TODO introduce a cfg symbol for this
#[inline(always)] #[inline(always)]
fn sync_regs(&mut self) { fn sync_regs(&self) {
T::register_block() T::register_block()
.reg_update .reg_update
.modify(|_, w| w.reg_update().set_bit()); .modify(|_, w| w.reg_update().set_bit());