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Correct a number of comments in various examples

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This commit is contained in:
Jesse Braham 2023-05-24 06:04:54 -07:00 committed by Jesse Braham
parent 278ce406b6
commit a92c46f309
14 changed files with 26 additions and 26 deletions
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4
esp32-hal/examples/spi_eh1_device_loopback.rs
View File

@ -38,8 +38,8 @@ fn main() -> ! {
let mut system = peripherals.DPORT.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32 this includes the RTC WDT and the
// TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32-hal/examples/spi_eh1_loopback.rs
View File

@ -36,8 +36,8 @@ fn main() -> ! {
let mut system = peripherals.DPORT.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32 this includes the RTC WDT and the
// TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32-hal/examples/spi_loopback.rs
View File

@ -35,8 +35,8 @@ fn main() -> ! {
let mut system = peripherals.DPORT.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32 this includes the RTC WDT and the
// TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32c2-hal/examples/blinky_erased_pins.rs
View File

@ -22,8 +22,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-C2, this includes the Super WDT,
// the RTC WDT, and the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

2
esp32c6-hal/examples/interrupt_preemption.rs
View File

@ -32,7 +32,7 @@ fn main() -> ! {
let sw_int = system.software_interrupt_control;
let clocks = ClockControl::boot_defaults(clockctrl).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.LP_CLKRST);
let timer_group0 = TimerGroup::new(

2
esp32c6-hal/examples/software_interrupts.rs
View File

@ -32,7 +32,7 @@ fn main() -> ! {
let sw_int = system.software_interrupt_control;
let clocks = ClockControl::boot_defaults(clockctrl).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.LP_CLKRST);
let timer_group0 = TimerGroup::new(

4
esp32s2-hal/examples/spi_eh1_device_loopback.rs
View File

@ -38,8 +38,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S2, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s2-hal/examples/spi_eh1_loopback.rs
View File

@ -36,8 +36,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S2, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s2-hal/examples/spi_loopback.rs
View File

@ -35,8 +35,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S2, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s2-hal/examples/spi_loopback_dma.rs
View File

@ -37,8 +37,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S2, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s3-hal/examples/qspi_flash.rs
View File

@ -38,8 +38,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S3, this includes the RTC WDT, and
// the TIMG WDTs.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s3-hal/examples/spi_eh1_device_loopback.rs
View File

@ -38,8 +38,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S3, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s3-hal/examples/spi_eh1_loopback.rs
View File

@ -36,8 +36,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S3, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,

4
esp32s3-hal/examples/spi_loopback.rs
View File

@ -35,8 +35,8 @@ fn main() -> ! {
let mut system = peripherals.SYSTEM.split();
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
// the RTC WDT, and the TIMG WDTs.
// Disable the watchdog timers. For the ESP32-S3, this includes the RTC WDT, and
// the TIMG WDT.
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
let timer_group0 = TimerGroup::new(
peripherals.TIMG0,