From 468d4a90c5974e1d70a0ab34e7dea165d72a7e89 Mon Sep 17 00:00:00 2001 From: bjoernQ Date: Mon, 22 Aug 2022 11:29:33 +0200 Subject: [PATCH 1/4] Fix IRAM/DRAM overlap for ESP32-S2 --- esp32s2-hal/build.rs | 5 ++ esp32s2-hal/examples/spi_eh1_loopback.rs | 13 ++-- esp32s2-hal/ld/link-esp32s2.x | 83 ++++++++++++++++++++++++ esp32s2-hal/ld/linkall.x | 2 +- esp32s2-hal/ld/memory.x | 10 +-- 5 files changed, 100 insertions(+), 13 deletions(-) create mode 100644 esp32s2-hal/ld/link-esp32s2.x diff --git a/esp32s2-hal/build.rs b/esp32s2-hal/build.rs index ee29e3235..47417e9b1 100644 --- a/esp32s2-hal/build.rs +++ b/esp32s2-hal/build.rs @@ -23,6 +23,11 @@ fn main() { .write_all(include_bytes!("ld/linkall.x")) .unwrap(); + File::create(out.join("link-esp32s2.x")) + .unwrap() + .write_all(include_bytes!("ld/link-esp32s2.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); // Only re-run the build script when memory.x is changed, diff --git a/esp32s2-hal/examples/spi_eh1_loopback.rs b/esp32s2-hal/examples/spi_eh1_loopback.rs index 98c055586..54a76856c 100644 --- a/esp32s2-hal/examples/spi_eh1_loopback.rs +++ b/esp32s2-hal/examples/spi_eh1_loopback.rs @@ -18,6 +18,7 @@ use core::fmt::Write; +use embedded_hal_1::spi::blocking::SpiBus; use esp32s2_hal::{ clock::ClockControl, gpio::IO, @@ -32,8 +33,6 @@ use esp32s2_hal::{ use panic_halt as _; use xtensa_lx_rt::entry; -use embedded_hal_1::spi::blocking::SpiBus; - #[entry] fn main() -> ! { let peripherals = Peripherals::take().unwrap(); @@ -82,18 +81,17 @@ fn main() -> ! { writeln!(serial0, " SUCCESS").unwrap(); delay.delay_ms(250u32); - // --- Asymmetric transfer (Read more than we write) --- write!(serial0, "Starting asymetric transfer (read > write)...").unwrap(); let mut read: [u8; 4] = [0x00; 4]; - SpiBus::transfer(&mut spi, &mut read[0..2], &write[..]).expect("Asymmetric transfer failed"); + SpiBus::transfer(&mut spi, &mut read[0..2], &write[..]) + .expect("Asymmetric transfer failed"); assert_eq!(write[0], read[0]); assert_eq!(read[2], 0x00u8); writeln!(serial0, " SUCCESS").unwrap(); delay.delay_ms(250u32); - // --- Symmetric transfer with huge buffer --- // Only your RAM is the limit! write!(serial0, "Starting huge transfer...").unwrap(); @@ -108,8 +106,8 @@ fn main() -> ! { writeln!(serial0, " SUCCESS").unwrap(); delay.delay_ms(250u32); - - // --- Symmetric transfer with huge buffer in-place (No additional allocation needed) --- + // --- Symmetric transfer with huge buffer in-place (No additional allocation + // needed) --- write!(serial0, "Starting huge transfer (in-place)...").unwrap(); let mut write = [0x55u8; 4096]; for byte in 0..write.len() { @@ -124,4 +122,3 @@ fn main() -> ! { delay.delay_ms(250u32); } } - diff --git a/esp32s2-hal/ld/link-esp32s2.x b/esp32s2-hal/ld/link-esp32s2.x new file mode 100644 index 000000000..6f75ef243 --- /dev/null +++ b/esp32s2-hal/ld/link-esp32s2.x @@ -0,0 +1,83 @@ + +/* before memory.x to allow override */ +ENTRY(Reset) + +INCLUDE memory.x + +/* after memory.x to allow override */ +PROVIDE(__pre_init = DefaultPreInit); +PROVIDE(__zero_bss = default_mem_hook); +PROVIDE(__init_data = default_mem_hook); + +INCLUDE exception.x + +SECTIONS { + .text : ALIGN(4) + { + _stext = .; + . = ALIGN (4); + _text_start = ABSOLUTE(.); + . = ALIGN (4); + *(.literal .text .literal.* .text.*) + _text_end = ABSOLUTE(.); + _etext = .; + } > ROTEXT + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + . = ALIGN (4); + *(.rodata .rodata.*) + _rodata_end = ABSOLUTE(.); + } > RODATA + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + . = ALIGN (4); + *(.data .data.*) + _data_end = ABSOLUTE(.); + } > RWDATA AT > RODATA + + /* LMA of .data */ + _sidata = LOADADDR(.data); + + .bss (NOLOAD) : ALIGN(4) + { + _bss_start = ABSOLUTE(.); + . = ALIGN (4); + *(.bss .bss.* COMMON) + _bss_end = ABSOLUTE(.); + } > RWDATA + + .noinit (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + *(.noinit .noinit.*) + } > RWDATA + + .dram0_reserved_for_data (NOLOAD) : ALIGN(4) + { + . = ORIGIN(RWTEXT) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit); + } > RWTEXT + + .rwtext : ALIGN(4) + { + . = ALIGN (4); + *(.rwtext.literal .rwtext .rwtext.literal.* .rwtext.*) + } > RWTEXT + + /* must be last segment using RWTEXT */ + .text_heap_start (NOLOAD) : ALIGN(4) + { + . = ALIGN (4); + _text_heap_start = ABSOLUTE(.); + } > RWTEXT + + /* must be last segment using RWDATA */ + .heap_start (NOLOAD) : ALIGN(4) + { + . = ALIGN (4); + _heap_start = ABSOLUTE(.); + } > RWDATA +} diff --git a/esp32s2-hal/ld/linkall.x b/esp32s2-hal/ld/linkall.x index f4be5b1ec..a63b70477 100644 --- a/esp32s2-hal/ld/linkall.x +++ b/esp32s2-hal/ld/linkall.x @@ -1,2 +1,2 @@ -INCLUDE "link.x" +INCLUDE "link-esp32s2.x" INCLUDE "hal-defaults.x" diff --git a/esp32s2-hal/ld/memory.x b/esp32s2-hal/ld/memory.x index 423709db4..33ab029c5 100644 --- a/esp32s2-hal/ld/memory.x +++ b/esp32s2-hal/ld/memory.x @@ -11,6 +11,8 @@ ENTRY(ESP32Reset) /* reserved at the start of DRAM */ RESERVE_DRAM = 0x4000; +VECTORS_SIZE = 0x400; + /* reserved at the start of the RTC memories for use by the ULP processor */ RESERVE_RTC_FAST = 0; RESERVE_RTC_SLOW = 0; @@ -21,17 +23,17 @@ STACK_SIZE = 8k; /* Specify main memory areas */ MEMORY { - vectors_seg ( RX ) : ORIGIN = 0x40022000, len = 1k /* SRAM0 */ - iram_seg ( RX ) : ORIGIN = 0x40022400, len = 128k-0x400 /* SRAM0 */ + vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM, len = VECTORS_SIZE /* SRAM0 */ + iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM + VECTORS_SIZE, len = 192 - RESERVE_DRAM - VECTORS_SIZE /* SRAM0 */ - dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM, len = 192k - RESERVE_DRAM + dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM + VECTORS_SIZE, len = 192k - RESERVE_DRAM - VECTORS_SIZE /* SRAM1; reserved for static ROM usage; can be used for heap. Length based on the "_dram0_rtos_reserved_start" symbol from IDF used to delimit the ROM data reserved region: https://github.com/espressif/esp-idf/blob/bcb34ca7aef4e8d3b97d75ad069b960fb1c17c16/components/heap/port/esp32s2/memory_layout.c#L121-L122 */ - reserved_for_boot_seg : ORIGIN = 0x3FFE0000, len = 0x1FA10 + reserved_for_boot_seg : ORIGIN = 0x3ffffa10, len = 0x5f0 /* external flash The 0x20 offset is a convenience for the app binary image generation. From 92d618a8e58d5a4df514658d6f35101ce45b67ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Mon, 22 Aug 2022 15:25:04 +0200 Subject: [PATCH 2/4] Update esp32s2-hal/ld/memory.x Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com> --- esp32s2-hal/ld/memory.x | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp32s2-hal/ld/memory.x b/esp32s2-hal/ld/memory.x index 33ab029c5..62102b2dd 100644 --- a/esp32s2-hal/ld/memory.x +++ b/esp32s2-hal/ld/memory.x @@ -24,7 +24,7 @@ STACK_SIZE = 8k; MEMORY { vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM, len = VECTORS_SIZE /* SRAM0 */ - iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM + VECTORS_SIZE, len = 192 - RESERVE_DRAM - VECTORS_SIZE /* SRAM0 */ + iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM + VECTORS_SIZE, len = 192k - RESERVE_DRAM - VECTORS_SIZE /* SRAM0 */ dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM + VECTORS_SIZE, len = 192k - RESERVE_DRAM - VECTORS_SIZE From 520f8d6f415394bf6c143cdd48fef65fa39dda37 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Mon, 22 Aug 2022 15:25:09 +0200 Subject: [PATCH 3/4] Update esp32s2-hal/ld/link-esp32s2.x Co-authored-by: Gustavo Henrique Nihei <38959758+gustavonihei@users.noreply.github.com> --- esp32s2-hal/ld/link-esp32s2.x | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/esp32s2-hal/ld/link-esp32s2.x b/esp32s2-hal/ld/link-esp32s2.x index 6f75ef243..05b6c444b 100644 --- a/esp32s2-hal/ld/link-esp32s2.x +++ b/esp32s2-hal/ld/link-esp32s2.x @@ -56,7 +56,7 @@ SECTIONS { *(.noinit .noinit.*) } > RWDATA - .dram0_reserved_for_data (NOLOAD) : ALIGN(4) + .iram0_reserved_for_data (NOLOAD) : ALIGN(4) { . = ORIGIN(RWTEXT) + SIZEOF(.data) + SIZEOF(.bss) + SIZEOF(.noinit); } > RWTEXT From b9f59c436ce6a2d939337773b063e61713573aed Mon Sep 17 00:00:00 2001 From: bjoernQ Date: Mon, 22 Aug 2022 15:42:12 +0200 Subject: [PATCH 4/4] Rename RESERVE_DRAM to RESERVE_CACHES, revert change of reserved_for_boot_seg --- esp32s2-hal/ld/memory.x | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/esp32s2-hal/ld/memory.x b/esp32s2-hal/ld/memory.x index 62102b2dd..2e2a50635 100644 --- a/esp32s2-hal/ld/memory.x +++ b/esp32s2-hal/ld/memory.x @@ -8,8 +8,8 @@ /* override entry point */ ENTRY(ESP32Reset) -/* reserved at the start of DRAM */ -RESERVE_DRAM = 0x4000; +/* reserved at the start of DRAM/IRAM */ +RESERVE_CACHES = 0x2000; VECTORS_SIZE = 0x400; @@ -23,17 +23,17 @@ STACK_SIZE = 8k; /* Specify main memory areas */ MEMORY { - vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM, len = VECTORS_SIZE /* SRAM0 */ - iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_DRAM + VECTORS_SIZE, len = 192k - RESERVE_DRAM - VECTORS_SIZE /* SRAM0 */ + vectors_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES, len = VECTORS_SIZE /* SRAM0 */ + iram_seg ( RX ) : ORIGIN = 0x40020000 + RESERVE_CACHES + VECTORS_SIZE, len = 192k - RESERVE_CACHES - VECTORS_SIZE /* SRAM0 */ - dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_DRAM + VECTORS_SIZE, len = 192k - RESERVE_DRAM - VECTORS_SIZE + dram_seg ( RW ) : ORIGIN = 0x3FFB0000 + RESERVE_CACHES + VECTORS_SIZE, len = 192k - RESERVE_CACHES - VECTORS_SIZE /* SRAM1; reserved for static ROM usage; can be used for heap. Length based on the "_dram0_rtos_reserved_start" symbol from IDF used to delimit the ROM data reserved region: https://github.com/espressif/esp-idf/blob/bcb34ca7aef4e8d3b97d75ad069b960fb1c17c16/components/heap/port/esp32s2/memory_layout.c#L121-L122 */ - reserved_for_boot_seg : ORIGIN = 0x3ffffa10, len = 0x5f0 + reserved_for_boot_seg : ORIGIN = 0x3FFE0000, len = 0x1FA10 /* external flash The 0x20 offset is a convenience for the app binary image generation.